November 1992

Philips Semiconductors

Preliminary specification

Horizontal and vertical deflection controller for
VGA/XGA and autosync monitors

TDA4851

FEATURES

VGA operation fully implemented including
alignment-free vertical and E/W amplitude presettings

4th VGA mode easy applicable (XGA, Super VGA)

Autosync operation externally selectable

Low jitter

All adjustments DC-controllable

Alignment-free oscillators

Sync separators for video or horizontal and vertical TTL
sync levels regardless of polarity

Horizontal oscillator with PLL1 for sync and PLL2 for
flyback

Constant vertical and E/W amplitude in autosync
operation

DC-coupling to vertical power amplifier

Internal supply voltage stabilization with excellent ripple
rejection to ensure stable geometrical adjustments

GENERAL DESCRIPTION

The TDA4851 is a monolithic integrated circuit for
economical solutions in VGA/XGA and autosync monitors.
The IC incorporates the complete horizontal and vertical
small signal processing.
VGA-dependent mode detection and settings are
performed on chip. In conjunction with TDA4860/61/65,
or TDA8351 (vertical output circuits) the ICs offer an
extremely advanced system solution.

QUICK REFERENCE DATA

ORDERING INFORMATION

Note

1. SOT146-1; 1996 November 26.

SYMBOL

PARAMETER

MIN. TYP.

MAX.

UNIT

positive supply voltage (pin 1)

9.2

supply current

i sync

AC-coupled composite video signal with negative-going sync
(peak-to-peak value, pin 9)

sync slicing level

120

DC-coupled TTL-compatible horizontal sync signal (peak-to-peak value,
pin 9)

1.7

slicing level

1.2

1.4

1.6

DC-coupled TTL-compatible vertical sync signal (peak-to-peak value,
pin 10)

1.7

slicing level

1.2

1.4

1.6

o V

vertical differential output current (peak-to-peak value, pins 5 and 6)

o H

horizontal sink output current on pin 3

amb

operating ambient temperature range

EXTENDED TYPE

NUMBER

PACKAGE

PINS

PIN POSITION

MATERIAL

CODE

TDA4851

DIL

plastic

SOT146

(1)

November 1992

Philips Semiconductors

Preliminary specification

Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors

TDA4851

PINNING

SYMBOL

PIN

DESCRIPTION

positive supply voltage

FLB

horizontal flyback input

HOR

horizontal output

GND

ground (0 V)

VERT1

vertical output 1; negative-going sawtooth

VERT2

vertical output 2; positive-going sawtooth

MODE

4th mode output and autosync input

CLBL

clamping/blanking pulse output

HVS

horizontal sync/video input

vertical sync input

E/W output (parabola to driver stage)

capacitor for amplitude control

vertical amplitude adjustment input

E/W amplitude adjustment input (parabola)

VOS

vertical oscillator resistor

VOS

vertical oscillator capacitor

PLL1

PLL1 phase

HOS

horizontal oscillator resistor

HOS

horizontal oscillator capacitor

PLL2

PLL2 phase

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

Horizontal sync separator and polarity correction

An AC-coupled video signal or a DC-coupled TTL sync
signal (H only or composite sync) is input on pin 9. Video
signals are clamped with top sync on 1.28 V, and are
sliced at 1.4 V. This results in a fixed absolute slicing level
of 120 mV related to top sync.
DC-coupled TTL sync signals are also sliced at 1.4 V,
however with the clamping circuit in current limitation.
The polarity of the separated sync is detected by internal
integration of the signal, then the polarity is corrected.
The polarity information is fed to the VGA mode detector.
The corrected sync is input signal for the vertical sync
integrator and the PLL1 stage.

Vertical sync separator, polarity correction and
vertical sync integrator

DC-coupled vertical TTL sync signals may be applied to
pin 10. They are sliced at 1.4 V. The polarity of the
separated sync is detected by internal integration, then the
polarity is corrected. The polarity information is fed to the

VGA mode detector. If pin 10 is not used, it must be
connected to ground. The separated V

i sync

signal from

pin10, or the integrated composite sync signal from pin 9
(TTL or video) triggers directly the vertical oscillator.

VGA mode detector and mode output

The three standard VGA modes and a 4th not fixed mode
are decoded by the polarities of the horizontal and the
vertical sync input signals. An external resistor (from V

pin 7) is necessary to match this function. In all three VGA
modes the correct amplitudes are activated. The presence
of the 4th mode is indicated by a HIGH on pin 7. This signal
can be used externally to switch any horizontal or vertical
parameters.

VGA mode detector input

For autosync operation the voltage on pin 7 must be
externally forced to a level of

50 mV. Vertical amplitude

pre-settings for VGA are then inhibited. The delay time
between vertical trigger pulse and the start of vertical
deflection changes from 575

s to 300

s (575

s is

November 1992

Philips Semiconductors

Preliminary specification

Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors

TDA4851

needed for VGA). The vertical amplitude then remains
constant in a frequency range from 50 Hz up to 110 Hz.

Clamping and V-blanking generator

A combined clamping and V-blanking pulse is available on
pin 8 (suitable for the video pre-amplifier TDA4881). The
lower level of 1.9 V is the blanking signal derived from the
vertical blanking pulse from the internal vertical oscillator.
Vertical blanking equals the delay between vertical sync
and start of vertical scan. By this, an optimum blanking is
achieved for VGA/XGA and autosync operation
(selectable via pin 7).
The upper level of 5.4 V is the horizontal clamping pulse
with an internally fixed pulse width of 0.8

s. A monoflop,

which is triggered by the trailing edge of the horizontal
sync pulse, generates this pulse. If composite sync is
applied, one clamping pulse per H-period is generated
during V-sync. The phase of the clamping pulse may
change during V-sync (see Fig.8).

PLL1 phase detector

The phase detector is a standard type using switched
current sources. The middle of the sync is compared with
a fixed point of the oscillator sawtooth voltage. The PLL
filter is connected to pin 17. If composite sync is applied,
the disturbed control voltage is corrected during V-sync
(see Fig.8).

Horizontal oscillator

This oscillator is of the relaxation type and requires a fixed
capacitor of 10 nF at pin 19. By changing the current into
pin 18 the whole frequency range from 13 to 100 kHz can
be covered.
The current can be generated either by a frequency to
voltage converter or by a resistor. A frequency adjustment
may also be added if necessary.
The PLL1 control voltage at pin 17 modulates via a buffer
stage the oscillator thresholds. A high DC-loop gain
ensures a stable phase relationship between horizontal
sync and line flyback pulses.

PLL2 phase detector

This phase detector is similar to the PLL1 phase detector.
Line flyback signals (pin 2) are compared with a fixed point
of the oscillator sawtooth voltage. Delays in the horizontal
deflection circuit are compensated by adjusting the phase
relationship between horizontal sync and horizontal output
pulses.

A certain amount of phase adjustment is possible by
injecting a DC current from an external source into the
PLL2 filter capacitor at pin 20.

Horizontal driver

This open-collector output stage (pin 3) can directly drive
an external driver transistor. The saturation voltage is less
than 300 mV at 20 mA.
To protect the line deflection transistor, the horizontal
output stage does not conduct for V

6.4 V (pin 1).

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of the vertical
amplitude after changes in sync conditions. The
free-running frequency f

is determined by the values of

VOS

and C

VOS

. The recommended values should be

altered marginally only to preserve the excellent linearity
and noise performance. The vertical drive currents I

and

are in relation to the value of R

VOS

Therefore, the oscillator frequency must be determined
only by C

VOS

on pin 16.

To achieve a stabilized amplitude the free-running
frequency f

(without adjustment) must be lower than the

lowest occurring sync frequency. The following
contributions can be assumed:

(for 50 to 110 Hz application)

minimum frequency
offset between f

and the

lowest trigger frequency

10%

spread of IC

spread of R (22 k

)

spread of C (0.1

19%

10.8

VOS

-----------------------------------------------------

Result: f

1.19

----------- Hz

42 Hz

November 1992

Philips Semiconductors

Preliminary specification

Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors

TDA4851

Table 1

VGA modes

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134)

Note to the Limiting Values

1. Equivalent to discharging a 200 pF capacitor through a 0

series resistor.

THERMAL RESISTANCE

MODE

H / V SYNC

POLARITY

FREQUENCY H

(kHz)

FREQUENCY V

(Hz)

NUMBER OF

ACTIVE LINES

MODE OUTPUT

PIN 7

31.45

350

LOW

31.45

400

LOW

31.45

480

LOW

fixed by external circuitry

HIGH

autosync

*/*

fixed by external circuitry

forced to GND

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage (pin 1)

0.5

3,7

voltage on pins 3 and 7

0.5

voltage on pin 8

0.5

voltage on pins 5, 6, 9, 10, 13, 14 and 18

0.5

6.5

current on pin 2

current on pin 3

100

current on pin 7

current on pin 8

stg

storage temperature range

150

amb

operating ambient temperature range

maximum junction temperature

150

ESD

electrostatic handling for all pins (note 1)

400

SYMBOL

PARAMETER

THERMAL RESISTANCE

th j-a

from junction to ambient in free air

65 K/W

November 1992

Philips Semiconductors

Preliminary specification

Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors

TDA4851

CHARACTERISTICS

= 12 V; T

amb

C; measurements taken in Fig.3 unless otherwise specified

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

positive supply voltage (pin 1)

9.2

supply current

1.05 mA

3.388 mA

Internal reference voltage

ref

internal reference voltage

6.0

6.25

6.5

temperature coefficient

amb

20 to

100

-6

PSRR

power supply ripple rejection

f = 1 kHz sinewave

f = 1 MHz sinewave

supply voltage (pin 1) to ensure all
internal reference voltages

9.2

Composite sync input (AC-coupled)

= 5 V

i sync

sync amplitude of video input signal
(pin 9)

sync on green

300

top sync clamping level

1.1

1.28

1.5

slicing level above top sync level

= 50

120

150

allowed source resistance for 7%
duty factor

i sync

200 mV

1.5

differential input resistance

during sync

charging current of coupling capacitor

1.5 V

1.3

int

vertical sync integration time to
generate vertical trigger pulse

= 31 kHz;

1.050 mA

= 64 kHz;

2.169 mA

3.5

6.5

= 100 kHz;

3.388 mA

2.5

3.4

4.5

Horizontal sync input (DC-coupled, TTL-compatible)

i sync

sync input signal
(peak-to-peak value, pin 9)

1.7

slicing level

1.2

1.4

1.6

minimum pulse width

700

rise time and fall time

500

input current

= 0.8 V

200

= 5.5 V

Automatic horizontal polarity switch

H-sync on pin 9

p H

horizontal sync pulse width related to t

(duty factor for automatic polarity
correction)

delay time for changing sync polarity

0.3

1.8

November 1992

Philips Semiconductors

Preliminary specification

Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors

TDA4851

Vertical sync input (DC-coupled, TTL-compatible)

V-sync on pin 10

i sync

sync input signal
(peak-to-peak value, pin 10)

1.7

slicing level

1.2

1.4

1.6

input current

5.5 V

p V

maximum vertical sync pulse width for
automatic vertical polarity switch

300

Horizontal mode detector output

VGA mode

output saturation voltage LOW
(for Modes 1, 2 and 3)

= 6 mA

0.275

0.33

output voltage HIGH

mode 4

load current range to force VGA
mode-dependent vertical and parabola
amplitudes

modes 1, 2 and 3

output current

mode 4

VGA / autosync mode switch

input voltage LOW to force autosync
mode

Horizontal clamping / blanking generator output

Fig.6

output voltage LOW

0.9

blanking output voltage

internal V blanking

1.6

1.9

2.2

clamping output voltage

H-sync on pin 9

5.15

5.4

5.65

internal sink current for all output levels

H and V scanning

2.3

2.9

3.5

external load current

3.0

clamping pulse start

with end of H-sync

clp

clamping pulse width

= 3 V

0.6

0.8

1.0

steepness of rise and fall times

ns/V

Vertical oscillator

ref

= 6.25 V

vertical free-running frequency

= 22 k

;

= 0.1

nominal vertical sync range

no f

adjustment

110

voltage on pin 15

= 22 k

2.8

3.0

3.2

delay between sync pulse and start of
vertical scan

measured on pin 8

in VGA/XGA mode, activated by an
external resistor on pin 7

500

575

650

in autosync mode

50 mV

240

300

360

control current for amplitude control

200

capacitor for amplitude control

0.18

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

November 1992

Philips Semiconductors

Preliminary specification

Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors

TDA4851

Vertical differential output

Fig.7

differential output current between
pins 5 and 6 (peak-to-peak value)

mode 3; I

> -

135

= 22 k

0.9

1.0

1.1

maximum offset-current error

= 1 mA

2.5

maximum linearity error

1.5

Vertical amplitude adjustment (in percentage of output signal)

input voltage

5.0

adjustment current

o max

(100%)

110

120

135

o min

(typically 58%)

VGA mode-dependent pre-settings
activated by an external resistor on pin 7

Table 1; note 1

Mode 1

116.2

116.8

117.4

Mode 2

101.6

102.2

102.8

Mode 3

100

Mode 4

100

autosync operation
(VGA operation disabled)

50 mV

100

Horizontal comparator PLL1

upper control voltage limitation

5.9

lower control voltage limitation

5.1

control current

Fig.6

0.083I

Horizontal oscillator

osc

centre frequency

= 2.4 k

(pin 18);

= 10 nF (pin 19)

31.45

kHz

deviation of centre frequency

temperature coefficient

200

300

-6

relative holding/catching range

6.5

7.3

external oscillator current

0.5

4.3

voltage at reference current input
(pin 18)

2.35

2.5

2.65

Horizontal PLL2

Fig.6

upper clamping level of flyback input

= 6 mA

5.5

lower clamping level of flyback input

1 mA

0.75

H-flyback slicing level

3.0

delay between middle of sync and
middle of H-flyback related to t

3.0

upper control voltage limitation

6.2

lower control voltage limitation

4.8

control current

0.083I

t/t

PLL2 control range related to t

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

November 1992

Philips Semiconductors

Preliminary specification

Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors

TDA4851

Notes to the characteristics

t relative to value of Mode 3.

2. Parabola amplitude tracks with mode-dependent vertical amplitude but not with vertical amplitude adjustment.

Tracking can be achieved by a resistor from vertical amplitude potentiometer to pin 14.

Horizontal output (open-collector)

Fig.6

output voltage LOW

= 20 mA

0.3

= 60 mA

0.8

duty factor

threshold to activate under voltage
protection

horizontal output off

5.6

horizontal output on

5.8

jitter of horizontal output

31 kHz

3.5

64 kHz

1.9

100 kHz

1.2

E/W output

note 2

bottom output signal during mid-scan
(pin 11)

internally stabilized

1.05

1.2

1.35

top output signal during flyback

4.2

4.5

4.8

temperature coefficient of output signal

250

-6

E/W amplitude adjustment (parabola)

Fig.7

input voltage (pin 14)

5.0

adjustment current

100% parabola

110

120

135

typically 28% parabola

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

November 1992

Philips Semiconductors

Preliminary specification

Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors

TDA4851

PACKAGE OUTLINE

UNIT

max.

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT146-1

92-11-17
95-05-24

min.

max.

1.73
1.30

0.53
0.38

0.36
0.23

26.92
26.54

6.40
6.22

3.60
3.05

0.254

2.54

7.62

8.25
7.80

10.0

8.3

2.0

4.2

0.51

3.2

0.068
0.051

0.021
0.015

0.014
0.009

1.060
1.045

0.25
0.24

0.14
0.12

0.01

0.10

0.30

0.32
0.31

0.39
0.33

0.078

0.17

0.020

0.13

SC603

(e )

seating plane

pin 1 index

10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1)

DIP20: plastic dual in-line package; 20 leads (300 mil)

SOT146-1

November 1992

Philips Semiconductors

Preliminary specification

Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors

TDA4851

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Soldering by dipping or by wave

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300

C it may remain in

contact for up to 10 seconds. If the bit temperature is
between 300 and 400

C, contact may be up to 5 seconds.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

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