2003 Feb 05
2
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical
deflection booster
TDA4867J
FEATURES
Fully integrated, few external components
Maximum 2.5 A (p-p) deflection current
No additional components in combination with the
deflection controller family TDA485x and SAA4856
Pre-amplifier with differential high CMRR current mode
inputs
Low offsets
High linear sawtooth signal amplification
High efficient DC-coupled vertical output bridge circuit
High deflection frequency up to 200 Hz
Power supply and flyback supply voltage independent
adjustable to optimize power consumption and flyback
time
Excellent transition behaviour during flyback
Guard circuit for screen protection
Power save mode controlled by input pins
(in combination with SAA4856 only) or guard pin.
GENERAL DESCRIPTION
The TDA4867J is a power booster for use in colour vertical
deflection systems for frame frequencies of 50 to 200 Hz.
The circuit provides a high CMRR current driven
differential input. Due to the bridge configuration of the two
output stages DC-coupling of the deflection coil is
achieved. In conjunction with the deflection controller
family TDA485x and SAA4856 the ICs offer an extremely
advanced system solution.
QUICK REFERENCE DATA
Notes
1. Voltages refer to pin GND.
2. If V
FB
is between 40 and 60 V a decoupling capacitor C
FB
= 22
F (between pin V
FB
and pin GND) and a resistor
R
FB
= 100
(between pin V
FB
and flyback supply voltage) are required (see Fig.6).
3. Differential input current I
i(dif)
= I
INP
-
I
INN
.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DC supplies; note 1
V
P
supply voltage
8.2
-
25
V
V
FB
flyback supply voltage
note 2
V
P
+ 6
-
60
V
I
q(VFB)
quiescent flyback current
no load; no signal
-
2.5
4
mA
Vertical circuit
I
defl(p-p)
deflection current on pins OUTB
and OUTA (peak-to-peak value)
0.6
-
2.5
A
I
i(dif)
differential input current
note 3
-
500
600
A
Flyback generator
I
FB(p-p)
maximum current during flyback on
pin V
FB
(peak-to-peak value)
-
-
2.5
A
Guard circuit; note 1
V
GUARD
guard voltage
guard on
5.5
6.2
-
V
2003 Feb 05
4
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical
deflection booster
TDA4867J
PINNING
FUNCTIONAL DESCRIPTION
The TDA4867J consists of a differential input stage, two
output stages, a flyback generator, a protection circuit for
the output stages and a guard circuit.
Differential input stage
The differential input stage has a high CMRR differential
current mode input (pin INP and pin INN) that results in a
high electromagnetic immunity and is especially suitable
for driver units with differential (e.g. TDA485x or SAA4856)
and single-ended current signals.
The differential input stage delivers the driver signals for
the output stages.
In combination with the SAA4856 the power save mode
can be achieved via the input pins without additional
components.
Output stages
The two output stages are current driven in opposite phase
and operate in combination with the deflection coil in a full
bridge configuration. Therefore, the TDA4867J requires no
external coupling capacitor and operates with one supply
voltage (V
P
) and a separate adjustable flyback supply
voltage (V
FB
) only. The deflection current through the coil
(I
defl
) is measured with the resistor R
m
which produces a
voltage drop: U
rm
R
m
I
defl
. At pin FEEDB a part of I
defl
is fed back to the input stage. The feedback input has a
current input characteristic which holds the differential
voltage between pin FEEDB and pin OUTB on zero.
Therefore the feedback current (I
FEEDB
) through R
ref
is:
The input stage directly compares the driver currents into
pins INP and INN with the half of the feedback current
(I
FEEDB
). Any difference of this comparison leads to a more
or less driver current for the output stages. The relation
between the deflection current and the differential input
current (I
i(dif)
= I
INP
-
I
INN
) is:
or:
The deflection current can be adjusted up to
1.25 A by
varying R
ref
when R
m
is fixed to 1
.
Flyback generator
The flyback generator supplies the output stage A during
flyback. This makes it possible to optimize power
consumption (supply voltage V
P
) and flyback time (flyback
voltage V
FB
) separately. Due to the absence of a
decoupling capacitor the flyback voltage is fully available.
In parallel with the deflection yoke and the damping
resistor (R
p
) an additional capacitor (C
SP
) and a series
resistor (R
SP
) have to be used. The flyback time can be
optimized depending on the value of C
SP
.
SYMBOL
PIN
DESCRIPTION
INP
1
non-inverted input
INN
2
inverted input
V
P
3
supply voltage
OUTB
4
output B
GND
5
ground
OUTA
6
output A
V
FB
7
flyback supply voltage
GUARD
8
guard output or power save
mode input
FEEDB
9
feedback input
handbook, halfpage
TDA4867J
MGU989
1
2
3
4
5
6
7
8
9
INP
INN
VP
OUTB
GND
OUTA
VFB
GUARD
FEEDB
Fig.2 Pin configuration.
I
FEEDB
R
m
R
ref
----------
I
defl
I
i dif
(
)
2
I
FEEDB
R
m
R
ref
----------
I
defl
2
=
I
defl
I
i dif
(
)
R
ref
2
R
m
-----------------
2003 Feb 05
5
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical
deflection booster
TDA4867J
Protection
The output stages are protected against:
Thermal overshoot in normal operation
Short-circuit of the coil (pins OUTB and OUTA).
Guard circuit
The internal guard circuit provides a blanking signal for the
CRT. The guard signal is active HIGH:
At thermal overshoot
During flyback
When missing flyback supply voltage
When power supply voltage too low, V
P
< V
P(min)
.
The internal guard circuit will not be activated, if the input
signals on pins INP and INN delivered from the driver
circuit are out of range or at short-circuit of the coil
(pins OUTB and OUTA).
For this reason an external guard circuit can be applied to
detect failures of the deflection (see Fig.5). This circuit will
be activated when flyback pulses are missing, which is the
indication of any abnormal operation.
The guard output pin can be used as input for the power
save mode. A current or a voltage has to be applied to the
pin. In this case the output stages are switched off
completely.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages referenced to ground (pin GND);
unless otherwise specified.
Notes
1. Maximum output currents I
OUTB
and I
OUTA
are limited by current protection.
2. Internally limited by thermal protection; will be activated for T
j
150
C.
3. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k
resistor.
4. Machine model: equivalent to discharging a 200 pF capacitor through a 0.75
H inductance.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
P
supply voltage
0
30
V
V
FB
flyback supply voltage
0
60
V
I
FB
flyback supply current
0
1.8
A
V
INP
, V
INN
input voltage
0
5
V
I
INP
, I
INN
input current
0
5
mA
V
OUTB
output voltage on pin OUTB
0
V
P
V
V
OUTA
output voltage on pin OUTA
0
V
FB
V
I
OUTB
, I
OUTA
output current
note 1
0
1.6
A
V
FEEDB
feedback voltage
0
V
P
V
I
FEEDB
feedback current
0
5
mA
V
GUARD
guard voltage
0
10
V
I
GUARD
guard current
0
5
mA
T
stg
storage temperature
-
20
+150
C
T
amb
ambient temperature
-
20
+75
C
T
j
junction temperature
note 2
-
20
+150
C
V
esd
electrostatic discharge voltage
note 3
-
4000
+4000
V
note 4
-
250
+250
V
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