2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

CONTENTS

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

8.1

Power supply

8.2

Voltage supervisor

8.2.1

Without external divider on pin PORADJ
(or with TDA8024AT)

8.2.2

With an external divider on pin PORADJ (not
for the TDA8024AT)

8.2.3

Application examples

8.3

Clock circuitry

8.4

I/O transceivers

8.5

Inactive mode

8.6

Activation sequence

8.7

Active mode

8.8

Deactivation sequence

8.9

generator

8.10

Fault detection

LIMITING VALUES

HANDLING

THERMAL CHARACTERISTICS

CHARACTERISTICS

APPLICATION INFORMATION

PACKAGE OUTLINES

SOLDERING

15.1

Introduction to soldering surface mount
packages

15.2

Reflow soldering

15.3

Wave soldering

15.4

Manual soldering

15.5

Suitability of surface mount IC packages for
wave and reflow soldering methods

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

FEATURES

IC card interface

3 or 5 V supply for the IC (V

and GND)

Three specifically protected half-duplex bidirectional
buffered I/O lines to card contacts C4, C7 and C8

DC/DC converter for V

generation separately

powered from a 5 V

20% supply (V

DDP

and PGND)

3 or 5 V

5% regulated card supply voltage (V

) with

appropriate decoupling has the following capabilities:

< 80 mA at V

DDP

= 4 to 6.5 V

Handles current spikes of 40 nAs up to 20 MHz

Controls rise and fall times

Filtered overload detection at approximately 120 mA

Thermal and short-circuit protection on all card contacts

Automatic activation and deactivation sequences;
initiated by software or by hardware in the event of a
short-circuit, card take-off, overheating, V

or V

DDP

drop-out

Enhanced ESD protection on card side (>6 kV)

26 MHz integrated crystal oscillator

Clock generation for cards up to 20 MHz (divided by
1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals)
with synchronous frequency changes

Non-inverted control of RST via pin RSTIN

ISO 7816, GSM11.11 and EMV (payment systems)
compatibility

Supply supervisor for spike-killing during power-on and
power-off and Power-on reset (threshold fixed internally
or externally by a resistor bridge); not for TDA8024AT

Built-in debounce on card presence contacts

One multiplexed status signal OFF.

APPLICATIONS

IC card readers for banking

Electronic payment

Identification

Pay TV.

GENERAL DESCRIPTION

The TDA8024 is a complete and cost-efficient analog
interface for asynchronous 3 or 5 V smart cards. It can be
placed between the card and the microcontroller to
perform all supply, protection and control functions. Very
few external components are required. The TDA8024AT is
a direct replacement for the TDA8004AT.

More information can be obtained from the Philips Internet
site (http://www.semiconductors.philips.com) and from
"Application note AN10141".

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8024T

SO28

plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

TDA8024AT

SO28

plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

TDA8024TT

TSSOP28

plastic thin shrink small outline package; 28 leads; body width 4.4 mm

SOT361-1

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Power supplies

supply voltage

2.7

6.5

DDP

DC/DC converter supply
voltage

= 5 V;

< 80 mA

4.0

5.0

6.5

= 5 V;

< 20 mA

3.0

6.5

supply current

= 3.3 V; f

XTAL

= 10 MHz

card inactive

1.2

card active; f

CLK

= f

XTAL

;

= 30 pF

1.5

DDP

DC/DC converter supply
current

DDP

= 5 V; f

XTAL

= 10 MHz

inactive mode

0.1

active mode; f

CLK

= f

XTAL

;

= 30 pF;

= 0

Card supply

card supply voltage (including
ripple voltage)

5 V card

card active;

< 80 mA DC

4.75

5.0

5.25

card active; current pulses
I

= 40 nAs

4.65

5.0

5.25

3 V card

card active;

< 65 mA DC

2.85

3.0

3.15

card active; current pulses
I

= 40 nAs

2.76

3.0

3.20

CC(ripple)(p-p)

ripple voltage on V

(peak-to-peak value)

ripple

= 20 kHz to 200 MHz

350

card supply current

= 0 to 5 V

= 0 to 3 V

General

deactivation time

100

tot

total power dissipation

continuous operation;
T

amb

25 to +85

0.56

amb

ambient temperature

+85

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

BLOCK DIAGRAM

mdb051

100 nF

I/O

TRANSCEIVER

I/O

TRANSCEIVER

I/O

TRANSCEIVER

THERMAL

PROTECTION

GENERATOR

RST

BUFFER

CLOCK

BUFFER

SEQUENCER

CLOCK

CIRCUITRY

OSCILLATOR

HORSEQ

INTERNAL OSCILLATOR

2.5 MHz

DC/DC CONVERTER

INTERNAL

REFERENCE

VOLTAGE SENSE

SUPPLY

EN2

EN5

EN4

EN3

CLK

EN1 CLKUP

ALARM

ref

DDP

4 PGND

17 V

RST

CGND

PRES

CLK

AUX1

AUX2

I/O

GND

I/OUC

AUX2UC

AUX1UC

(1)

XTAL2

XTAL1

CLKDIV2

CLKDIV1

5V/3V

CMDVCC

RSTIN

OFF

TDA8024

POWER_ON

PORADJ

Fig.1 Block diagram.

(1) Optional external resistor bridge. If this bridge is not required pin 18 should be connected to ground; see Section 8.2.2. Pin 18 is not connected

in the TDA8024AT.

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

PINNING

Note

1. The noise margin on V

will be higher with the 220 nF capacitor.

SYMBOL

PIN

TYPE

DESCRIPTION

CLKDIV1

CLK frequency selection input 1

CLKDIV2

CLK frequency selection input 2

5V/3V

card supply voltage selection input; V

= 5 V (HIGH) or V

= 3 V (LOW)

PGND

DC/DC converter power supply ground

I/O

DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 m

DDP

DC/DC converter power supply voltage

I/O

DC/DC converter capacitor; connected between pins S1 and S2; C = 100 nF with
ESR < 100 m

I/O

DC/DC converter output decoupling capacitor connection; C = 100 nF with
ESR < 100 mW must be connected between V

and PGND

PRES

card presence contact input (active LOW); if PRES or PRES is active, the card is
considered `present' and a built-in debounce feature of 8 ms (typ.) is activated

PRES

card presence contact input (active HIGH); if PRES or PRES is active, the card is
considered `present' and a built-in debounce feature of 8 ms (typ.) is activated

I/O

data line to/from card reader contact C7; integrated 11 k

pull-up resistor to V

AUX2

I/O

data line to/from card reader contact C8; integrated 11 k

pull-up resistor to V

AUX1

I/O

data line to/from card reader contact C4; integrated 11 k

pull-up resistor to V

CGND

card signal ground

CLK

I/O

card clock to/from card reader contact C3

RST

card reset output from card reader contact C2

card supply voltage to card reader contact C1; decoupled to CGND via 2

100 nF

or 100 + 220 nF capacitors with ESR < 100 m

; note 1

PORADJ

Power-on reset threshold adjustment input for changing the reset threshold with
an external resistor bridge; doubles the width of the POR pulse when used; this
pin is not connected for the TDA8024AT

CMDVCC

input from the host to start activation sequence (active LOW)

RSTIN

card reset input from the host

supply voltage

GND

ground

OFF

NMOS interrupt output to the host (active LOW); 20 k

integrated pull-up resistor

to V

XTAL1

crystal connection or input for external clock

XTAL2

crystal connection (leave open-circuit if external clock source is used)

I/OUC

I/O

host data I/O line; integrated 11 k

pull-up resistor to V

AUX1UC

I/O

auxiliary data line to/from the host; integrated 11 k

pull-up resistor to V

AUX2UC

I/O

auxiliary data line to/from the host; integrated 11 k

pull-up resistor to V

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

TDA8024T

CLKDIV1

AUX2UC

CLKDIV2

AUX1UC

5V/3V

I/OUC

PGND

XTAL2

XTAL1

DDP

OFF

GND

PRES

RSTIN

PRES

CMDVCC

I/O

PORADJ

AUX2

AUX1

RST

CGND

CLK

001aab430

Fig.2 Pin configuration TDA8024T.

TDA8024TT

CLKDIV1

AUX2UC

CLKDIV2

AUX1UC

5V/3V

I/OUC

PGND

XTAL2

XTAL1

DDP

OFF

GND

PRES

RSTIN

PRES

CMDVCC

I/O

PORADJ

AUX2

AUX1

RST

CGND

CLK

001aab431

Fig.3 Pin configuration TDA8024TT.

TDA8024AT

CLKDIV1

AUX2UC

CLKDIV2

AUX1UC

5V/3V

I/OUC

PGND

XTAL2

XTAL1

DDP

OFF

GND

PRES

RSTIN

PRES

CMDVCC

I/O

n.c.

AUX2

AUX1

RST

CGND

CLK

001aab382

Fig.4 Pin configuration TDA8024AT.

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

FUNCTIONAL DESCRIPTION

Throughout this document it is assumed that the reader is
familiar with ISO7816 terminology.

8.1

Power supply

The supply pins for the IC are V

and GND. V

should

be in the range of 2.7 to 6.5 V. All signals interfacing with
the system controller are referred to V

, therefore V

should also supply the system controller. All card reader
contacts remain inactive during power-on or power-off.

The internal circuits are maintained in the reset state until
V

reaches V

th2

+ V

hys2

and for the duration of the

internal Power-on reset pulse, t

(see Fig.5). When V

falls below V

th2

, an automatic deactivation of the contacts

is performed.

A DC/DC converter is incorporated to generate the
5 or 3 V card supply voltage (V

). The DC/DC converter

should be supplied separately by V

DDP

and PGND. Due to

the possibility of large transient currents, the two 100 nF
capacitors of the DC/DC converter should be located as
near as possible to the IC and have an ESR less than
100 m

The DC/DC converter functions as a voltage doubler or a
voltage follower according to the respective values of V

and V

DDP

(both have thresholds with a hysteresis of

100 mV).

The DC/DC converter function changes as follows:

= 5 V and V

DDP

> 5.8 V; voltage follower

= 5 V and V

DDP

< 5.7 V; voltage doubler

= 3 V and V

DDP

> 4.1 V; voltage follower

= 3 V and V

DDP

< 4.0 V; voltage doubler.

Supply voltages V

and V

DDP

may be applied to the IC in

any sequence.

After powering the device, OFF remains LOW until
CMDVCC is set HIGH.

During power off, OFF falls LOW when V

is below the

falling threshold voltage.

8.2

Voltage supervisor

8.2.1

ITHOUT EXTERNAL DIVIDER ON PIN

PORADJ

(

OR WITH

TDA8024AT)

The voltage supervisor surveys the V

supply. A defined

reset pulse of approximately 8 ms (t

) is used internally to

keep the IC inactive during power-on or power-off of the
V

supply (see Fig.5).

As long as V

is less than V

th2

+ V

hys2

, the IC remains

inactive whatever the levels on the command lines. This
state also lasts for the duration of t

after V

has reached

a level higher than V

th2

+ V

hys2

When V

falls below V

th2

, a deactivation sequence of the

contacts is performed.

handbook, full pagewidth

Vth2

Vhys2

VDD

Vth2

ALARM

(internal signal)

supply dropout

power-off

power-on

MDB053

Fig.5 Voltage supervisor.

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

8.2.2

ITH AN EXTERNAL DIVIDER ON PIN

PORADJ (

NOT

FOR THE

TDA8024AT)

If an external resistor bridge is connected to pin PORADJ
(R1 and R2 in Fig.1), then the following occurs:

The internal threshold voltage V

th2

is overridden by the

external voltage and by the hysteresis, therefore:

where V

bridge

= 1.25 V typ. and V

hys(ext)

= 60 mV typ.

The reset pulse width t

is doubled to approximately

16 ms.

Input PORADJ is biased internally with a pull-down current
source of 4

A which is removed when the voltage on

pin PORADJ exceeds 1 V. This ensures that after
detection of the external bridge by the IC during power-on,
the input current on pin PORADJ does not cause
inaccuracy of the bridge voltage.

The minimum threshold voltage should be higher than 2 V.

The maximum threshold voltage may be up to V

8.2.3

PPLICATION EXAMPLES

The voltage supervisor is used as Power-on reset and as
supply dropout detection during a card session.

Supply dropout detection is to ensure that a proper
deactivation sequence is followed before the voltage is too
low.

For the internal voltage supervisor to function, the system
microcontroller should operate down to 2.35 V to ensure a
proper deactivation sequence. If this is not possible,
external resistor values can be chosen to overcome the
problem.

8.2.3.1

Microcontroller requiring a 3.3 V

20% supply

For a microcontroller supplied by 3.3 V with a

regulator and with resistors R1, R2 having a

tolerance, the minimum supply voltage is 3.135 V.

PORADJ

= k

, where

with S1 and S2

the actual values of nominal resistors R1 and R2.

This can be shown as

0.99

R1 < S1 < 1.01

R1 and

0.99

R2 < S2 < 1.01

Transposed, this becomes

If V1 = V

th(ext)(rise)(max)

and V2 = V

th(ext)(fall)(min)

activation will always be possible if V

PORADJ

> V1

and deactivation will always be done for V

PORADJ

< V2.

Activation is always possible for

and deactivation is always possible for

That is V1 = 1.31 V and V2 = 1.19 V

and

Suppose R1 + R2 = 100 k

, then

= 42.3 k

and R1 = 57.7 k

Deactivation will be effective at
V2

(1 + 1.02

1.365) = 2.847 V in any case.

If the microcontroller continues to function down to 2.80 V,
the slew rate on V

should be less than 2 V/ms to ensure

that clock CLK is correctly delivered to the card until
time t

(see Fig.9).

8.2.3.2

Microcontroller requiring a 3.3 V

10% supply

For a microcontroller supplied by a 3.3 V with a

regulator and with resistors R1, R2 having a

0.1%

tolerance, the minimum supply voltage is 3.267 V.

The same calculations as in Section 8.2.3.1 conclude:

Therefore

= 40.14 k

and R1 = 59.86 k

Deactivation will be effective at
V2

(1 + 1.002

1.491) = 2.967 V in any case.

If the microcontroller continues to function down to 2.97 V,
the slew rate on V

should be less than 0.20 V/ms to

ensure that clock CLK is correctly delivered to the card
until time t

(see Fig.9).

th2(ext)(rise)

R1
R2

-------

bridge

hys(ext)

--------------------

th2(ext)(fall)

R1
R2

-------

bridge

hys(ext)

--------------------

---------------------

0.98

R1
R2

-------

0.99
1.01

-----------

--------

1
k

---

1
k

---

1.01
0.99

-----------

R1
R2

-------

1.02

R1
R2

-------

R1
R2

-------

3.135

1.31

---------------

0.98

1.365

100 k

2.365

-------------------

R1
R2

-------

3.267
1.310

---------------

0.998

1.491

100 k

2.49

-------------------

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

8.3

Clock circuitry

The card clock signal (CLK) is derived from a clock signal
input to pin XTAL1 or from a crystal operating at up to
26 MHz connected between pins XTAL1 and XTAL2.

The clock frequency can be f

XTAL

. Frequency selection is made via

inputs CLKDIV1 and CLKDIV2 (see Table 1).

Table 1

Clock frequency selection; note 1

Note

1. The status of pins CLKDIV1 and CLKDIV2 must not be

changed simultaneously; a delay of 10 ns minimum
between changes is needed; the minimum duration of
any state of CLK is eight periods of XTAL1.

The frequency change is synchronous, which means that
during transition no pulse is shorter than 45% of the
smallest period, and that the first and last clock pulses
about the instant of change have the correct width.

When changing the frequency dynamically, the change is
effective for only eight periods of XTAL1 after the
command.

The duty factor of f

XTAL

depends on the signal present at

pin XTAL1.

In order to reach a 45 to 55% duty factor on pin CLK, the
input signal on pin XTAL1 should have a duty factor of
48 to 52% and transition times of less than 5% of the input
signal period.

If a crystal is used, the duty factor on pin CLK may be
45 to 55% depending on the circuit layout and on the
crystal characteristics and frequency.

In other cases, the duty factor on pin CLK is guaranteed
between 45 and 55% of the clock period.

The crystal oscillator runs as soon as the IC is powered up.
If the crystal oscillator is used, or if the clock pulse on
pin XTAL1 is permanent, the clock pulse is applied to the
card as shown in the activation sequences shown in Figs 7
and 8.

If the signal applied to XTAL1 is controlled by the system
microcontroller, the clock pulse will be applied to the card
when it is sent by the system microcontroller (after
completion of the activation sequence).

8.4

I/O transceivers

The three data lines I/O, AUX1 and AUX2 are identical.

The idle state is realized by both I/O and I/OUC lines being
pulled HIGH via a 11 k

resistor (I/O to V

and I/OUC to

Pin I/O is referenced to V

, and pin I/OUC to V

, thus

allowing operation when V

is not equal to V

The first side of the transceiver to receive a falling edge
becomes the master. An anti-latch circuit disables the
detection of falling edges on the line of the other side,
which then becomes a slave.

After a time delay t

d(edge)

, an N transistor on the slave side

is turned on, thus transmitting the logic 0 present on the
master side.

When the master side returns to logic 1, a P transistor on
the slave side is turned on during the time delay t

and

then both sides return to their idle states.

This active pull-up feature ensures fast LOW-to-HIGH
transitions; as shown in Fig.6, it is able to deliver more than
1 mA at an output voltage of up to 0.9V

into an 80 pF

load. At the end of the active pull-up pulse, the output
voltage depends only on the internal pull-up resistor and
the load current.

The current to and from the card I/O lines is limited
internally to 15 mA and the maximum frequency on these
lines is 1 MHz.

CLKDIV1

CLKDIV2

CLK

XTAL

-------------

XTAL

-------------

XTAL

-------------

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

8.5

Inactive mode

After a Power-on reset, the circuit enters the inactive
mode. A minimum number of circuits are active while
waiting for the microcontroller to start a session:

All card contacts are inactive (approximately 200

GND)

Pins I/OUC, AUX1UC and AUX2UC are in the
high-impedance state (11 k

pull-up resistor to V

)

Voltage generators are stopped

XTAL oscillator is running

Voltage supervisor is active

The internal oscillator is running at its low frequency.

8.6

Activation sequence

After power-on and after the internal pulse width delay, the
system microcontroller can check the presence of a card
using the signals OFF and CMDVCC as shown in Table 2.

Table 2

Card presence indication

If the card is in the reader (this is the case if PRES or
PRES is active), the system microcontroller can start a
card session by pulling CMDVCC LOW. The following
sequence then occurs (see Fig.6):

1. CMDVCC is pulled LOW and the internal oscillator

changes to its high frequency (t

2. The voltage doubler is started (between t

and t

3. V

rises from 0 to 5 V (or 3 V) with a controlled slope

= t

+ 1.5

T) where T is 64 times the period of the

internal oscillator (approximately 25

s).

4. I/O, AUX1 and AUX2 are enabled (t

= t

+ 4T) (these

were pulled LOW until this moment).

5. CLK is applied to the C3 contact of the card reader (t

6. RST is enabled (t

= t

+ 7T).

The clock may be applied to the card using the following
sequence:

1. Set RSTIN HIGH.

2. Set CMDVCC LOW.

3. Reset RSTIN LOW between t

and t

; CLK will start at

this moment.

4. RST remains LOW until t

, when RST is enabled to be

the copy of RSTIN.

5. After t

, RSTIN has no further affect on CLK; this

allows a precise count of CLK pulses before toggling
RST.

If the applied clock is not needed, then CMDVCC may be
set LOW with RSTIN LOW. In this case, CLK will start at t

(minimum 200 ns after the transition on I/O), and after t

RSTIN may be set HIGH in order to obtain an Answer To
Request (ATR) from the card.

Activation should not be performed with RSTIN held
permanently HIGH.

(2)

(1)

t (ns)

(V)

(mA)

FCE661

Fig.6

I/O, AUX1 and AUX2 output voltage and
current as functions of time during a
LOW-to-HIGH transition.

(1) Current.

(2) Voltage.

OFF

CMDVCC

INDICATION

HIGH

card present

LOW

HIGH

card not present

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

8.7

Active mode

When the activation sequence is completed, the TDA8024
will be in its active mode. Data is exchanged between the
card and the microcontroller via the I/O lines. The
TDA8024 is designed for cards without V

(the voltage

required to program or erase the internal non-volatile
memory).

8.8

Deactivation sequence

When a session is completed, the microcontroller sets the
CMDVCC line HIGH. The circuit then executes an
automatic deactivation sequence by counting the
sequencer back and finishing in the inactive mode (see
Fig.9):

1. RST goes LOW (t

2. CLK is held LOW (t

= t

+ 0.5

T) where T is 64

times the period of the internal oscillator
(approximately 25

s).

3. I/O, AUX1 and AUX2 are pulled LOW (t

= t

+ T).

4. V

starts to fall towards zero (t

= t

+ 1.5

T).

5. The deactivation sequence is complete at t

, when

reaches its inactive state.

6. V

falls to zero (t

= t

+ 5T) and all card contacts

become low-impedance to GND; I/OUC, AUX1UC and
AUX2UC remain at V

(pulled-up via a 11 k

resistor).

7. The internal oscillator returns to its lower frequency.

handbook, full pagewidth

RST

CMDVCC

CLK

I/O

VUP

VCC

t15

t14

t13

t12

MDB056

tde

t10

Fig.9 Deactivation sequence.

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

8.9

generator

The V

generator has a capacity to supply up to 80 mA

continuously at 5 V and 65 mA at 3 V.

An internal overload detector operates at approximately
120 mA. Current samples to the detector are internally
filtered, allowing spurious current pulses up to 200 mA
with a duration in the order of

s to be drawn by the card

without causing deactivation. The average current must
stay below the specified maximum current value.

For reasons of V

voltage accuracy, a 100 nF capacitor

with an ESR < 100 m

should be tied to CGND near to

pin V

, and a 100 or 220 nF capacitor (220 nF is the best

choice) with the same ESR should be tied to CGND near
card reader contact C1.

8.10

Fault detection

The following fault conditions are monitored:

Short-circuit or high current on V

Removal of a card during a transaction

dropping

DC/DC converter operating out of the specified values
(V

DDP

too low or current from V

too high)

Overheating.

There are two different cases (see Fig.10):

CMDVCC HIGH outside a card session. Output OFF
is LOW if a card is not in the card reader, and HIGH if a
card is in the reader. A voltage drop on the V

supply

is detected by the supply supervisor, this generates an
internal Power-on reset pulse but does not act upon
OFF. No short-circuit or overheating is detected
because the card is not powered-up.

CMDVCC LOW within a card session. Output OFF
goes LOW when a fault condition is detected. As soon
as this occurs, an emergency deactivation is performed
automatically (see Fig.11). When the system controller
resets CMDVCC to HIGH it may sense the OFF level
again after completing the deactivation sequence. This
distinguishes between a hardware problem or a card
extraction (OFF goes HIGH again if a card is present).

Depending on the type of card-present switch within the
connector (normally-closed or normally-open) and on the
mechanical characteristics of the switch, bouncing may
occur on the PRES signals at card insertion or withdrawal.

There is a debounce feature in the device with an 8 ms
typical duration (see Fig.10). When a card is inserted,
output OFF goes HIGH only at the end of the debounce
time.

When the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES or PRES and output OFF goes LOW.

handbook, full pagewidth

MDB059

OFF

CMDVCC

PRES

VCC

debounce

deactivation caused by
cards withdrawal

deactivation caused by
short-circuit

debounce

Fig.10 Behaviour of OFF, CMDVCC, PRES and V

See

"Application note AN10141" for software decision algorithm on OFF signal.

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

LIMITING VALUES

Notes

1. All card contacts are protected against any short-circuit with any other card contact.

2. Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining.

Method 3015 (HBM; 1500

and 100 pF) 3 pulses positive and 3 pulses negative on each pin referenced to ground.

3. In accordance with EIA/JESD22-A114-B, June 2000.

4. In accordance with EIA/JESD22-A115-A, October 1997.

10 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see

"Handling MOS devices").

11 THERMAL CHARACTERISTICS

Note

1. This figure was obtained using the following PCB technology: FR, 4 layers, 0.5 mm thickness, class 5, copper

thickness 35

m, Ni/Go plating, ground plane in internal layers

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

0.3

+6.5

DDP

DC/DC converter supply voltage

0.3

+6.5

, V

voltage on input and output pins

pins XTAL1, XTAL2, 5V/3V, RSTIN,
AUX1UC, AUX2UC, I/OUC,
CLKDIV1, CLKDIV2, CMDVCC, OFF
and PORADJ

0.3

+6.5

card

voltage on card pins

pins PRES, PRES, I/O, RST, AUX1,
AUX2 and CLK

0.3

+6.5

voltage on other pins

pins V

, S1 and S2

0.3

+6.5

j(max)

maximum junction temperature

150

stg

storage temperature

+150

esd

electrostatic discharge voltage

card contacts in typical application;
notes 1 and 2

pins I/O, RST, V

, AUX1, AUX2,

CLK, PRES and PRES

all pins; note 1

human body model; notes 2 and 3

machine model; note 4

200

+200

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction
to ambient

in free air

TDA8024T

K/W

TDA8024AT

K/W

TDA8024TT

100

(1)

K/W

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

12 CHARACTERISTICS
V

= 3.3 V; V

DDP

= 5 V; T

amb

= 25

C; f

XTAL

= 10 MHz; all currents flowing into the IC are positive; see note 1; unless

otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP

MAX.

UNIT

Temperature

amb

ambient temperature

+85

Supplies

supply voltage

2.7

6.5

DDP

DC/DC converter supply
voltage

= 5 V;

< 80 mA

4.0

5.0

6.5

= 5 V;

< 20 mA

3.0

6.5

supply current

card inactive

1.2

card active; f

CLK

= f

XTAL

;

= 30 pF

1.5

DDP

DC/DC converter supply
current

inactive mode

0.1

active mode; f

CLK

= f

XTAL

;

= 30 pF;

= 0

= 5 V;

= 80 mA

200

= 3 V;

= 65 mA

100

th2

falling threshold voltage on
V

no external resistors at
pin PORADJ; V

level falling

2.35

2.45

2.55

hys2

hysteresis of threshold
voltage V

th2

no external resistors at
pin PORADJ

100

150

Pin PORADJ; note 2

th(ext)(rise)

external rising threshold
voltage on V

external resistor bridge at
pin PORADJ; V

level rising

1.240

1.28

1.310

th(ext)(fall)

external falling threshold
voltage on V

external resistor bridge at
pin PORADJ; V

level falling

1.190

1.22

1.26

hys(ext)

hysteresis of threshold
voltage V

th(ext)

external resistor bridge at
pin PORADJ

hys(ext)

hysteresis of threshold
voltage V

th(ext)

variation

with temperature

external resistor bridge at
pin PORADJ

0.25

mV/K

width of internal Power-on
reset pulse

no external resistors at
pin PORADJ

external resistor bridge at
pin PORADJ

L(PORADJ)

leakage current on
pin PORADJ

PORADJ

< 0.5 V

0.1

PORADJ

> 1 V

tot

total power dissipation

continuous operation;
T

amb

25 to +85

0.56

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

DC/DC converter

CLK

clock frequency

card active

2.2

3.2

MHz

th(vd-vf)

threshold voltage for
voltage doubler to change
to voltage follower

5 V card

5.2

5.8

6.2

3 V card

3.8

4.1

4.4

UP(av)

output voltage on pin V

(average value)

= 5 V

5.2

5.7

6.2

= 3 V; V

DDP

= 3.3 V

3.5

3.9

4.3

Card supply voltage (pin V

); note 3

VCC

external capacitance on
pin V

note 4

400

card supply voltage
(including ripple voltage)

5 V card

card inactive;

= 0 mA

0.1

+0.1

card inactive;

= 1 mA

0.1

+0.3

card active;

< 80 mA

4.75

5.0

5.25

card active; single current
pulse, I

100 mA,

= 2 ms

4.65

5.0

5.25

card active; current pulses,
I

= 40 nAs

4.65

5.0

5.25

card active; current pulses,
I

= 40 nAs with

< 200 mA, t

< 400 ns

4.65

5.0

5.25

3 V card

card inactive;

= 0 mA

0.1

+0.1

card inactive;

= 1 mA

0.1

+0.3

card active;

< 65 mA

2.85

3.0

3.15

card active; single current
pulse I

100 mA;

= 2 ms

2.76

3.0

3.20

card active; current pulses,
I

= 40 nAs

2.76

3.0

3.20

card active; current pulses,
I

= 40 nAs with

< 200 mA, t

< 400 ns

2.76

3.0

3.20

CC(ripple)(p-p)

ripple voltage on V

(peak to peak value)

ripple

= 20 kHz to 200 MHz

350

card supply current

= 0 to 5 V

= 0 to 3 V

short-circuit to GND

100

120

150

slew rate

slew up or down

0.08

0.15

0.22

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP

MAX.

UNIT

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

Crystal oscillator (pins XTAL1 and XTAL2)

XTAL1

XTAL2

external capacitance on
pins XTAL1 and XTAL2

depends on type of crystal or
resonator used

XTAL

crystal frequency

MHz

XTAL1

frequency applied on
pin XTAL1

MHz

LOW-level input voltage on
pin XTAL1

0.3

+0.3V

HIGH-level input voltage
on pin XTAL1

0.7V

+ 0.3 V

Data lines (pins I/O, I/OUC, AUX1, AUX2, AUX1UC and AUX2UC)

d(I/O-I/OUC),

d(I/OUC-I/O)

I/O to I/OUC, I/OUC to I/O
falling edge delay

200

active pull-up pulse width

100

I/O(max)

maximum frequency on
data lines

MHz

input capacitance on data
lines

Data lines to card reader (pins I/O, AUX1 and AUX2; with integrated 11 k

pull-up resistors to V

)

o(inactive)

output voltage

inactive mode

no load

0.1

o(inactive)

= 1 mA

0.3

o(inactive)

output current

inactive mode; pin grounded

LOW-level output voltage

= 1 mA

0.3

15 mA

0.4

HIGH-level output voltage

no DC load

0.9V

+ 0.1 V

5 and 3 V cards; I

0.75V

+ 0.1 V

10 mA

0.4

LOW-level input voltage

0.3

0.8

HIGH-level input voltage

1.5

+ 0.3 V

LOW-level input current

= 0 V

600

LIH

HIGH-level input leakage
current

= V

t(DI)

data input transition time

IL(max)

to V

IH(min)

1.2

t(DO)

data output transition time

= 0 to V

; C

80 pF;

10% to 90%

0.1

integrated pull-up resistor

pull-up resistor to V

current when pull-up active V

= 0.9V

; C = 80 pF

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP

MAX.

UNIT

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

Data lines to microcontroller (pins I/OUC, AUX1UC and AUX2UC; with integrated 11 k

pull-up resistors

to V

)

LOW-level output voltage

= 1 mA

0.3

HIGH-level output voltage

no DC load

0.9V

+ 0.1 V

5 and 3 V cards; I

0.75V

+ 0.1 V

LOW-level input voltage

0.3

+0.3V

HIGH-level input voltage

0.7V

+ 0.3 V

LIH

HIGH-level input leakage
current

= V

LOW-level input current

= 0 V

600

integrated pull-up resistor

pull-up resistor to V

t(DI)

data input transition time

IL(max)

to V

IH(min)

1.2

t(DO)

data output transition time

= 0 to V

; C

< 30 pF;

10% to 90%

0.1

current when pull-up active V

= 0.9V

; C = 30 pF

Internal oscillator

OSC(int)

frequency of internal
oscillator

inactive mode

140

200

kHz

active mode

2.2

2.7

3.2

MHz

Reset output to card reader (pin RST)

o(inactive)

output voltage

inactive mode

no load

0.1

o(inactive)

= 1 mA

0.3

o(inactive)

output current

inactive mode; pin grounded

d(RSTIN-RST)

RSTIN to RST delay

RST enabled

LOW-level output voltage

= 200

0.2

= 20 mA (current limit)

0.4

HIGH-level output voltage

200

0.9V

20 mA (current limit)

0.4

rise time

= 100 pF; V

= 5 or 3 V

0.1

fall time

= 100 pF; V

= 5 or 3 V

0.1

Clock output to card reader (pin CLK)

o(inactive)

output voltage

inactive mode

no load

0.1

o(inactive)

= 1 mA

0.3

o(inactive)

output current

CLK inactive; pin grounded

LOW-level output voltage

= 200

0.3

= 70 mA (current limit)

0.4

HIGH-level output voltage

200

0.9V

70 mA (current limit)

0.4

rise time

= 30 pF; note 5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP

MAX.

UNIT

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

fall time

= 30 pF; note 5

duty factor (except for
f

XTAL

)

= 30 pF; note 5

slew rate

slew up or down; C

= 30 pF

0.2

V/ns

Control inputs (pins CLKDIV1, CLKDIV2, CMDVCC, RSTIN and 5V/3V); note 6

LOW-level input voltage

0.3

+0.3V

HIGH-level input voltage

0.7V

+ 0.3 V

LIL

LOW-level input leakage
current

0 < V

< V

LIH

HIGH-level input leakage
current

0 < V

< V

Card presence inputs (pins PRES and PRES); note 7

LOW-level input voltage

0.3

+0.3V

HIGH-level input voltage

0.7V

+ 0.3 V

LIL

LOW-level input leakage
current

0 < V

< V

LIH

HIGH-level input leakage
current

0 < V

< V

Interrupt output (pin OFF; NMOS drain with integrated 20 k

pull-up resistor to V

)

LOW-level output voltage

= 2 mA

0.3

HIGH-level output voltage

0.75V

integrated pull-up resistor

20 k

pull-up resistor to V

Protection and limitation

CC(sd)

shutdown and limitation
current pin V

130

150

I/O(lim)

limitation current pins I/O,
AUX1 and AUX2

+15

CLK(lim)

limitation current pin CLK

+70

RST(lim)

limitation current pin RST

+20

shut-down temperature

150

Timing

act

activation time

see Fig.7

220

deactivation time

see Fig.8

100

start of the window for
sending CLK to the card

see Fig.7

130

end of the window for
sending CLK to the card

see Fig.7

140

220

debounce

debounce time pins PRES
and PRES

see Fig.10

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP

MAX.

UNIT

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

Notes

1. All parameters remain within limits but are tested only statistically for the temperature range. When a parameter is

specified as a function of V

or V

it means their actual value at the moment of measurement.

2. If no external bridge is used then, to avoid any disturbance, it is recommended to connect pin 18 to ground. Pin 18

is not connected in the TDA8024AT

3. To meet these specifications, pin V

should be decoupled to CGND using two ceramic multilayer capacitors of low

ESR both with values of 100 nF, or one 100 nF and one 220 nF (see Fig.13).

4. Permitted capacitor values are 100, or 100 + 100, or 220, or 220 + 100, or 330 nF.

5. Transition time and duty factor definitions are shown in Fig.12;

6. Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table 1.

7. Pin PRES is active LOW; pin PRES is active HIGH; PRES has an integrated 1.25

A current source to GND

(PRES to V

); the card is considered present if at least one of the inputs PRES or PRES is active.

---------------

handbook, full pagewidth

MDB058

10%

90%

10%

VOH

VOL

Fig.12 Definition of output and input transition times.

13 APPLICATION INFORMATION

Performance can be affected by the layout of the
application. For example, an additional cross-capacitance
of 1 pF between card reader contacts C2 and C3 or C2
and C7 can cause contact C2 to be polluted with high
frequency noise from C3 (or C7). In this case, include a
100 pF capacitor between contacts C2 and CGND.

Application recommendations:

Ensure there is ample ground area around the TDA8024
and the connector; place the TDA8024 very near to the
connector; decouple the V

and V

DDP

lines (these lines

are best positioned under the connector)

The TDA8024 and the microcontroller must use the
same V

supply. Pins CLKDIV1, CLKDIV2, RSTIN,

PRES, PRES, AUX1UC, I/OUC, AUX2UC, 5V/3V,
CMDVCC, and OFF are referred to V

; if pin XTAL1 is

to be driven by an external clock, also refer this pin to
V

Track C3 should be placed as far as possible from the
other tracks

The track connecting CGND to C5 should be straight
(the two capacitors on C1 should be connected to this
ground track)

Avoid ground loops between CGND, PGND and GND

Decouple V

DDP

and V

separately; if the two supplies

are the same in the application, then they should be
connected in star on the main track.

With all these layout precautions, noise should be kept to
an acceptable level and jitter on C3 should be less than
100 ps.

Reference layouts are provided in

"Application

note 10141", available on request.

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

handbook, full pagewidth

100 nF

(1)

100 nF

(1)

100 nF

(3)

(6)

(7)

AUX2UC

AUX1UC

I/OUC

XTAL2

XTAL1

OFF

GND

VDD

RSTIN

CMDVCC

PORADJ

VCC

RST

CLK

CLKDIV1

CLKDIV2

5V/3V

PGND

VDDP

VUP

PRES

I/O

AUX2

AUX1

CGND

TDA8024

C5
C6

C1
C2

CARD READ

(normally closed type)

3.3 V

VDD

58.1 k

41.9 k

3.3 V POWERED
MICROCONTROLLER

33 pF

100 nF

(4)

220 nF

(5)

5 V

100 k

MDB050

3.3 V

(2)

Fig.13 Application diagram.

(1) These capacitors must be of the low ESR-type and be placed near the IC (within 100 mm).

(2) TDA8024 and the microcontroller must use the same V

supply.

(3) Make short, straight connections between CGND, C5 and the ground connection to the capacitor.

(4) Mount one low ESR-type 100 nF capacitor close to pin V

(5) Mount one low ESR-type 100 or 220 nF capacitor close to C1 contact (less than 100 mm from it).

(6) The connection to C3 should be routed as far from C2, C7, C4 and C8 and, if possible, surrounded by grounded tracks.

(7) Optional resistor bridge for changing the threshold of V

. If this bridge is not required pin 18 should be connected to ground; see Section 8.2.2.

Pin 18 is not connected in the TDA8024AT.

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

14 PACKAGE OUTLINES

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

inches

2.65

0.3
0.1

2.45
2.25

0.49
0.36

0.32
0.23

18.1
17.7

7.6
7.4

1.27

10.65
10.00

1.1
1.0

0.9
0.4

8
0

0.25

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1
0.4

SOT136-1

detail X

(A )

0.25

075E06

MS-013

pin 1 index

0.1

0.012
0.004

0.096
0.089

0.019
0.014

0.013
0.009

0.71
0.69

0.30
0.29

0.05

1.4

0.055

0.419
0.394

0.043
0.039

0.035
0.016

0.01

0.25

0.01

0.004

0.043
0.016

0.01

10 mm

scale

SO28: plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

99-12-27
03-02-19

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

UNIT

(1)

(2)

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

0.15
0.05

0.95
0.80

0.30
0.19

0.2
0.1

9.8
9.6

4.5
4.3

0.65

6.6
6.2

0.4
0.3

0.8
0.5

8
0

0.13

0.1

0.2

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75
0.50

SOT361-1

MO-153

99-12-27
03-02-19

0.25

pin 1 index

detail X

(A )

2.5

5 mm

scale

TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm

SOT361-1

max.

1.1

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

15 SOLDERING

15.1

Introduction to soldering surface mount
packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.

15.2

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 seconds and 200 seconds
depending on heating method.

Typical reflow peak temperatures range from
215

C to 270

C depending on solder paste material. The

top-surface temperature of the packages should
preferably be kept:

below 225

C (SnPb process) or below 245

C (Pb-free

process)

for all BGA, HTSSON-T and SSOP-T packages

for packages with a thickness

2.5 mm

for packages with a thickness < 2.5 mm and a

volume

350 mm

so called thick/large packages.

below 240

C (SnPb process) or below 260

C (Pb-free

process) for packages with a thickness < 2.5 mm and a
volume < 350 mm

so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.

15.3

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time of the leads in the wave ranges from
3 seconds to 4 seconds at 250

C or 265

C, depending

on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 seconds to 5 seconds
between 270

C and 320

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

15.5

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. For more detailed information on the BGA packages refer to the

"(LF)BGA Application Note" (AN01026); order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account

be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217

C measured in the atmosphere of the reflow oven. The package body peak temperature

must be kept as low as possible.

4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.

5. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted

on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.

9. Hot bar or manual soldering is suitable for PMFP packages.

PACKAGE

(1)

SOLDERING METHOD

WAVE

REFLOW

(2)

BGA, HTSSON..T

(3)

, LBGA, LFBGA, SQFP, SSOP..T

(3)

, TFBGA,

USON, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS

not suitable

(4)

suitable

PLCC

(5)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(5)(6)

suitable

SSOP, TSSOP, VSO, VSSOP

not recommended

(7)

suitable

CWQCCN..L

(8)

, PMFP

(9)

, WQCCN..L

(8)

not suitable

2004 July 12

Philips Semiconductors

Product specification

IC card interface

TDA8024

16 DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL

DATA SHEET

STATUS

(1)

PRODUCT

STATUS

(2)(3)

DEFINITION

Objective data

Development

This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Preliminary data Qualification

This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

III

Product data

Production

This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).

17 DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

18 DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status `Production'), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.

SCA76

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Philips Semiconductors a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands

R63/03/pp

Date of release:

2004 July 12

Document order number:

9397 750 13195

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8024AT

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8024AT