1999 Nov 10

Philips Semiconductors

Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8357J

FEATURES

Few external components required

High efficiency fully DC coupled vertical bridge output
circuit

Vertical flyback switch with short rise and fall times

Built-in guard circuit

Thermal protection circuit

Improved EMC performance due to differential inputs.

GENERAL DESCRIPTION

The TDA8357J is a power circuit for use in 90

and 110

colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.

The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of absence of second breakdown.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

supply voltage

7.5

flyback supply voltage

q(P)(av)

average quiescent supply current

during scan

q(FB)(av)

average quiescent flyback supply current

during scan

tot

total power dissipation

Inputs and outputs

i(dif)(p-p)

differential input voltage (peak-to-peak value)

1000

1500

o(p-p)

output current (peak-to-peak value)

2.0

Flyback switch

o(peak)

maximum (peak) output current

1.5 ms

1.2

Thermal data; in accordance with IEC 747-1

stg

storage temperature

+150

amb

ambient temperature

+75

junction temperature

150

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8357J

DBS9P

plastic DIL-bent-SIL power package; 9 leads (lead length
12/11 mm); exposed die pad

SOT523-1

1999 Nov 10

Philips Semiconductors

Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8357J

FUNCTIONAL DESCRIPTION

Vertical output stage

The vertical driver circuit has a bridge configuration.
The deflection coil is connected between the
complimentary driven output amplifiers. The differential
input circuit is voltage driven. The input circuit is specially
designed for direct connection to driver circuits delivering
a differential signal but it is also suitable for single-ended
applications. The output currents of the driver device are
converted to voltages by the conversion resistors
R

CV1

and R

CV2

(see Fig.3) connected to pins INA

and INB. The differential input voltage is compared with
the voltage across the measuring resistor R

, providing

internal feedback information. The voltage across R

proportional with the output current. The relationship
between the differential input current and the output
current is defined by:

i(dif)(p-p)

= I

o(p-p)

The output current should measure 0.5 to 2.0 A (p-p) and
is determined by the value of R

and R

. The allowable

input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances. Depending on the values of R

and the

internal bondwire resistance (typical value of 50 m

) the

actual value of the current in the deflection coil will be
about 5% lower than calculated.

Flyback supply

The flyback voltage is determined by the flyback supply
voltage V

. The principle of two supply voltages (class G)

allows to use an optimum supply voltage V

for scan and

an optimum flyback supply voltage V

for flyback, thus

very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to V

, due

to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short rise
and fall times of the flyback switch are determined mainly
by the slew-rate value of more than 300 V/

Protection

The output circuit contains protection circuits for:

Too high die temperature

Overvoltage of output A.

Guard circuit

A guard circuit with output pin GUARD is provided.

The guard circuit generates a HIGH-level during the
flyback period. The guard circuit is also activated for one
of the following conditions:

During thermal protection (T

170

During an open-loop condition.

The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.

Damping resistor compensation

HF loop stability is achieved by connecting a damping
resistor R

across the deflection coil. The current values

in R

during scan and flyback are significantly different.

Both the resistor current and the deflection coil current flow
into measuring resistor R

, resulting in a too low deflection

coil current at the start of the scan.

The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time.
For that purpose a compensation resistor R

CMP

in series

with a zener diode is connected between pins OUTA
and INA (see Fig.4). The zener diode voltage value should
be equal to V

. The value of R

CMP

is calculated by:

where:

loss(FB)

is the voltage loss between pins V

and OUTA

at flyback

coil

is the deflection coil resistance

is the voltage of zener diode D5.

CMP

loss FB

(

)

(

)

CV1

loss FB

(

)

coil peak

(

)

coil

(

)

------------------------------------------------------------------------------------------------------------

1999 Nov 10

Philips Semiconductors

Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8357J

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.

2. At T

j(max)

3. Equivalent to 200 pF capacitance discharge through a 0

resistor.

4. Equivalent to 100 pF capacitance discharge through a 1.5 k

resistor.

5. Internally limited by thermal protection at T

170

THERMAL CHARACTERISTICS
In accordance with IEC 747-1.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

flyback supply voltage

DC voltage

pin OUTA

note 1

pin OUTB

pins INA, INB, GUARD and FEEDB

0.5

DC current

pins OUTA and OUTB

during scan (p-p)

2.0

pins OUTA and OUTB

at flyback (peak); t

1.5 ms

1.2

pins INA, INB, GUARD and FEEDB

+20

latch-up current

current into any pin; pin voltage
is 1.5

; note 2

+200

current out of any pin; pin voltage
is

1.5

; note 2

200

electrostatic handling voltage

machine model; note 3

300

+300

human body model; note 4

2000 +2000 V

tot

total power dissipation

stg

storage temperature

+150

amb

ambient temperature

+75

junction temperature

note 5

150

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

th(j-c)

thermal resistance from junction to case

K/W

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

1999 Nov 10

Philips Semiconductors

Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8357J

CHARACTERISTICS
V

= 12 V; V

= 45 V; f

vert

= 50 Hz; V

I(bias)

= 880 mV; T

amb

= 25

C; measured in test circuit of Fig.3; unless otherwise

specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

operating supply voltage

7.5

flyback supply voltage

note 1

q(P)(av)

average quiescent supply current

during scan

q(P)

quiescent supply current

no signal; no load

q(FB)(av)

average quiescent flyback supply
current

during scan

Inputs A and B

i(dif)(p-p)

differential input voltage
(peak-to-peak value)

note 2

1000

1500

I(bias)

input bias voltage

note 2

100

880

1600

I(bias)

input bias current

Outputs A and B

loss(1)

voltage loss first scan part

note 3

= 0.7 A

3.9

= 1.0 A

5.5

loss(2)

voltage loss second scan part

note 4

0.7 A

2.8

1.0 A

4.0

o(p-p)

output current (peak-to-peak value)

2.0

linearity error

o(p-p)

= 2.0 A; notes 5 and 6

adjacent blocks

non adjacent blocks

offset

offset voltage

across R

; V

i(dif)

= 0 V

I(bias)

= 200 mV

I(bias)

= 1 V

offset(T)

offset voltage variation with temperature across R

; V

i(dif)

= 0 V

V/K

DC output voltage

i(dif)

= 0 V

0.5V

v(ol)

open-loop voltage gain

notes 7 and 8

3dB(h)

high

3 dB cut-off frequency

open-loop

kHz

voltage gain

note 9

v(T)

voltage gain variation with the
temperature

PSRR

power supply rejection ratio

note 10

1999 Nov 10

Philips Semiconductors

Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8357J

Notes

1. To limit V

OUTA

to 68 V, V

must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA

and V

at the first part of the flyback.

2. Allowable input range: V

I(bias)

+ V

i(dif)

< 1600 mV and V

I(bias)

i(dif)

> 100 mV for each input.

3. This value specifies the sum of the voltage losses of the internal current paths between pins V

and OUTA, and

between pins OUTB and GND. Specified for T

= 125

C. The temperature coefficient for V

loss(1)

is a positive value.

4. This value specifies the sum of the voltage losses of the internal current paths between pins V

and OUTB, and

between pins OUTA and GND. Specified for T

= 125

C. The temperature coefficient for V

loss(2)

is a positive value.

5. The linearity error is measured for a linear input signal without S-correction and is based on the `on screen'

measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
blocks k. The 1st and 22nd blocks are ignored, while the voltage amplitudes are measured across R

, starting at

k = 2 and ending at k = 21, where V

and V

k+1

are the measured voltages of two successive blocks. V

min

, V

max

and

avg

are the minimum, maximum and average voltages respectively. The linearity errors are defined as:

(adjacent blocks)

(non adjacent blocks)

6. The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage

dependent S-distortion in the input stage.

8. Pin FEEDB not connected.

10. V

P(ripple)

= 500 mV (RMS value); 50 Hz < f

P(ripple)

< 1 kHz; measured across R

11. This value specifies the internal voltage loss of the current path between pins V

and OUTA.

Flyback switch

o(peak)

maximum (peak) output current

1.5 ms

1.2

loss(FB)

voltage loss at flyback

note 11

= 0.7 A

7.5

8.5

= 1.0 A

Guard circuit

O(grd)

guard output voltage

O(grd)

= 100

O(grd)(max)

allowable guard voltage

maximum leakage current
I

L(max)

= 10

O(grd)

output current

O(grd)

= 0 V; not active

O(grd)

= 4.5 V; active

2.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

avg

--------------------------

max

min

avg

-------------------------------

v ol

( )

OUTA

OUTB

FEEDB

OUTB

--------------------------------------------

FEEDB

OUTB

INA

INB

--------------------------------------------

1999

Nov

Philips Semiconductors

Preliminar

y specification

Full br

idge v

r
tical deflection output circuit

in L

VDMOS

TD
A8357J

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, full pagewidth

VP = 11 V

Vfb = 29 V

deflection
coil
8.82 mH
7.9

(W66ESF)

1.5

RD1
330

RCMP
270 k

DEFLECTION

CONTROLLER

2.2 nF

(1)

47 nF

100

12 V

(2)

(100 V)

100 nF

220

(25 V)

RFB

RD2

(1)

INA

INB

FEEDB

GUARD

RGRD

12 k

RCV1

2.2 k

(1%)

RCV2

2.2 k

(1%)

2.7 k

MGS807

INPUT

AND

FEEDBACK

CIRCUIT

GUARD

CIRCUIT

TDA8357J

GND

VFB

OUTB

OUTA

Vi(p-p)

VI(bias)

Vi(p-p)

Fig.4 Application diagram.

vert

= 50 Hz; t

= 640

s; I

I(bias)

= 400

A; I

i(dif)(peak)

= 494

A; I

o(p-p)

= 1.45 A.

(1) Optional, depending on the deflection coil impedance.

(2) Optional extended flash over protection; BYD33D or equivalent.

1999 Nov 10

Philips Semiconductors

Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8357J

Supply voltage calculation

For calculating the minimum required supply voltage,
several specific application parameter values have to be
known. These parameters are the required
maximum (peak) deflection coil current I

coil(peak)

, the coil

parameters R

coil

and L

coil

, and the measuring resistance

of R

. The required maximum (peak) deflection coil

current should also include the overscan.

The deflection coil resistance has to be multiplied with 1.2
in order to take account of hot conditions.

Chapter "Characteristics" supplies values for the voltage
losses of the vertical output stage. For the first part of the
scan the voltage loss is given by V

loss(1)

. For the second

part of the scan the voltage loss is given by V

loss(2)

The voltage drop across the deflection coil during scan is
determined by the coil impedance. For the first part of the
scan the inductive contribution and the ohmic contribution
to the total coil voltage drop are of opposite sign, while for
the second part of the scan the inductive part and the
ohmic part have the same sign.

For the vertical frequency the maximum frequency
occurring must be applied to the calculations.

The required power supply voltage V

for the first part of

the scan is given by:

The required power supply voltage V

for the second part

of the scan is given by:

The minimum required supply voltage V

shall be the

highest of the two values V

P(1)

and V

P(2)

. Spread in supply

voltage and component values also has to be taken into
account.

Flyback supply voltage calculation

If the flyback time is known, the required flyback supply
voltage can be calculated by the simplified formula:

where:

The flyback supply voltage calculated this way is about
5% to 10% higher than required.

Calculation of the power dissipation of the vertical
output stage

The IC total power dissipation is given by the formula:

tot

= P

sup

The power to be supplied is given by the formula:

In this formula 0.3 [W] represents the average value of the
losses in the flyback supply.

The average external load power dissipation in the
deflection coil and the measuring resistor is given by the
formula:

Example

Table 1

Application values

Table 2

Calculated values

P 1

( )

coil peak

(

)

coil

(

)

coil

coil peak

(

)

vert max

(

)

loss 1

( )

P 2

( )

coil peak

(

)

coil

(

)

coil

coil peak

(

)

vert max

(

)

loss 2

( )

coil p p

(

)

coil

---------------------------

coil

---------------------------

SYMBOL

VALUE

UNIT

coil(peak)

0.725

coil(p-p)

1.45

coil

8.82

coil

7.9

1.5

vert

640

SYMBOL

VALUE

UNIT

+ R

coil

(hot)

vert

0.02

0.000802

sup

4.45

1.93

tot

2.52

sup

coil peak

(

)

------------------------

0.015 [A]

0.3 [W]

coil peak

(

)

(

)

--------------------------------

coil

(

)

1999 Nov 10

Philips Semiconductors

Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

TDA8357J

SOLDERING

Introduction to soldering through-hole mount
packages

This text gives a brief insight to wave, dip and manual
soldering. A more in-depth account of soldering ICs can be
found in our

"Data Handbook IC26; Integrated Circuit

Packages" (document order number 9398 652 90011).

Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joints for more than 5 seconds.

The total contact time of successive solder waves must not
exceed 5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg(max)

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300

C it may remain in contact for up to

10 seconds. If the bit temperature is between
300 and 400

C, contact may be up to 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

DIPPING

WAVE

DBS, DIP, HDIP, SDIP, SIL

suitable

(1)

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

Philips Semiconductors a worldwide company

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Printed in The Netherlands

545004/200/01/pp

Date of release:

1999 Nov 10

Document order number:

9397 750 06196

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