1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

FEATURES

Few external components required

High efficiency fully DC coupled vertical bridge output
circuit

Vertical flyback switch with short rise and fall times

Built-in guard circuit

Thermal protection circuit

Improved EMC performance due to differential inputs

East-west output stage.

GENERAL DESCRIPTION

The TDA8358J is a power circuit for use in 90

and 110

colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9 picture tubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.

The east-west output stage is able to supply the sink
current for a diode modulator circuit.

The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of absence of second breakdown.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

supply voltage

7.5

flyback supply voltage

q(P)(av)

average quiescent supply current

during scan

q(FB)(av)

average quiescent flyback supply current

during scan

east-west power dissipation

tot

total power dissipation

Inputs and outputs

i(dif)(p-p)

differential input voltage (peak-to-peak value)

1000

1500

o(p-p)

output current (peak-to-peak value)

3.2

Flyback switch

o(peak)

maximum (peak) output current

1.5 ms

1.8

East-west amplifier

output voltage

I(bias)

input bias voltage

3.2

output current

750

Thermal data; in accordance with IEC 747-1

stg

storage temperature

+150

amb

ambient temperature

+75

junction temperature

150

1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

PINNING

FUNCTIONAL DESCRIPTION

Vertical output stage

The vertical driver circuit has a bridge configuration.
The deflection coil is connected between the
complimentary driven output amplifiers. The differential
input circuit is voltage driven. The input circuit is specially
designed for direct connection to driver circuits delivering
a differential signal but it is also suitable for single-ended
applications. The output currents of the driver device are
converted to voltages by the conversion resistors
R

CV1

and R

CV2

(see Fig.3) connected to pins INA

and INB. The differential input voltage is compared with
the voltage across the measuring resistor R

, providing

internal feedback information. The voltage across R

proportional with the output current. The relationship
between the differential input current and the output
current is defined by:

i(dif)(p-p)

= I

o(p-p)

The output current should measure 0.5 to 3.2 A (p-p) and
is determined by the value of R

and R

. The allowable

input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances. Depending on the value of R

and the internal

bondwire resistance (typical value 50 m

) the actual value

of the current in the deflection coil will be about 5% lower
than calculated.

Flyback supply

The flyback voltage is determined by the flyback supply
voltage V

. The principle of two supply voltages (class G)

allows to use an optimum supply voltage V

for scan and

an optimum flyback supply voltage V

for flyback, thus

very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to V

, due

to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short
rise and fall times of the flyback switch are determined
mainly by the slew-rate value of more than 300 V/

Protection

The output circuit contains protection circuits for:

Too high die temperature

Overvoltage of output A.

SYMBOL

PIN

DESCRIPTION

INA

input A

INB

input B

supply voltage

OUTB

output B

INEW

east-west input

VGND

vertical ground

EWGND

east-west ground

OUTEW

east-west output

flyback supply voltage

OUTA

output A

GUARD

guard output

FEEDB

feedback input

COMP

compensation input

handbook, halfpage

TDA8358J

MGL867

INA

INB

OUTB

INEW

VGND

EWGND

OUTEW

VFB

OUTA

GUARD

FEEDB

COMP

Fig.2 Pin configuration.

The die has been glued to the metal block of the package. If the metal
block is not insulated from the heatsink, the heatsink shall only be
connected directly to pin VGND.

1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

Guard circuit

A guard circuit with output pin GUARD is provided.

The guard circuit generates a HIGH-level during the
flyback period. The guard circuit is also activated for one
of the following conditions:

During thermal protection (T

170

During an open-loop condition.

The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.

Damping resistor compensation

HF loop stability is achieved by connecting a damping
resistor R

(see Fig.4) across the deflection coil.

The current values in R

during scan and flyback are

significantly different. Both the resistor current and the
deflection coil current flow into measuring resistor R

resulting in a too low deflection coil current at the start of
the scan.

The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time.

For that purpose a compensation resistor R

CMP

connected between pins OUTA and COMP. The value of
R

CMP

is calculated by:

where:

coil

is the coil resistance

loss(FB)

is the voltage loss between pins V

and OUTA

at flyback.

East-west amplifier

The east-west amplifier is a current driver sinking the
current of a diode modulator circuit. A feedback
resistor R

EWF

(see Fig.4) has to be connected between

the input and output of the inverting east-west amplifier in
order to convert the east-west correction input current into
an output voltage. The output voltage of the east-west
circuit at pin OUTEW is given by:

EWF

+ V

The maximum output voltage is V

o(max)

= 68 V, while the

maximum output current of the circuit is I

o(max)

= 750 mA.

CMP

loss FB

(

)

(

)

300

(

)

loss FB

(

)

coil peak

(

)

coil

(

)

-------------------------------------------------------------------------------------------------------------

1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.

2. Equivalent to 200 pF capacitance discharge through a 0

resistor.

3. Equivalent to 100 pF capacitance discharge through a 1.5 k

resistor.

4. For repetitive time durations of t < 0.1 ms or a non repetitive time duration of t < 5 ms the maximum (peak) east-west

power dissipation P

EW(peak)

= 15 W.

5. Internally limited by thermal protection at T

170

THERMAL CHARACTERISTICS
In accordance with IEC 747-1.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

flyback supply voltage

VGND-EWGND

voltage difference between
pins VGND and EWGND

0.3

DC voltage

pins OUTA and OUTEW

note 1

pin OUTB

pins INA, INB, INEW, GUARD,
FEEDB, and COMP

0.5

DC current

pins OUTA and OUTB

during scan (p-p)

3.2

pins OUTA and OUTB

at flyback (peak); t

1.5 ms

1.8

pins INA, INB, INEW, GUARD,
FEEDB, and COMP

+20

pin OUTEW

750

latch-up current

input current into any pin;
pin voltage is 1.5

; T

= 150

+200

input current out of any pin;
pin voltage is

1.5

; T

= 150

200

electrostatic handling voltage

machine model; note 2

300

+300

human body model; note 3

2000 +2000 V

east-west power dissipation

note 4

tot

total power dissipation

stg

storage temperature

+150

amb

ambient temperature

+75

junction temperature

note 5

150

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-c)

thermal resistance from junction to case

K/W

th(j-a)

thermal resistance from junction to ambient

in free air

K/W

1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

CHARACTERISTICS
V

= 12 V; V

= 45 V; f

vert

= 50 Hz; V

I(bias)

= 880 mV; T

amb

= 25

C; measured in test circuit of Fig.3; unless otherwise

specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

operating supply voltage

7.5

flyback supply voltage

note 1

q(P)(av)

average quiescent supply current

during scan

q(P)

quiescent supply current

no signal; no load

q(FB)(av)

average quiescent flyback supply
current

during scan

Inputs A and B

i(dif)(p-p)

differential input voltage
(peak-to-peak value)

note 2

1000

1500

I(bias)

input bias voltage

note 2

100

880

1600

I(bias)

input bias current

Outputs A and B

loss(1)

voltage loss first scan part

note 3

= 1.1 A

4.5

= 1.6 A

6.6

loss(2)

voltage loss second scan part

note 4

1.1 A

3.3

1.6 A

4.8

o(p-p)

output current (peak-to-peak value)

3.2

linearity error

o(p-p)

= 3.2 A; notes 5 and 6

adjacent blocks

non adjacent blocks

offset

offset voltage

across R

; V

i(dif)

= 0 V

I(bias)

= 200 mV

I(bias)

= 1 V

offset(T)

offset voltage variation with
temperature

across R

; V

i(dif)

= 0 V

V/K

DC output voltage

i(dif)

= 0 V

0.5V

v(ol)

open-loop voltage gain

notes 7 and 8

3dB(h)

high

3 dB cut-off frequency

open-loop

kHz

voltage gain

note 9

v(T)

voltage gain variation with
temperature

PSRR

power supply rejection ratio

note 10

1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

Notes

1. To limit V

OUTA

to 68 V, V

must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA

and V

at the first part of the flyback.

2. Allowable input range for both inputs: V

I(bias)

+ V

i(dif)(peak)

< 1600 mV and V

I(bias)

i(dif)(peak)

> 100 mV.

3. This value specifies the sum of the voltage losses of the internal current paths between pins V

and OUTA, and

between pins OUTB and GND. Specified for T

= 125

C. The temperature coefficient for V

loss(1)

is a positive value.

4. This value specifies the sum of the voltage losses of the internal current paths between pins V

and OUTB, and

between pins OUTA and GND. Specified for T

= 125

C. The temperature coefficient for V

loss(2)

is a positive value.

5. The linearity error is measured for a linear input signal without S-correction and is based on the `on screen'

measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists
of two successive parts. The voltage amplitudes are measured across R

, starting at k = 1 and ending at k = 10,

where V

and V

k+1

are the measured voltages of two successive blocks. V

min

, V

max

and V

avg

are the minimum,

maximum and average voltages respectively. The linearity errors are defined as:

(adjacent blocks)

(non adjacent blocks)

Flyback switch

o(peak)

maximum (peak) output current

1.5 ms

1.8

loss(FB)

voltage loss at flyback

note 11

= 1.1 A

7.5

8.5

= 1.6 A

Guard circuit

O(grd)

guard output voltage

O(grd)

= 100

O(grd)(max)

allowable guard voltage

maximum leakage current
I

L(max)

= 10

O(grd)

output current

O(grd)

= 0 V; not active

O(grd)

= 4.5 V; active

2.5

East-west amplifier

output voltage

at pin OUTEW

loss

voltage loss

= 750 mA; note 12

I(bias)

input bias voltage

2.5

3.2

I(bias)

input bias current

into pin INEW; note 13

= 100 mA

2.5

= 500 mA

11.5

v(ol)

open-loop voltage gain

THD

harmonic distortion

0.5

3dB(h)

high

3 dB cut-off frequency

MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

avg

--------------------------

100%

max

min

avg

-------------------------------

100%

1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

6. The linearity errors are specified for a minimum input voltage of 300 mV single-ended. Lower input voltages lead to

voltage dependent S-distortion in the input stage.

8. Pin FEEDB not connected.

10. V

P(ripple)

= 500 mV (RMS value); 50 Hz < f

P(ripple)

< 1 kHz; measured across R

11. This value specifies the internal voltage loss of the current path between pins V

and OUTA.

12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND.

13. Measured for R

EWF

= 10 k

; R

EWL

= 30

; V

= 6 V.

a) For I

= 100 mA and a voltage of 9 V at R

EWL

connected to the line output transformer, the east-west amplifier

input current (see Fig.4) is I

= 300

b) For I

= 500 mA and a voltage of 21 V at R

EWL

connected to the line output transformer, the east-west amplifier

input current (see Fig.4) is I

= 350

v ol

( )

OUTA

OUTB

FEEDB

OUTB

--------------------------------------------

FEEDB

OUTB

INA

INB

--------------------------------------------

1999

Dec

Philips Semiconductors

Product specification

Full br

idge v

r
tical deflection output circuit

in L

VDMOS with east-w

est amplifier

TD
A8358J

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ll pagewidth

VP = 14 V

Vfb = 30 V

deflection
coil
5 mH
6

(W66ESF)

0.5

RD1
270

RCMP
820 k

(1)

47 nF

100

(2)

(100 V)

2.7

(3)

100 nF

220

(25 V)

RFB

RD2

(1)

FEEDB

GUARD

RGRD
5.6 k

2.7 k

INPUT

AND

FEEDBACK

CIRCUIT

GUARD

CIRCUIT

TDA8358J

VFB

OUTB

OUTA

DEFLECTION

CONTROLLER

2.2 nF

INA

INB

RCV1

2.2 k

(1%)

RCV2

2.2 k

(1%)

VI(bias)

REWL

REWF

82 k

MGL874

VGND

EWGND

INEW

OUTEW

to line output
transformer

COMP.

CIRCUIT

COMP

II(av)

Ii(p-p)

Vi(p-p)

Fig.4 Application diagram.

Deflection circuit: f

vert

= 50 Hz; t

= 640

s; I

I(bias)

= 400

A; I

i(dif)(peak)

= 290

A; I

o(p-p)

= 2.4 A.

East-west amplifier: I

i(B)

= 290

A; I

i(T)

= 510

(1) Optional, component values depend on the deflection coil impedance.

(2) Extended flash over protection; BYD33D or equivalent.

(3) Optional, extended flash over protection.

1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

Supply voltage calculation

For calculating the minimum required supply voltage,
several specific application parameter values have to be
known. These parameters are the required
maximum (peak) deflection coil current I

coil(peak)

, the coil

parameters R

coil

and L

coil

, and the measuring resistance

of R

. The required maximum (peak) deflection coil

current should also include the overscan.

The deflection coil resistance has to be multiplied with 1.2
in order to take account of hot conditions.

Chapter "Characteristics" supplies values for the voltage
losses of the vertical output stage. For the first part of the
scan the voltage loss is given by V

loss(1)

. For the second

part of the scan the voltage loss is given by V

loss(2)

The voltage drop across the deflection coil during scan is
determined by the coil impedance. For the first part of the
scan the inductive contribution and the ohmic contribution
to the total coil voltage drop are of opposite sign, while for
the second part of the scan the inductive part and the
ohmic part have the same sign.

For the vertical frequency the maximum frequency
occurring must be applied to the calculations.

The required power supply voltage V

for the first part of

the scan is given by:

The required power supply voltage V

for the second part

of the scan is given by:

The minimum required supply voltage V

shall be the

highest of the two values V

P(1)

and V

P(2)

. Spread in supply

voltage and component values also has to be taken into
account.

Flyback supply voltage calculation

If the flyback time is known, the required flyback supply
voltage can be calculated by the simplified formula:

where:

The flyback supply voltage calculated this way is about
5% to 10% higher than required.

Calculation of the power dissipation of the vertical
output stage

The power dissipation of the vertical output stage is given
by the formula:

= P

sup

The power to be supplied is given by the formula:

In this formula 0.3 [W] represents the average value of the
losses in the flyback supply.

The average external load power dissipation in the
deflection coil and the measuring resistor is given by the
formula:

Example

Table 1

Application values

Table 2

Calculated values

P 1

( )

coil peak

(

)

coil

(

)

coil

coil peak

(

)

vert max

(

)

loss 1

( )

P 2

( )

coil peak

(

)

coil

(

)

coil

coil peak

(

)

vert max

(

)

loss 2

( )

coil p p

(

)

coil

---------------------------

coil

---------------------------

SYMBOL

VALUE

UNIT

coil(peak)

1.2

coil(p-p)

2.4

coil

0.6

vert

640

SYMBOL

VALUE

UNIT

+ R

coil

(hot)

7.8

vert

0.02

0.000641

sup

8.91

3.74

5.17

sup

coil peak

(

)

------------------------

0.015 [A]

0.3 [W]

coil peak

(

)

(

)

--------------------------------

coil

(

)

1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

Power dissipation calculation for the east-west stage

In general the shape of the east-west output wave form is
a parabola. The output voltage will be higher at the
beginning and end of the vertical scan compared to the
voltage at the scan middle, while the output current will be
higher at the scan middle. This results in an almost uniform
power dissipation distribution during scan. Therefore the
power dissipation can be calculated by multiplying the
average values of the output voltage and the output
current of pin OUTEW.

When verifying the dissipation also the start-up and stop
dissipation should be taken into account. Power
dissipation during start-up can be 3 to 5 times higher than
during normal operation.

Heatsink calculation

The value of the heatsink can be calculated in a standard
way with a method based on average temperatures.
The required thermal resistance of the heatsink is
determined by the maximum die temperature of 150

In general we recommend to design for an average die
temperature not exceeding 130

C. It should be noted

that the heatsink thermal resistance R

th(h-a)

found by

performing a standard calculation will be lower then
normally found for a vertical deflection stand alone device,
due to the contribution of the EW power dissipation to this
value.

XAMPLE

Measured or known values:

= 3 W; P

= 6 W; T

amb

= 40

C; T

= 130

th(j-c)

= 4 K/W; R

th(c-h)

= 1 K/W.

The required heatsink thermal resistance is given by:

When we use the values known we find:

The heatsink temperature will be:

= T

amb

+ R

th(h-a)

tot

= 40 + 5

9 = 85

Equivalent thermal resistance network

The TDA8358J has two independent power dissipating
systems, the vertical output circuit and the east-west
circuit.

It is recommended to verify the individual maximum (peak)
junction temperatures of both circuits. Therefore the
maximum (peak) power dissipations of the circuits and
also the heatsink temperature should be measured.
The maximum (peak) junction temperatures can be
calculated by using an equivalent thermal network
(see Fig.5).

The network does only consist the contribution of the
maximum (peak) power dissipation P

TRv(peak)

, being the

dissipation of the most critical transistor internally
connected to pins OUTB and VGND. The model assumes
equivalent maximum (peak) power dissipations during the
different vertical scan stages for all the functionally paired
transistors. The calculated maximum (peak) junction
temperatures should not exceed T

= 150

th h

(

)

amb

-------------------------

(

th j

(

)

th c

(

)

th h

(

)

130

----------------------

(

)

5 K/W

1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

XAMPLE

Measured or known values:

The east-west power dissipation: P

= 3 W

The vertical power dissipation: P

= 6 W

The maximum (peak) power dissipation of the most
critical transistor: P

TRv(peak)

= 5 W

The case temperature: T

= 85

The IC total power dissipation is:

tot

= P

+ P

= 6 + 3 = 9 W

It should be noted that the allowed IC total power
dissipation is P

tot

= 15 W (maximum value).

The maximum (peak) temperature T

P1(peak)

is given by:

P1(peak)

= T

+ (P

+ P

TRv(peak)

)

th(P1-c)

= 85 + (3 + 5)

2.2 = 102.6

The maximum (peak) junction temperatures for the output
circuits are given by:

j(EW)(peak)

= T

P1(peak)

+ R

th(EW-P1)

= 102.6 + 10.5

3 = 134.1

j(TRv)(peak)

= T

P1(peak)

+ R

th(TRv-P1)

TRv(peak)

= 102.6 + 5.2

5 = 128.6

handbook, halfpage

MGL872

TEW(M)

PEW

TTRv(M)

TP1(M)

PTRv(M)

Ptot

Rth(TRv-P1)

5.2 K/W

Rth(P1-c)

2.2 K/W

Rth(EW-P1)

10.5 K/W

Fig.5 Equivalent thermal resistance network.

1999 Dec 22

Philips Semiconductors

Product specification

Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier

TDA8358J

SOLDERING

Introduction to soldering through-hole mount
packages

This text gives a brief insight to wave, dip and manual
soldering. A more in-depth account of soldering ICs can be
found in our

"Data Handbook IC26; Integrated Circuit

Packages" (document order number 9398 652 90011).

Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joints for more than 5 seconds.

The total contact time of successive solder waves must not
exceed 5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg(max)

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300

C it may remain in contact for up to

10 seconds. If the bit temperature is between
300 and 400

C, contact may be up to 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

DIPPING

WAVE

DBS, DIP, HDIP, SDIP, SIL

suitable

(1)

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

SCA

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Internet: http://www.semiconductors.philips.com

1999

Philips Semiconductors a worldwide company

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777

Printed in The Netherlands

545004/100/01/pp

Date of release:

1999 Dec 22

Document order number:

9397 750 06197

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