January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

FEATURES

Multistandard vision IF circuit (positive and
negative modulation)

Video identification circuit in the IF circuit which is
independent of the synchronization for stable On Screen
Display (OSD) under `no-signal' conditions

Source selection with 2 Colour Video Blanking
Synchronization (CVBS) inputs and a Y/C (or extra
CVBS) input

Output signals of the video switch circuit for the teletext
decoder and a Picture-In-Picture (PIP) processor

Integrated chrominance trap and bandpass filters
(automatically calibrated)

Integrated luminance delay line

Asymmetrical peaking in the luminance channel with a
(defeatable) noise coring function

PAL/NTSC colour decoder with automatic search
system

Easy interfacing with the TDA8395 (SECAM decoder)
for multistandard applications

RGB control circuit with black-current stabilization and
white point adjustment; to obtain a good grey scale
tracking the black-current ratio of the 3 guns depends on
the white point adjustment

Linear RGB inputs and fast blanking

Horizontal synchronization with two control loops and
alignment-free horizontal oscillator

Vertical count-down circuit

Geometry correction by means of modulation of the
vertical and EW drive

C-bus control of various functions

Low dissipation (850 mW)

Small amount of peripheral components compared with
competition ICs

Only one adjustment (vision IF demodulator)

Y, U and V inputs and outputs.

GENERAL DESCRIPTION

The TDA8366 is an I

C-bus controlled PAL/NTSC TV

processor. The circuit has been designed for use with the
baseband chrominance delay line TDA4665 and for
DC-coupled vertical and East-West (EW) output stages.

The device can process both CVBS and Y/C input signals
and has a linear RGB-input with fast blanking.

The peaking circuit generates asymmetrical overshoots
(the amplitude of the `black' overshoots is approximately
2 times higher as the one of the `white' overshoots) and
contains a (defeatable) coring function.

The RGB control circuit contains a black-current stabilizer
circuit with internal clamp capacitors. The white point of the
picture tube is adjusted via the I

C-bus.

The deflection control circuit provides a drive pulse for the
horizontal output stage, a differential sawtooth current for
the vertical output stage and an East-West drive current for
the East-West output stage.These signals can be
manipulated for geometry correction of the picture.

The supply voltage for the IC is 8 V. The IC is available in
an SDIP package with 52 pins and in a QFP package with
64 pins (see Chapter "Ordering information").

The pin numbers indicated in this document are
referenced to the SDIP52; SOT247-1 package; unless
otherwise indicated.

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

ORDERING INFORMATION

Note

1. When using IR reflow soldering it is recommended that the Drypack instructions in the

"Quality Reference Handbook"

(order number 9398 510 63011) are followed.

QUICK REFERENCE DATA

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8366

SDIP52

plastic shrink dual in-line package; 52 leads (600 mil)

SOT247-1

TDA8366H

QFP64

(1)

plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14

2.8 mm

SOT319-2

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

8.0

supply current

100

Input voltages

46,47(rms)

video IF amplifier sensitivity (RMS value)

15(p-p)

external CVBS input (peak-to-peak value)

1.0

9(p-p)

S-VHS luminance input voltage (peak-to-peak value)

1.0

8(p-p)

S-VHS chroma input voltage (burst amplitude)
(peak-to-peak value)

0.3

21,22,23(p-p)

RGB inputs (peak-to-peak value)

0.7

Output signals

o(p-p)

demodulated CVBS output (peak-to-peak value)

2.5

tuner AGC output current range

36(p-p)

TXT output voltage (peak-to-peak value)

1.0

13(p-p)

PIP output voltage (peak-to-peak value)

1.0

28(p-p)

Y) output voltage (peak-to-peak value)

525

27(p-p)

Y) output voltage (peak-to-peak value)

675

Y output voltage

450

19,18,17(p-p)

RGB output signal amplitudes (peak-to-peak value)

2.0

horizontal output current

44,45

vertical output current

EW drive output current

0.5

January 1995

Philips Semiconductors

Objective specification

C-bus controlled P

AL/NTSC TV

processor

TDA8366

BLOCK DIAGRAM

handbook, full pagewidth

MLA745 - 1

AFC AND

SAMPLE AND HOLD

IF AMPLIFIER

AND DEMODULATOR

VIDEO

IDENTIFICATION

AGC FOR IF

AND TUNER

VIDEO

AMPLIFIER

VIDEO MUTE

CVBS - SWITCH

S-VHS - SWITCH

BANDPASS

TRAP

SOUND

TRAP

CONTROL DACs

17 x 6 bits

2 x 4 bits

PAL/NTSC

DECODER

FILTER

TUNING

VERTICAL

SYNC

SEPARATOR

SYNC

SEPARATOR

AND 1st LOOP

VCO

AND

CONTROL

I C-BUS

TRANSCEIVER

4.4

MHz

3.6

MHz

14 31

2nd LOOP AND

HORIZONTAL

OUTPUT

HORIZONTAL/

VERTICAL

DIVIDER

DELAY

AND

PEAKING

G-Y MATRIX

AND

SAT CONTROL

TDA4661

EW GEOMETRY

VERTICAL

GEOMETRY

BLACK

CURRENT

STABILIZER

RGB MATRIX

AND

OUTPUT

RGB INPUT

AND

SWITCH

BRI

CONTR

WHITE

POINT

V ( 8 V)

26 25

21 22 23 24

LUMOUT

LUMIN

RI GI BI

RGBIN

CHROMA

CVBS/Y

PIPO

CVBS/TXT

CVBSEXT

DEC

DET

XTAL2 XTAL1

DECDIG

DECBG

GND1

GND2

PH1LF

CVBS

IFVO

INT

AFC

IDENT

IFIN1

IFDEM2

IFDEM1

IFIN2

POL

AGCOUT

(TUNER)

MUTE

POL

TOP

SCL

SDA

HOUT

SCO

FBI

PH2LF

ref

HUE

SAT

BCLIN

BLKIN

EWD

EHTO

VDR

VSC

VDR(neg)

(pos)

SEC

RYO BYO

BYI

RYI

TDA8366

DEC AGC

ref

I ref

V ( 8 V)

Fig.1 Block diagram (SDIP52; SOT247-1).

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

PINNING

SYMBOL

PIN

DESCRIPTION

SDIP52

QFP64

IFDEM1

IF demodulator tuned circuit 1

IFDEM2

IF demodulator tuned circuit 2

DEC

DIG

decoupling digital supply

IFVO

IF video output

SCL

serial clock input

SDA

serial data input/output

DEC

bandgap decoupling

CHROMA

chrominance input (S-VHS)

CVBS/Y

external CVBS/Y input

main supply voltage 1 (+8 V)

CVBS

INT

internal CVBS input

GND1

ground 1

PIPO

picture-in-picture output

DEC

decoupling filter tuning

CVBS

EXT

external CVBS input

BLKIN

black-current input

blue output

green output

red output

BCLIN

beam current limiter input

red input for insertion

green input for insertion

blue input for insertion

RGBIN

RGB insertion input

LUMIN

luminance input

LUMOUT

luminance output

BYO

Y) signal output

RYO

Y) signal output

BYI

Y) signal input

RYI

Y) signal input

SEC

ref

SECAM reference output

XTAL1

3.58 MHz crystal connection

XTAL2

4.43/3.58 MHz crystal connection

DET

loop filter phase detector

horizontal oscillator supply voltage (+8 V)

CVBS/TXT

CVBS/TXT output

SCO

sandcastle output

HOUT

horizontal output

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

The pin numbers mentioned in the rest of this document are referenced to the SDIP52 (SOT247-1) package.

FBI

flyback input

PH2LF

phase-2 filter

PH1LF

phase-1 filter

GND2

ground 2

EWD

east-west drive output

VDR

(pos)

vertical drive 1 positive output

VDR

(neg)

vertical drive 2 negative output

IFIN1

IF input 1

IFIN2

IF input 2

EHTO

EHT/overvoltage protection input

VSC

vertical sawtooth capacitor

ref

reference current input

DEC

AGC

AGC decoupling capacitor

AGCOUT

tuner AGC output

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

supply voltage 3 (+8 V)

GND3

ground 3

GND4

ground 4

SYMBOL

PIN

DESCRIPTION

SDIP52

QFP64

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

FUNCTIONAL DESCRIPTION

Vision IF amplifier

The IF-amplifier contains 3 AC-coupled control stages with
a total gain control range which is in excess of 66 dB. The
sensitivity of the circuit is comparable with that of modern
IF-ICs. The reference carrier for the video demodulator is
obtained by means of passive regeneration of the picture
carrier. The external reference tuned circuit is the only
remaining adjustment of the IC.

The polarity of the demodulator can be switched via the
I

C-bus in such a way that the circuit is suitable for both

positive and negative modulated signals.

The AFC-circuit is driven with the same reference signal as
the video demodulator. To avoid that the video content
disturbs the AFC operation a sample-and-hold circuit is
applied for signals with negative modulation. The capacitor
for this function is internal. The AFC information is supplied
to the tuning system via the I

C-bus.

The AGC-detector operates on top-sync or top white-level
depending on the polarity of the demodulator. The
demodulation polarity is switched via the I

C-bus. The

AGC detector time-constant capacitor is connected
externally (this mainly because of the flexibility of the
application). The time-constant of the AGC system during
positive modulation is rather long to avoid visible variations
of the signal amplitude. To obtain an acceptable speed of
the AGC system a circuit has been included which detects
whether the AGC detector is activated every frame period.
When during 3 frame periods no action is detected the
speed of the system is increased.

The circuit contains a video identification circuit which is
independent of the synchronization circuit. Therefore
search tuning is possible when the display section of the
receiver is used as a monitor. The identification output is
supplied to the tuning system via the I

C-bus. The

information of this identification circuit can also be used to
switch the phase-1 (

) loop to a low gain when no signal

is received so that a stable OSD display is obtained. The
coupling of the video identification circuit with the

loop

can be switched on and off via the I

C-bus.

Synchronization circuit

The sync separator is preceded by a controlled amplifier
which adjusts the sync pulse amplitude to a fixed level.
These pulses are fed to the slicing stage which is operating
at 50% of the amplitude.

The separated sync pulses are fed to the first phase
detector and to the coincidence detector. This coincidence
detector is only used to detect whether the line oscillator is
synchronized and not for transmitter identification. The first
Phase-Locked Loop (PLL) has a very high-statical
steepness so that the phase of the picture is independent
of the line frequency.

The line oscillator is running at twice the line frequency.
The oscillator capacitor is internal. Because of the spreads
of internal components an automatic adjustment circuit
has been added to the IC. It compares the oscillator
frequency with that of the crystal oscillator in the colour
decoder.

To protect the horizontal output transistor the horizontal
drive is switched-off when a power-on-reset is detected.
The frequency of the oscillator is calibrated again when all
subaddress bytes have been sent. When the oscillator has
the right frequency the calibration stops and the horizontal
drive is switched-on again via the soft start procedure
(standby bit in normal mode). When the IC is switched-on
the same procedure is followed.

When the coincidence detector indicates an out-of-lock
situation the calibration procedure is repeated.

The circuit has a second control loop to generate the drive
pulses for the horizontal driver stage. During the start-up
procedure the duty cycle of the horizontal output pulse
increases from 0 to 50% in approximately 100 lines.

The vertical sawtooth generator drives the vertical output
and EW correction drive circuits. The geometry processing
circuits provide control of horizontal shift, EW width, EW
parabola/width ratio, EW corner/parabola ratio, trapezium
correction, vertical shift, vertical slope, vertical amplitude,
and the S-correction. All these controls can be set via the
I

C-bus. The geometry processor has a differential current

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

output for the vertical drive signal and a single-ended
output for the EW drive. Both the vertical drive and the EW
drive outputs can be modulated for EHT compensation.
The EHT compensation pin is also used for overvoltage
protection.

The geometry processor also offers the possibilities for
vertical compression (for display of 16 : 9 pictures on a
4 : 3 screen) and vertical expansion (for display of
4 : 3 pictures on a 16 : 9 screen with full picture width, or
for display of `letter-box' transmissions on a 4 : 3 screen
with full picture height). For the expand mode it is possible
to shift the picture vertically (only one fixed position).

Also the de-interlace of the vertical output can be set via
the I

C-bus.

To avoid damage of the picture tube when the vertical
deflection fails the guard output current of the TDA8350
can be supplied to the sandcastle output. When a failure is
detected the RGB-outputs are blanked and a bit is set
(NDF) in the status byte of the I

C-bus. When no vertical

deflection output stage is connected this guard circuit will
also blank the output signals. This can be overruled by
means of the EVG bit of subaddress 0A (see Table 1).

Integrated video filters

The circuit contains a chrominance bandpass and trap
circuit. The chrominance trap filter in the luminance path is
designed for a symmetrical step response behaviour. The
filters are realized by means of gyrator circuits and they
are automatically tuned by comparing the tuning frequency
with the crystal frequency of the decoder. The luminance
delay line and the delay for the peaking circuit are also
realized by means of gyrator circuits.

It is possible to connect a Colour Transient Improvement
(CTI) or Picture Signal Improvement (PSI) IC to the
TDA8366. Therefore the luminance signal which has
passed the filter and delay line circuit is externally
available. The output signal of the transient improvement
circuit must be supplied to the luminance input circuit.
When the CTI function is not required the two pins must be
AC-coupled.

Video switches

The circuit has two CVBS inputs and an Super-Video
Home System (S-VHS) input. The input can be chosen by
the I

C-bus. The input selector also has a position in which

CVBS

EXT

is processed, unless there is a signal on the

S-VHS input. When the input selector is in this position it
switches to the S-VHS input if the S-VHS detector detects
sync pulses on the S-VHS luminance input. The S-VHS
detector output can be read by the I

C-bus. When the

S-VHS option is not used the luminance input can be used
as a second input for external CVBS signals. The choice is
made via the CVS-bit (see Table 1).

The video switch circuit has two outputs which can be
programmed in a different way. The input signal for the
decoder is also available on the TXT output. Therefore this
signal can be used to drive the teletext decoder and the
SECAM add-on decoder. The signal on the PIP output can
be chosen independent of the TXT output. If S-VHS is
selected for one of the outputs the luminance and
chrominance signals are added so that a CVBS signal is
obtained again.

Colour decoder

The colour decoder contains an alignment-free crystal
oscillator, a killer circuit and the colour difference
demodulators. The 90

phase shift for the reference signal

is made internally. The demodulation angle and gain ratio
for the colour difference signals for PAL and NTSC are
adapted to the standard.

The colour decoder is very flexible. Together with the
SECAM decoder TDA8395 an automatic multistandard
decoder can be designed.

Which standard the IC can decode depends on the
external crystals. If a 4.4 MHz and a 3.5 MHz crystal are
used PAL 4.4, NTSC 4.4, NTSC 3.5 and PAL 3.5 can be
decoded. If two 3.5 MHz crystals are used PAL N and M
can be decoded. If one crystal is connected only
PAL/NTSC 4.4 or PAL/NTSC 3.5 can be decoded. The
crystal frequency of the decoder is used to tune the line
oscillator. Therefore the value of the crystal frequency
must be given to the IC via the I

C-bus.

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

RGB output circuit and black-current stabilization

The colour-difference signals are matrixed with the
luminance signal to obtain the RGB-signals. For the
RGB-inputs linear amplifiers have been chosen so that the
circuit is suited for signals coming from the SCART
connector. The contrast and brightness control operate on
internal and external signals.

The output signal has an amplitude of approximately 2 V
black-to-white at nominal input signals and nominal
settings of the controls.

The black current stabilization is realized by means of a
feedback from the video output amplifiers to the RGB
control circuit. The `black current' of the 3 guns of the
picture tube is internally measured and stabilized. The
black level control is active during 4 lines at the end of the
vertical blanking. During the first line the leakage current is
measured and the following 3 lines the 3 guns are
adjusted to the required level. The maximum acceptable
leakage current is

100

A. The nominal value of the

`black current' is 10

A. The ratio of the currents for the

various guns automatically tracks with the white point
adjustment so that the back-ground colour is the same as
the adjusted white point.

The input impedance of the `black-current' measuring pin
is 15 k

. Therefore the beam current during scan will

cause the input voltage to exceed the supply voltage. The
internal protection will start conducting so that the
excessive current is bypassed.

When the TV receiver is switched-on the black current
stabilization circuit is not active, the RGB outputs are
blanked and beam current limiting input pin is
short-circuited. Only during the measuring lines will the
outputs supply a voltage of 5 V to the video output stage
so that it can be detected if the picture tube is warming up.
These pulses are switched-on after a waiting time of
approximately 0.5 s. This ensures that the vertical
deflection is activated so that the measuring pulses are not

visible on the screen. As soon as the current supplied to
the measuring input exceeds a value of 190

A the

stabilization circuit is activated. After a waiting time of
approximately 0.8 s the blanking and the beam current
limiting input pin are released. The remaining switch-on
behaviour of the picture is determined by the external time
constant of the beam current limiting network.

C-BUS SPECIFICATION

Valid subaddresses: 00 to 13; subaddress FE is reserved
for test purposes. Auto-increment mode is available for
subaddresses.

Start-up procedure

Read the status bytes until POR = 0 and send all
subaddress bytes. The horizontal output signal is
switched-on when the oscillator is calibrated. It is possible
to have the horizontal output signal available before
calibration. Then the SFM bit must be set to logic 0.

Each time before the data in the IC is refreshed, the status
bytes must be read. If POR = 1, the procedure mentioned
above must be carried out to restart the IC.

When this procedure is not followed the horizontal
frequency may be incorrect after power-up or after a
power dip.

handbook, halfpage

MLA743

1/0

R/W

Fig.4 Slave address (8A).

X = don't care.

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

Inputs

Table 1

Input status bits; note 1

Note

1. X = don't care.

Table 2

Output status bits; note 1

Note

1. X = don't care.

FUNCTION

SUBADDRESS

(HEX)

DATA BYTE

Source select

INA

INB

INC

IND

FOA

FOB

Decoder mode

FORF

FORS

STB

POC

CM2

CM1

CM0

Hue

Horizontal shift (HS)

EW width (EW)

EW parabola/width (PW)

EW corner parabola (CP)

EW trapezium (TC)

Vertical slope (VS)

NCIN

Vertical amplitude (VA)

VID

LBM

S-correction (SC)

HCO

EVG

Vertical shift (VSH)

SBL

PRD

White point R

EXP

White point G

SFM

CVS

White point B

MAT

PHL

Peaking

YD3

YD2

YD1

YD0

Brightness

RBL

COR

Saturation

IE1

Contrast

AFW

IFS

AGC take-over

MOD

VSW

FUNCTION

SUBADDRESS

(HEX)

DATA BYTE

Output status bytes

POR

FSI

STS

XPR

CD2

CD1

CD0

NDF

IN1

IFI

AFA

AFB

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

NPUT CONTROL BITS

Table 3

Source select 1

Table 4

Source select 2

Table 5

Phase 1 (

) time constant

Note

1. X = don't care.

Table 6

Crystal indication

INA

INB

DECODER AND TXT

CVBS

INT

CVBS

EXT

S-VHS

S-VHS (CVBS

EXT

)

INC

IND

PIP

CVBS

INT

CVBS

EXT

S-VHS

S-VHS (CVBS

EXT

)

FOA

FOB

(1)

MODE

normal

slow

fast

CRYSTAL

two 3.6 MHz

one 3.6 MHz (pin 32)

one 4.4 MHz (pin 33)

3.6 MHz (pin 32) and 4.4 MHz
(pin 33)

Table 7

Forced field frequency

Note

1. When the forced mode is selected the divider will only

switch to that position when the horizontal oscillator is
not synchronized.

Table 8

Interlace

Table 9

Standby

Table 10 Synchronization mode

Table 11 Colour decoder mode

FORF

FORS

FIELD FREQUENCY

auto (60 Hz when line not
synchronized)

60 Hz; note 1

50 Hz; note 1

auto (50 Hz when line not
synchronized)

STATUS

interlace

de-interlace

STB

MODE

standby

normal

POC

MODE

active

not active

CM2

CM1

CM0

DECODER MODE

not forced, own intelligence

forced NTSC 3.6 MHz

forced PAL 4.4 MHz

forced SECAM

forced NTSC 4.4 MHz

forced PAL 3.6 MHz (pin 32)

forced PAL 3.6 MHz (pin 33)

no function

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

Table 12 Vertical divider mode

Table 13 Video ident mode

Table 14 Long blanking mode

Table 15 EHT tracking mode

Table 16 Enable vertical guard (RGB blanking)

Table 17 Service blanking

Table 18 Overvoltage input mode

Table 19 Vertical deflection mode

NCIN

VERTICAL DIVIDER MODE

normal operation

switched to search window

VID

VIDEO IDENT MODE

loop switched on and off

not active

LBM

BLANKING MODE

adapted to standard (50 or 60 Hz)

fixed in accordance with 50 Hz standard

HCO

TRACKING MODE

EHT tracking only on vertical

EHT tracking on vertical and EW

EVG

VERTICAL GUARD MODE

not active

active

SBL

SERVICE BLANKING MODE

off

PRD

OVERVOLTAGE MODE

detection mode

protection mode

EXP

VERTICAL DEFLECTION MODE

normal

compress

expand

expand and lift

Table 20 Horizontal frequency during switch-on

Table 21 Condition Y/C input

Table 22 PAL/NTSC matrix

Table 23 Colour crystal PLL

Table 24 Y-delay adjustment; note 1

Note

1. For an equal delay of the luminance and chrominance

signal the delay must be set at a value of 160 ns. This
is only valid for a CVBS signal without group
delay distortions.

Table 25 RGB blanking

Table 26 Noise coring (peaking)

SFM

START-UP FREQUENCY

maximum

nominal

CVS

Y-INPUT MODE

switched to Y/C mode

switched to CVBS mode

MAT

MATRIX

adapted to standard

PAL

PHL

STATE

PLL closed

oscillator free-running

YD0 to YD3

Y-DELAY

YD3

160 ns +

YD2

80 ns +

YD1

40 ns +

YD0

40 ns

RBL

RGB BLANKING

not active

active

COR

NOISE CORING

off

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

Table 27 Enable fast blanking

Table 28 AFC window

Table 29 IF sensitivity

Table 30 Modulation standard

Table 31 Video mute

UTPUT CONTROL BITS

Table 32 Power-on-reset

Table 33 Field frequency indication

Table 34 S-VHS status

IE1

FAST BLANKING

not active

active

AFW

AFC WINDOW

normal

enlarged

IFS

IF SENSITIVITY

normal

reduced

MOD

MODULATION

negative

positive

VSW

STATE

normal operation

IF-video signal switched off

POR

MODE

normal

power-down

FSI

FREQUENCY

50 Hz

60 Hz

STS

S-VHS INPUT

no signal

signal

Table 35 Phase 1 (

) lock indication

Table 36 X-ray protection

Table 37 Colour decoder mode

Table 38 Output vertical guard

Table 39 Indication RGB insertion

Table 40 Output video identification

INDICATION

not locked

locked

XPR

OVERVOLTAGE

no overvoltage detected

overvoltage detected

CD2

CD1

CD0

STANDARD

no colour standard identified

NTSC 3.6 MHz

PAL 4.4 MHz

SECAM

NTSC 4.4 MHz

PAL 3.6 MHz (pin 32)

PAL 3.6 MHz (pin 33)

spare

NDF

VERTICAL OUTPUT STAGE

failure

IN1

RGB INSERTION

no (pin 24 LOW)

yes (pin 24 HIGH)

IFI

VIDEO SIGNAL

no video signal identified

video signal identified

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

Table 41 AFC output

AFA

AFB

CONDITION

outside window; too low

outside window; too high

in window; below reference

in window; above reference

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. All pins are protected against ESD by means of internal clamping diodes.

2. Human Body Model (HBM): R = 1.5 k

; C = 100 pF.

3. Machine Model (MM): R = 0

; C = 200 pF.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

9.0

stg

storage temperature

+150

amb

operating ambient temperature

sol

soldering temperature

for 5 s

260

operating junction temperature

150

electrostatic handling

HBM; all pins; notes 1 and 2

2000

+2000

MM; all pins; notes 1 and 3

200

+200

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

SDIP52

K/W

QFP64

K/W

QUALITY SPECIFICATION

In accordance with

"SNW-FQ-611E". The number of the

quality specification can be found in the

"Quality

Reference Handbook". The handbook can be ordered
using the code 9398 510 63011.

Latch-up

trigger

100 mA or

1.5V

DD(max)

trigger

100 mA or

0.5V

DD(max)

Following pins do not meet the above specification:

Pin 7:

90 mA

Pin 17: 90 mA

Pin 18: 90 mA

Pin 19: 90 mA

Pin 24:

90 mA

Pin 34: 60 mA

Pin 49:

90 mA

Pin 50:

90 mA.

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

CHARACTERISTICS

= 8 V; T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

AIN SUPPLY

(

10)

supply voltage

7.2

8.0

8.8

supply current

100

tot

total power dissipation

850

ORIZONTAL OSCILLATOR SUPPLY

(

35)

supply voltage

7.2

8.0

8.8

supply current

IF circuit

ISION

AMPLIFIER INPUTS

(

PINS

AND

47)

i(rms)

input sensitivity (RMS value)

note 1

= 38.90 MHz

100

= 45.75 MHz

100

= 58.75 MHz

100

input resistance (differential)

note 2

input capacitance (differential)

note 2

gain control range

i max(rms)

maximum input signal
(RMS value)

100

150

IDEO AMPLIFIER OUTPUT

(

4); note 3

zero signal output level

negative modulation; note 4

4.7

positive modulation; note 4

2.0

top sync level

negative modulation

1.9

2.0

2.1

white level

positive modulation

4.5

difference in amplitude between
negative and positive
modulation

video output impedance

bias

internal bias current of NPN
emitter follower output transistor

1.0

source(max)

maximum source current

bandwidth of demodulated
output signal

3 dB

MHz

diff

differential gain

note 5

diff

differential phase

notes 5 and 6

deg

vid

video non-linearity

note 7

white spot threshold level

5.0

ins

white spot insertion level

3.3

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

IDEO AMPLIFIER OUTPUT

(

CONTINUED

)

clamp

noise inverter clamping level

1.4

ins

noise inverter insertion level
(identical to black level)

2.6

mod

intermodulation

notes 6 and 8

blue

= 0.92 or 1.1 MHz

= 2.66 or 3.3 MHz

yellow

= 0.92 or 1.1 MHz

= 2.66 or 3.3 MHz

S/N

signal-to-noise ratio

notes 6 and 9

= 10 mV

end of control range

residual carrier signal

note 6

5.5

residual 2nd harmonic of carrier
signal

note 6

2.5

AND TUNER

AGC; note 10

timing of IF-AGC with a 2.2

F capacitor (pin 51)

modulated video interference

30% AM for 1 mV to 100 mV;
0 to 200 Hz (system B/G)

inc

response time to an IF input
signal amplitude increase of
52 dB

positive and negative
modulation

dec

response to an IF input signal
amplitude decrease of 52 dB

negative modulation

positive modulation

100

allowed leakage current of the
AGC capacitor

negative modulation

positive modulation

200

Tuner take-over adjustment (via I

C-bus)

51min(rms)

minimum starting level for tuner
take-over (RMS value)

0.4

0.8

51max(rms)

maximum starting level for tuner
take-over (RMS value)

Tuner control output (pin 52)

52max

maximum tuner AGC output
voltage

maximum tuner gain; note 2

+ 1

52(sat)

output saturation voltage

minimum tuner gain;
I

= 2 mA

300

52max

maximum tuner AGC output
swing

leakage current RF AGC

input signal variation for
complete tuner control

0.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

AFC

OUTPUT

(

VIA

C-

BUS

); note 11

RES

AFC resolution

bits

sen

window sensitivity

100

kHz

senL

window sensitivity in large
window mode

195

240

300

kHz

AFC offset

note 6

kHz

IDEO IDENTIFICATION OUTPUT

(

VIA

C-

BUS

)

delay time of identification after
the AGC has stabilized on a
new transmitter

CVBS and S-VHS input switch

NTERNAL AND EXTERNAL

CVBS

INPUTS

(

PINS

AND

15)

11(p-p)

CVBS input voltage
(peak-to-peak value)

note 12

1.0

1.4

CVBS input current

CVBS

suppression of non-selected
CVBS input signal

notes 6 and 13

S-VHS

INPUT

(

PINS

AND

9(p-p)

luminance input voltage
(peak-to-peak value)

1.0

1.4

9(p-p)

luminance input current

chrominance input voltage
(burst amplitude)

note 14

0.3

0.45

chrominance input current

TXT

AND

PIP

OUTPUT SIGNALS

(

PINS

AND

13)

o(p-p)

output signal amplitude
(peak-to-peak value)

1.0

output impedance

250

top sync level

2.5

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

RGB inputs, colour difference inputs, luminance inputs and outputs

RGB

INPUTS

(

PINS

21, 22

AND

23)

21,22,23(p-p)

input signal amplitude for an
output signal of 2 V
(black-to-white) (peak-to-peak
value)

note 15

0.7

0.8

21,22,23(p-p)

input signal amplitude before
clipping occurs (peak-to-peak
value)

note 6

1.0

difference between black level
of internal and external signals
at the outputs

21,22,23

input currents

no clamping; note 2

0.5

delay difference for the three
channels

note 6

AST BLANKING

(

24)

input voltage

no data insertion

0.4

data insertion

0.9

24(max)

maximum input pulse

insertion

3.0

delay time from RGB in to
RGB out

data insertion; note 6

100

delay difference between
insertion to RGB out and
RGB in to RGB out

data insertion; note 6

input current

0.2

int

suppression of internal RGB
signals

notes 6 and 12; insertion;
f

= 0 to 5 MHz

ext

suppression of external RGB
signals

notes 6 and 12; no insertion;
f

= 0 to 5 MHz

input voltage to blank the RGB
outputs to facilitate `On Screen
Display' signals being applied to
the outputs

OLOUR DIFFERENCE INPUT SIGNALS

(

PINS

AND

30)

30(p-p)

input signal amplitude (R

(peak-to-peak value)

note 2

1.05

29(p-p)

input signal amplitude (B

(peak-to-peak value)

note 2

1.35

29,30

input current for both inputs

note 2

0.1

1.0

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PARAMETER

CONDITIONS

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UNIT

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

UMINANCE INPUTS AND OUTPUTS

(

PINS

AND

26)

26(p-p)

output signal amplitude
(peak-to-peak value)

top sync-white

0.45

0.63

top sync level

2.5

output impedance

250

25(p-p)

input signal amplitude
(peak-to-peak value)

0.45

clamp

clamp current

during burst key pulse

200

input current

no clamp

0.5

Chrominance filters

HROMINANCE TRAP CIRCUIT

trap

trap frequency

osc

MHz

trap quality factor

note 16

colour subcarrier rejection

HROMINANCE BANDPASS CIRCUIT

centre frequency

osc

MHz

QBP

bandpass quality factor

Delay line and peaking circuit

DELAY LINE

delay time

note 6

480

tuning range delay time

8 steps

160

+160

bandwidth of internal delay line

note 6

MHz

EAKING CONTROL

; note 17

c(p)

peaking centre frequency

MHz

width of preshoot or overshoot

note 2

160

overshoot

positive

negative

peaking control curve

16 steps

see Fig.5

ORING STAGE

coring range

IRE

wave gain

1.8

Horizontal synchronization circuits

YNC VIDEO INPUT

(

PINS

9, 11

AND

15)

9,11,15

sync pulse amplitude

note 2

300

slicing level for horizontal sync

note 18

slicing level for vertical sync

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

negative half wave gain

positive half wave gain

--------------------------------------------------------------

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

ORIZONTAL OSCILLATOR

free running frequency

15625

spread on free running
frequency

frequency variation with respect
to the supply voltage

= 8.0 V

10%; note 6

0.2

0.5

(max)

frequency variation with
temperature

amb

= 0 to 70

C; note 6

osc(max)

maximum frequency deviation
at the start of the horizontal
output

IRST CONTROL LOOP

(

FILTER CONNECTED TO PIN

41); note 19

holding range PLL

0.9

1.2

kHz

catching range PLL

note 6

0.6

0.9

kHz

S/N

signal-to-noise ratio of the video
input signal at which the time
constant is switched

HYS

hysteresis at the switching point

ECOND CONTROL LOOP

(

CAPACITOR CONNECTED TO PIN

40)

control sensitivity

150

control range from start of
horizontal output to flyback at
nominal shift position

shift

horizontal shift range

63 steps

control sensitivity for dynamic
compensation

5.3

s/V

ORIZONTAL OUTPUT

(

38); note 20

LOW level output voltage

= 10 mA

0.3

O(max)

maximum allowed output
current

O(max)

maximum allowed output
voltage

duty factor

note 6

LYBACK PULSE INPUT

(

39)

HSW

switching level for horizontal
blanking

0.4

2(SW)

switching level for phase-2 loop

4.0

39(max)

maximum input voltage

note 2

8.0

input impedance

note 2

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

ANDCASTLE PULSE OUTPUT

(

37)

output voltage

during burst key

4.8

5.3

5.8

during blanking

1.8

2.0

2.2

pulse width

burst key pulse

3.3

3.5

3.7

vertical blanking (50 Hz)

lines

vertical blanking (60 Hz)

lines

clamp

clamp level for vertical guard
detection

2.7

37(min)

minimum input current to
activate guard detection

0.5

37(max)

maximum allowable input
current

2.5

delay of start of burst key to
start of sync

5.4

OFT START

; note 21

duty factor control range

soft start time

100

lines

Vertical synchronization and geometry correction

ERTICAL OSCILLATOR

; note 22

free running frequency

50/60

lock

locking range

64.5

divider value not locked

625/525

lines

locking range

488

722

lines/
frame

ERTICAL RAMP GENERATOR

(

49)

49(p-p)

sawtooth amplitude
(peak-to-peak value)

VS = 1FH;
C = 100 nF; R = 39 k

3.5

dis

discharge current

charge

charge current set by external
resistor

note 23

vertical slope

control range (63 steps)

+14

compress mode

expand mode

133

charge current increase

f = 60 Hz

49L

LOW level of ramp

normal or expand mode

2.07

compress mode

2.55

ERTICAL DRIVE OUTPUTS

(

PINS

AND

45)

diff(p-p)

differential output current
(peak-to-peak value)

VA = 1FH

common mode current

400

output voltage range

4.0

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

EHT

TRACKING

OVERVOLTAGE PROTECTION

(

48)

input voltage

1.2

2.8

SMR

scan modulation range

vert

vertical sensitivity

7.5

%/V

EW sensitivity

when switched-on

7.5

%/V

EW equivalent output current

+120

120

overvoltage detection level

3.9

INTERLACE

first field delay

0.5H

WIDTH

control range

63 steps

100

equivalent output current

400

EW output voltage range

1.0

8.0

EW output current range

900

PARABOLA

WIDTH

control range

63 steps

equivalent output current

EW = 3FH

480

CORNER

PARABOLA

control range

63 steps

equivalent output current

PW = 3FH; EW = 3FH

210

TRAPEZIUM

control range

63 steps

equivalent output current

+80

ERTICAL AMPLITUDE

control range

63 steps; SC = 00H

120

63 steps; SC = 3FH

112

eqdiff(p-p)

equivalent differential vertical
drive output current
(peak-to-peak value)

SC = 00H

800

1200

ERTICAL SHIFT

control range

63 steps

eqdiff(p-p)

equivalent differential vertical
drive output current
(peak-to-peak value)

+40

S-

CORRECTION

control range

63 steps

SYMBOL

PARAMETER

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MIN.

TYP.

MAX.

UNIT

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

Colour demodulation part

HROMINANCE AMPLIFIER

ACC

ACC control range

note 24

change in amplitude of the
output signals over the ACC
range

THR

threshold colour killer ON

HYS

off

hysteresis colour killer OFF

strong signal conditions;
S/N

40 dB; note 6

noisy input signals; note 6

ACL

CIRCUIT

chrominance burst ratio at
which the ACL starts to operate

2.3

2.7

EFERENCE PART

Phase-locked loop; note 25

catching range

300

500

phase shift for a

400 Hz

deviation of the oscillator
frequency

note 6

deg

Oscillator

osc

temperature coefficient of the
oscillator frequency

note 6

2.0

2.5

Hz/K

osc

oscillator frequency deviation
with respect to the supply

note 6; V

= 8 V

10%

250

input resistance

pin 32; f = 3.58 MHz; note 2

1.5

pin 33; f = 4.43 MHz; note 2

1.0

input capacitance

pins 32 and 33; note 2

UE CONTROL

HUE

hue control range

63 steps; see Fig.6

deg

HUE

hue variation for

10% V

note 6

deg

HUE/

hue variation with temperature

amb

= 0 to 70

C; note 6

deg

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

EMODULATORS

(

PINS

AND

28)

28(p-p)

Y) output signal amplitude

(peak-to-peak value)

note 26

0.525

27(p-p)

Y) output signal amplitude

(peak-to-peak value)

note 26

0.675

gain between both
demodulators G(B

Y) and

G(R

1.60

1.78

1.96

spread of signal amplitude ratio
PAL/NTSC

note 6

output impedance (R

Y)/(B

output

note 6

500

bandwidth of demodulators

3 dB; note 27

650

kHz

27,28(p-p)

residual carrier output
(peak-to-peak value)

f = f

osc

; (R

Y) output

f = f

osc

; (B

Y) output

f = 2f

osc

; (R

Y) output

f = 2f

osc

; (B

Y) output

28(p-p)

H/2 ripple at (R

Y) output

(peak-to-peak value)

change of output signal
amplitude with temperature

note 6

0.1

%/K

change of output signal
amplitude with supply voltage

note 6

0.1

phase error in the demodulated
signals

deg

OLOUR DIFFERENCE MATRICES IN CONTROL CIRCUIT

PAL or (SECAM mode with TDA8395); (R

Y) and (B

Y) not affected

Y)/(R

Y) ratio of demodulated signals

0.51

10%

Y)/(B

Y) ratio of demodulated signals

0.19

25%

NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting)

Y) signal

1.39(R

0.07(B

Y) signal

0.46(R

0.15(B

SYMBOL

PARAMETER

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MIN.

TYP.

MAX.

UNIT

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

EFERENCE SIGNAL OUTPUT FOR

TDA8395 (

31)

ref

reference frequency

4.43

MHz

31(p-p)

output signal amplitude
(peak-to-peak value)

0.2

0.25

0.3

output level

PAL/NTSC identified

1.5

no PAL/NTSC identified;
SECAM (by TDA8395)
identified

5.0

required current to stop
PAL/NTSC identification circuit
during SECAM

150

Control part

ATURATION CONTROL

; note 15

SAT

saturation control range

63 steps; see Fig.7

ONTRAST CONTROL

; note 15

CON

contrast control range

63 steps

tracking between the three
channels over a control range of
10 dB

see Fig.8

0.5

RIGHTNESS CONTROL

BRI

brightness control range

63 steps; see Fig.9

0.7

RGB

AMPLIFIERS

(

PINS

17, 18

AND

19)

17,18,19(p-p)

output signal amplitude
(peak-to-peak value)

at nominal luminance input
signal, nominal contrast and
white-point adjustment;
note 15

tbf

2.0

tbf

at maximum white point
setting

3.0

BWmax(p-p)

maximum signal amplitude
(black-to-white)

note 28

2.6

at maximum white point
setting

3.6

RED(p-p)

output signal amplitude for the
`red' channel (peak-to-peak
value)

at nominal settings for
contrast and saturation
control and no luminance
signal to the input (R

Y, PAL)

tbf

2.1

tbf

blank

blanking level at the RGB
outputs

0.7

0.8

0.9

bias

internal bias current of NPN
emitter follower output transistor

1.5

available output current

output impedance

150

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

RGB

AMPLIFIERS

(

CONTINUED

)

control range of the
black-current stabilization

nominal brightness and
white-point adjustment (with
respect to the measuring
pulse); V

blk

= 2.5 V

black level shift with picture
content

note 6

output voltage of the 4-L pulse
after switch-on

4.2

bl/

variation of black level with
temperature

note 6

1.0

mV/K

relative variation in black level
between the three channels
during variations of

note 6

supply voltage (

10%)

nominal controls

tbf

saturation (50 dB)

nominal contrast

tbf

contrast (20 dB)

nominal saturation

tbf

brightness (

0.5 V)

nominal controls

tbf

temperature (range 40

tbf

S/N

signal-to-noise ratio of the
output signals

RGB input; note 29

CVBS input; note 29

res(p-p)

residual voltage at the RGB
outputs (peak-to-peak value)

at f

osc

at 2f

osc

plus higher

harmonics in RGB outputs

bandwidth of output signals

RGB input; at

3 dB

MHz

CVBS input; at

3 dB;

osc

= 3.58 MHz

2.8

MHz

CVBS input; at

3 dB;

osc

= 4.43 MHz

3.5

MHz

S-VHS input; at

3 dB

MHz

HITE

POINT ADJUSTMENT

C-bus setting for nominal gain

HEX code

20H

inc(max)

maximum increase of the gain

HEX code 3FH

dec(max)

maximum decrease of the gain

HEX code 00H

LACK

CURRENT STABILIZATION

(

16); note 30

bias

bias current for the picture tube
cathode

leak

acceptable leakage current

100

scan(max)

maximum current during scan

0.3

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

Notes

1. On set AGC.

2. This parameter is not tested during production and is just given as application information for the designer of the

television receiver.

3. Measured at 10 mV (RMS) top sync input signal.

4. So called projected zero point, i.e. with switched demodulator.

5. Measured in accordance with the test line given in Fig.10. For the differential phase test the peak white setting is

reduced to 87%.

a) The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and

smallest value relative to the subcarrier amplitude at blanking level.

b) The phase difference is defined as the difference in degrees between the largest and smallest phase angle.

6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix

batches which are made in the pilot production period.

7. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.11.

8. The test set-up and input conditions are given in Fig.12. The figures are measured with an input signal of

10 mV RMS.

9. Measured with a source impedance of 75

, where:

10. To obtain a good noise immunity of the AGC circuit the AGC detector is gated during the sync pulse. This gating is

switched-off during the vertical retrace to avoid disturbances of the signal amplitude due to phase errors of the
incoming video signal which are caused by the head-switching of VCRs.

EAM CURRENT LIMITING

(

20); note 28

contrast reduction starting
voltage

diffCR

voltage difference for full
contrast reduction

brightness reduction starting
voltage

diffBR

voltage difference for full
brightness reduction

bias

internal bias voltage

4.5

ch(int)

internal charge current

disch

discharge current due to
`peak-white limiting'

200

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

S/N = 20 log

(black-to-white)

m rms

(

)

B = 5 MHz

(

)

---------------------------------------------------------

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

11. The AFC slope is directly related to the Q-factor of the demodulator tuned circuit. The given AFC steepness is

obtained with a Q-factor of 60. The AFC off-set is tested with a double sideband input signal and with the reference
tuned circuit tuned to minimum AGC voltage (optimum tuning for the demodulator).

The tuning information is supplied to the tuning system via the I

C-bus. Two bits have been reserved for this function.

The first bit indicates whether the tuning is within the given window. The second bit indicates the direction of the
tuning. Bit indications:

a) AFA = 1; tuning inside window.

b) AFA = 0; tuning outside window.

c) AFB = 1; tuning too high.

d) AFB = 0; tuning too low.

To improve the speed of search tuning systems the AFC window can be increased to about 240 kHz. The width of
the window can be set by means of the AFW bit in subaddress 03.

12. Signal with negative-going sync. Amplitude includes sync pulse amplitude.

13. This parameter is measured at nominal settings of the various controls.

14. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1).

15. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum

10 dB. In the nominal

brightness setting the black level at the outputs is identical to the level of the black-current measuring pulses.

16. The

3 dB bandwidth of the circuit can be calculated by means of the following equation:

17. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns

and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the
overshoots but by measuring the frequency response of the Y output.

18. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing

level and the black level (back porch).

19. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is

switched depending on the input signal condition and the condition of the I

C-bus. Therefore the circuit contains a

noise detector and the time constant is switched to `slow' when too much noise is present in the signal. In the `fast'
mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to
head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be
automatically or overruled by the I

C-bus.

The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be
used to close or open the first control loop when a video signal is present or not present on the input. This enables
a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification
circuit with the first loop can be defeated via the I

C-bus.

When the horizontal PLL is set to the `slow' mode (via I

C-bus bits FOA and FOB) or during weak signal conditions

in the `automatic' mode the phase detector is gated to obtain a good noise immunity. The width of the gating pulse
is 5.7

The output current of the phase detector in the various conditions are shown in Table 42.

20. During the start-up period of the oscillator the duty factor of the output pulse rises gradually from 0% to 50% (time

approximately 100 lines).

21. The start-up frequency depends on the SFM bit in the I

C-bus protocol. When SFM = 0 the frequency starts at a high

(non calibrated) value. When SFM = 1 the output signal will only be available after calibration.

3 dB

osc

--------

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

22. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This

divider circuit has 3 modes of operation:

a) Search mode `large window'.

This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per
frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode
the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz).

b) Standard mode `narrow window'.

This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator
is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch
back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window.

c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz).

When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in
accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the
standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync
pulse is missing.

When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.

The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit
in subaddress 08.

23. Conditions: frequency is 50 Hz; normal mode; VS = 1F.

24. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude

300 mV (p-p)) the dynamic range of the ACC is +6 and

20 dB.

25. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency.

All oscillator specifications are measured with the Philips crystal series 9922 520.
If the spurious response of the 4.43 MHz crystal is lower than

1 dB with respect to the fundamental frequency for a

damping resistance of 1 k

, oscillation at the fundamental frequency is guaranteed.

The spurious response of the 3.58 MHz crystal must be lower than

1 dB with respect to the fundamental frequency

for a damping resistance of 1.5 k

The catching and detuning range are measured for nominal crystal parameters. These are:

a) Load resonance frequency f

= 4.433619 or 3.579545 MHz; C

= 20 pF.

b) Motional capacitance C

= 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal).

c) Parallel capacitance C

= 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal).

The actual load capacitance in the application should be C

= 18 pF to account for parasitic capacitances on and

off chip.

Philips Components has developed a special crystal which is tuned to the correct frequency in an application without
series capacitance (code number 9922 520 0038X; see Table 43). This has the advantage that the tuning (catching)
range is increased with approximately 50% without negative effects on spurious responses. When the catching range
of 300 Hz is considered too low this special crystal is a suitable alternative.

The free-running frequency of the oscillator can be checked by opening the colour PLL via the I

C-bus. In that

condition the colour killer is not active so that the frequency off-set is visible on the screen. When two crystals are
connected to the IC the circuit must be forced to one of the crystals during this test to prevent the oscillator switching
continuously between the two frequencies.

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

26. The (R

Y) and (B

Y) signals are demodulated with a phase difference of the reference carrier of 90

and a gain ratio

. The matrixing to the required signals is achieved in the control part.

27. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass

filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.

28. At nominal setting of the gain control. When this amplitude is exceeded the peak-white limiting circuit will reduce the

contrast. The control voltage is generated via the external capacitor connected to the beam-current limiting input.

29. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).

30. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain

(white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a
result the `black-current' of each gun is adapted to the white point setting so that the back-ground colour will follow
the white point adjustment.

Table 42 Output current of the phase detector in the various conditions

C-BUS COMMANDS

IC CONDITIONS

-1 CURRENT/MODE

VID

POC

FOA

FOB

IDENT

COIN

NOISE

SCAN

V-RETR

GATING

MODE

yes

auto

yes

180

270

auto

yes

slow

yes

180

270

slow

yes

180

270

fast

OSD

off

(

)

(

)

---------------------

1.78

Table 43 Code numbers for special crystals

SYSTEM

FREQUENCY

(MHz)

CODE NUMBER

PAL-N

3.582056

9922 520 00381

NTSC-M

3.579545

9922 520 00382

PAL-M

3.575611

9922 520 00383

PAL-B/G

4.433619

9922 520 00384

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

TEST AND APPLICATION INFORMATION

handbook, full pagewidth

MLA746 - 1

BAND

PASS

47 and 46

4.4

MHz

3.6

MHz

TDA4661

28 27

21 22 23 24

RI GI

RGBIN

CHROMA

EXT

CVBS/

TXT

CVBS

IFDEM2

IFDEM1

HOUT

FBI

BCLIN

BLKIN

EWD

VDR

SEC

RYO

BYO

BYI

SCO

RYI

TDA8395

to text decoder

STEREO AND CONTROL

BAND

PASS

SCL

SDA

CVBS/Y

SOUND

TRAP

QSS IF

SAW

FILTER

from

tuner

TDA8366

ref

(neg)

(pos)

Fig.13 Application diagram.

East-West output stage

In order to obtain correct tracking of the vertical and
horizontal EHT-correction, the EW output stage should be
dimensioned as illustrated in Fig.14.

Resistor R

determines the gain of the EW output stage.

Resistor R

determines the reference current for both the

vertical sawtooth generator and the geometry processor.

The preferred value of R

is 39 k

which results in a

reference current of 100

A (V

ref

= 3.9 V).

The value of R

must be:

Example: With V

ref

= 3.9 V; R

= 39 k

and V

scan

= 120 V

then R

= 68 k

scan

ref

-----------------------

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

Adjustment of geometry control parameters

The deflection processor of the TDA8366 offers nine
control parameters for picture alignment:

Vertical picture alignment

S-correction

vertical amplitude

vertical slope

vertical shift

Horizontal picture alignment

horizontal shift

EW width

EW parabola/width

EW corner/parabola

EW trapezium correction.

It is important to notice that the TDA8366 is designed for
use with a DC-coupled vertical deflection stage. This is the
reason why a vertical linearity alignment is not necessary
(and therefore not available).

For a particular combination of picture tube type, vertical
output stage and EW output stage it is determined which
are the required values for the settings of S-correction, EW
parabola/width ratio and EW corner/parabola ratio. These
parameters can be preset via the I

C-bus, and do not need

any additional adjustment. The rest of the parameters are
preset with the mid-value of their control range (i.e. 1FH),
or with the values obtained by previous TV-set
adjustments.

The vertical shift control is meant for compensation of
off-sets in the external vertical output stage or in the
picture tube. It can be shown that without compensation
these off-sets will result in a certain linearity error,
especially with picture tubes that need large S-correction.
The total linearity error is in first order approximation
proportional to the value of the off-set, and to the square of
the S-correction needed. The necessity to use the vertical
shift alignment depends on the expected off-sets in vertical
output stage and picture tube, on the required value of the
S-correction, and on the demands upon vertical linearity.

For adjustment of the vertical shift and vertical slope
independent of each other, a special service blanking
mode can be entered by setting the SBL bit HIGH. In this
mode the RGB-outputs are blanked during the second half
of the picture. There are 2 different methods for alignment
of the picture in vertical direction. Both methods make use
of the service blanking mode.

The first method is recommended for picture tubes that
have a marking for the middle of the screen. With the
vertical shift control the last line of the visible picture is
positioned exactly in the middle of the screen. After this
adjustment the vertical shift should not be changed. The
top of the picture is placed by adjustment of the vertical
amplitude, and the bottom by adjustment of the vertical
slope.

The second method is recommended for picture tubes that
have no marking for the middle of the screen. For this
method a video signal is required in which the middle of the
picture is indicated (e.g. the white line in the circle test
pattern). With the vertical slope control the beginning of the
blanking is positioned exactly on the middle of the picture.
Then the top and bottom of the picture are placed
symmetrical with respect to the middle of the screen by
adjustment of the vertical amplitude and vertical shift.
After this adjustment the vertical shift has the right setting
and should not be changed.

If the vertical shift alignment is not required VSH should be
set to its mid-value (i.e. VSH = 1F). Then the top of the
picture is placed by adjustment of the vertical amplitude
and the bottom by adjustment of the vertical slope. After
the vertical picture alignment the picture is positioned in
the horizontal direction by adjustment of the EW width and
the horizontal shift. Finally (if necessary) the left- and
right-hand sides of the picture are aligned in parallel by
adjusting the EW trapezium control.

After adjustment of the picture for normal vertical
deflection as described, no additional adjustment is
necessary for the compress and expand mode. If required
a small correction of the picture height can be made by
adjusting the vertical slope. This will not effect the linearity.

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

SOLDERING

Plastic dual in-line packages

Y DIP OR WAVE

The maximum permissible temperature of the solder is
260

C; this temperature must not be in contact with the

joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is
below 300

C, it must not be in contact for more than 10 s;

if between 300 and 400

C, for not more than 5 s.

Plastic quad flat-packs

Y WAVE

During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150

C within 6 s.

Typical dwell time is 4 s at 250

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

Y SOLDER PASTE REFLOW

Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45

EPAIRING SOLDERED JOINTS

(

BY HAND

HELD SOLDERING

IRON OR PULSE

HEATED SOLDER TOOL

)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300

C. When using proper tools, all other pins can be

soldered in one operation within 2 to 5 s at between 270
and 320

C. (Pulse-heated soldering is not recommended

for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

January 1995

Philips Semiconductors

Objective specification

C-bus controlled PAL/NTSC TV

processor

TDA8366

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Philips Semiconductors

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SCD36

All rights are reserved. Reproduction in whole or in part is prohibited without the
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other industrial or intellectual property rights.

Printed in The Netherlands

533061/1500/01/pp48

Date of release: January 1995

Document order number:

9397 745 80011

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8366H

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA8366H