1996 Jan 12

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

FEATURES

2 times 6-bit resolution

Sampling rate up to 40 MHz

High signal-to-noise ratio over a large analog input
frequency range (5.8 effective bits at 10 MHz full-scale
input at f

clk

= 40 MHz

TTL output

Two separated inputs (AC-coupling)

TTL compatible digital inputs

Low-level AC clock input signal allowed

Internal reference voltage regulator
(external reference regulation possible)

Power dissipation only 250 mW (typical)

Low analog input capacitance, no buffer amplifier
required

No sample-and-hold circuit required.

APPLICATIONS

High-speed analog-to-digital conversion for:

DBS (Digital Broadcast Satellite)

QPSK (Quadrature Phase Shift Keying) demodulation

Video.

GENERAL DESCRIPTION

The TDA8705 is a 6-bit high-speed dual analog-to-digital
converter (ADC) for satellite video and other applications.
It converts the two analog input signals into two 6-bit
binary-coded digital words at a maximum sampling rate of
40 MHz. All digital inputs and outputs are TTL compatible,
although a low-level sine wave clock input signal is
allowed.

QUICK REFERENCE DATA

Note

1. Full-scale sine wave (f

= 10 MHz; f

clk

= 40 MHz).

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CCA

analog supply voltage

4.75

5.0

5.25

CCD

digital supply voltage

4.75

5.0

5.25

CCO

output stages supply voltage

4.75

5.0

5.25

CCA

analog supply current

CCD

digital supply current

CCO

output stages supply current

ILE

DC integral linear error

0.25

0.5

LSB

DLE

DC differential linearity error

0.25

0.5

LSB

AILE

AC integral linearity error

note 1

0.5

1.0

LSB

clk(max)

maximum clock frequency

MHz

tot

total power dissipation

250

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA8705T

SO28

plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

1996

Jan

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital

Converter (ADC)

TDA8705

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BLOCK DIAGRAM

handbook, full pagewidth

AGND

DEC

VRTA

VCCA

VCCD

VCCO

16 D1B

D2B

D3B

D4B

D0B

D5B

TTL OUTPUTS

LATCHES

ANALOG -TO-DIGITAL

CONVERTER

MLC113

TDA8705

analog ground

data

outputs

LSB

MSB

24 D1A

D2A

D3A

D4A

D0A

D5A

TTL OUTPUTS

LATCHES

ANALOG -TO-DIGITAL

CONVERTER

data

outputs

LSB

MSB

REGULATOR

CLOCK DRIVER

VRBA

VRMA

VRTB

VRMB

VIA

RINTA

RINTB

VRBB

VIB

DGND

CLK

digital ground

OGND

output ground

reference

voltage TOP

reference

voltage TOP

analog

voltage input

reference

voltage BOTTOM

analog

voltage input

reference

voltage BOTTOM

reference

voltage MIDDLE

reference

voltage MIDDLE

Fig.1 Block diagram.

1996 Jan 12

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

PINNING

SYMBOL

PIN

DESCRIPTION

CLK

clock input

CCD

digital supply voltage (+5 V)

DGND

digital ground

RBA

reference voltage BOTTOM for
ADC A (decoupling)

RTA

reference voltage TOP for ADC A
(decoupling)

analog input voltage for ADC A

AGND

analog ground

CCA

analog supply voltage (+5 V)

RMA

reference voltage MIDDLE for ADC A
(decoupling)

DEC

decoupling input

analog input voltage for ADC B

RTB

reference voltage TOP for ADC B
(decoupling)

RBB

reference voltage BOTTOM for
ADC B (decoupling)

RMB

reference voltage MIDDLE for ADC B
(decoupling)

D0B

data output; bit 0 (LSB), ADC B

D1B

data output; bit 1, ADC B

D2B

data output; bit 2, ADC B

D3B

data output; bit 3, ADC B

D4B

data output; bit 4, ADC B

D5B

data output; bit 5 (MSB), ADC B

CCO

supply voltage for output stages
(+5 V)

OGND

output ground

D0A

data output; bit 0 (LSB), ADC A

D1A

data output; bit 1, ADC A

D2A

data output; bit 2, ADC A

D3A

data output; bit 3, ADC A

D4A

data output; bit 4, ADC A

D5A

data output; bit 5 (MSB), ADC A

Fig.2 Pin configuration.

handbook, halfpage

TDA8705

CLK

DGND

V IA

V CCD

V RBA

V RTA

V RMA

V IB

V RTB

V RBB

V RMB

VCCA

AGND

DEC

D5B

D4B

D3B

D2B

D1B

D0B

D3A

D2A

D1A

D0A

V CCO

OGND

D5A

D4A

MLC114

1996 Jan 12

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

CCA

, V

CCO

and V

CCD

may have any value between

0.3 V and +7.0 V provided the difference

between V

CCA

, V

CCO

and V

CCD

is between

1 V and +1 V.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

CCA

analog supply voltage

note 1

0.3

+7.0

CCD

digital supply voltage

note 1

0.3

+7.0

CCO

output stages supply voltage

note 1

0.3

+7.0

supply voltage differences
between V

CCA

and V

CCD

1.0

+1.0

supply voltage differences
between V

CCO

and V

CCD

1.0

+1.0

supply voltage differences
between V

CCA

and V

CCO

1.0

+1.0

input voltage

referenced to AGND

0.3

+7.0

clk(p-p)

AC input voltage for switching
(peak-to-peak value)

referenced to DGND

CCD

output current

stg

storage temperature

+150

amb

operating ambient temperature

+70

junction temperature

+150

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

K/W

1996 Jan 12

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

CHARACTERISTICS

CCA

= V

to V

= 4.75 to 5.25 V; V

CCD

= V

to V

= 4.75 to 5.25 V; V

CCO

= V

to V

= 4.75 to 5.25 V; AGND, OGND

and DGND shorted together; V

CCA

to V

CCD

0.25 to +0.25 V; V

CCO

to V

CCD

0.25 to +0.25 V;

CCA

to V

CCO

0.25 to +0.25 V; T

amb

= 0 to +70

C; typical values measured at V

CCA

= V

CCD

= V

CCO

= 5 V and

amb

= 25

C; C

= 15 pF; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

CCA

analog supply voltage

4.75

5.0

5.25

CCD

digital supply voltage

4.75

5.0

5.25

CCO

output stages supply voltage

4.75

5.0

5.25

CCA

analog supply current

CCD

digital supply current

CCO

output stages supply current

Inputs

LOCK INPUT

CLK;

REFERENCED TO

DGND; note 1

LOW level input voltage

0.8

HIGH level input voltage

2.0

CCD

LOW level input current

clk

= 0.4 V

HIGH level input current

clk

= 2.7 V

input impedance

clk

= 40 MHz

input capacitance

clk

= 40 MHz

ANALOG INPUT VOLTAGE FOR

AND

REFERENCED TO

AGND

DC parallel input resistance

parallel input capacitance

= 10 MHz

1.5

crosstalk between V

and V

= 10 MHz

Reference voltages for the resistor ladder A and B; see Table 1

reference voltage BOTTOM

1.9

2.0

2.1

reference voltage TOP

2.8

2.9

3.0

diff

differential reference voltage V

0.85

0.90

0.95

ref

reference current

LAD

resistor ladder

450

RLAD

temperature coefficient of the resistor
ladder

3280

ppm

osB

offset voltage BOTTOM

note 2

200

osT

offset voltage TOP

note 2

200

i(p-p)

input voltage amplitude
(peak-to-peak value)

0.45

0.50

0.55

Outputs; A and B

IGITAL OUTPUTS

D0;

REFERENCED TO

DGND

LOW level output voltage

= 1 mA

0.4

HIGH level output voltage

1 mA

2.4

CCD

1996 Jan 12

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

Switching characteristics

LOCK INPUT

CLK; note 1; see Fig.3

clk(max)

maximum clock frequency

MHz

CPH

clock pulse width HIGH

CPL

clock pulse width LOW

Analog signal processing

INEARITY

ILE

DC integral linearity error

0.25

0.5

LSB

DLE

DC differential linearity error

0.25

0.5

LSB

AILE

AC integral linearity error

note 3

0.5

1.0

LSB

OFE

offset error between A and B

= 10 MHz;

clk

= 40 MHz; note 4

LSB

gain error between A and B

= 10 MHz;

clk

= 40 MHz; note 4

LSB

MID

middle scale output code A and B

input voltage floating

ANDWIDTH

; f

clk

= 40 MHz

0.5 dB analog bandwidth

full-scale sine wave;
note 5

MHz

STLH

analog input settling time LOW-to-HIGH

full-scale square wave;
Fig.4; note 6

STHL

analog input settling time HIGH-to-LOW

full-scale square wave;
Fig.4; note 6

ARMONICS

; f

clk

= 40 MH

; see Fig.5

fundamental harmonics (full scale)

= 10 MHz

all

harmonics (full scale);
all components

= 10 MHz

second harmonics

third harmonics

THD

total harmonic distortion

= 10 MHz

IGNAL

NOISE RATIO

; note 7; see Fig.5

S/N

signal-to-noise ratio (full scale)

without harmonics;
f

clk

= 40 MHz;

= 10 MHz

FFECTIVE BITS

; note 7; see Figs 5 and 6

effective bits

clk

= 40 MHz

= 10 MHz

5.8

bits

= 20 MHz

5.6

bits

TONE

; note 8

TTIR

two-tone intermodulation rejection

clk

= 40 MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Jan 12

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must not be less than 1 ns.

2. Analog input voltages producing code 00 up to and including 3F:

a) V

osB

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

the reference voltage BOTTOM (V

) at T

amb

= 25

b) V

osT

(voltage offset TOP) is the difference between V

(reference voltage TOP) and the analog input which

produces data outputs equal to 3F at T

amb

= 25

3. Full-scale sine wave (f

= 10 MHz; f

clk

= 40 MHz).

4. The Offset Error (OFE) and Gain Error (GE) are determined by taking results from a simultaneous acquisition on both

ADCs of a sine wave greater than full-scale. The occurrences of code 0 and 63 are used to calculate the OFE
(mid-scale-to-mid-scale) and the GE (amplitude difference) between the two converters A and B.

5. The

0.5 dB analog bandwidth is determined by the 0.5 dB reduction in the reconstructed output, the input being a

full-scale sine wave. It is determined with a beat frequency method; no glitches occurrence.

6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square-wave signal) in order to sample the signal and obtain correct output data.

7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB

6.02 + 1.76 dB.

8. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.1 MHz. The two

input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.

9. Output data acquisition: the output data is available after the maximum delay time of t

IT ERROR RATE

BER

bit error rate

clk

= 40 MHz;

= 10 MHz;

16 LSB at code 32

times/
samples

Timing; f

clk

= 40 MHz; C

= 15 pF; note 9; see Fig.3

sampling delay time

output hold time

output delay time

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Jan 12

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

APPLICATION INFORMATION

Fig.7 Application diagram.

The analog and digital supplies should be separated and decoupled.

RT(n)

, V

RM(n)

and V

RB(n)

and DEC inputs are decoupled to AGND.

(1) In the event of AC-coupling, C

and C

values are chosen in accordance with the classical low frequencies cut-off formulae

where input resistance R

is the value measured under DC conditions.

In the event of DC-coupling, C

and C

capacitors are omitted. The DC biassing and AC modulation signal directly applied to inputs (pin 6 and 11),

must be in the range of V

RT(n)

RB(n)

(2) When pin 10 (DEC) is short-circuited to AGND, an external regulator can be connected to V

RT(n)

and V

RB(n)

--------------------------------------

handbook, full pagewidth

MLC117

5 V

CLK

V CCD

DGND

V IA

V RBA

V RTA

V RMA

V IB

V RTB

V RBB

V RMB

VCCA

AGND

DEC

D5B

D4B

D3B

D2B

D1B

D0B

D3A

D2A

D1A

D0A

V CCO

OGND

D5A

D4A

5 V

input A

input B

TDA8705

100 nF

100 nF
100 nF

1 nF

100 nF

(2)

(1)

1996 Jan 12

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

PACKAGE OUTLINE

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

2.65

0.30
0.10

2.45
2.25

0.49
0.36

0.32
0.23

18.1
17.7

7.6
7.4

1.27

10.65
10.00

1.1
1.0

0.9
0.4

8
0

0.25

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1
0.4

SOT136-1

detail X

(A )

0.25

075E06

MS-013AE

pin 1 index

0.10

0.012
0.004

0.096
0.089

0.019
0.014

0.013
0.009

0.71
0.69

0.30
0.29

0.050

1.4

0.055

0.419
0.394

0.043
0.039

0.035
0.016

0.01

0.25

0.01

0.004

0.043
0.016

0.01

10 mm

scale

SO28: plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

95-01-24
97-05-22

1996 Jan 12

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

Wave soldering

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow.

The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1996 Jan 12

Philips Semiconductors

Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

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Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,
Bangkok 10260, THAILAND,
Tel. (66) 2 745-4090, Fax. (66) 2 398-0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. (0 212)279 27 70, Fax. (0212)282 67 07

Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165,

252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991

United Kingdom: Philips Semiconductors LTD.,

276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. (0181)730-5000, Fax. (0181)754-8421

United States: 811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. (02)70-4044, Fax. (02)92 0601

Internet: http://www.semiconductors.philips.com/ps/

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. +31-40-2724825

SCDS47

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Printed in The Netherlands

537021/1100/02/pp16

Date of release: 1996 Jan 12

Document order number:

9397 750 00568

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