Document Outline

CONTENTS
1 FEATURES
- 1.1 Demodulator and decoder section
- 1.2 DSP section
- 1.3 Analog audio section
2 GENERAL DESCRIPTION
- 2.1 Supported standards
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 PINNING
6 FUNCTIONAL DESCRIPTION
- 6.1 Demodulator and decoder section
- 6.2 Digital signal processing
- 6.3 Analog audio section
7 LIMITING VALUES
8 THERMAL CHARACTERISTICS
9 CHARACTERISTICS
10 I 2 C-BUS CONTROL
- 10.1 Introduction
- 10.2 Power-up state
- 10.3 Slave receiver mode
  - 10.3.1 AGC GAIN REGISTER
  - 10.3.2 GENERAL CONFIGURATION REGISTER
  - 10.3.3 MONITOR SELECT REGISTER
  - 10.3.4 CARRIER 1 FREQUENCY REGISTER
  - 10.3.5 CARRIER 2 FREQUENCY REGISTER
  - 10.3.6 DEMODULATOR CONFIGURATION REGISTER
  - 10.3.7 FM DE-EMPHASIS REGISTER
  - 10.3.8 FM MATRIX REGISTER
  - 10.3.9 FM CHANNEL 1 LEVEL ADJUST REGISTER
  - 10.3.10 FM CHANNEL 2 LEVEL ADJUST REGISTER
  - 10.3.11 REGISTER 14
  - 10.3.12 REGISTER 15
  - 10.3.13 REGISTER 16
  - 10.3.14 REGISTER 17
  - 10.3.15 AUDIO MUTE CONTROL REGISTER
  - 10.3.16 DAC OUTPUT SELECT REGISTER
  - 10.3.17 SCART 1 OUTPUT SELECT REGISTER
  - 10.3.18 SCART 2 OUTPUT SELECT REGISTER
  - 10.3.19 LINE OUTPUT SELECT REGISTER
  - 10.3.20 ADC OUTPUT SELECT REGISTER
  - 10.3.21 MAIN CHANNEL SELECT REGISTER
  - 10.3.22 AUDIO EFFECTS REGISTER
  - 10.3.23 VOLUME CONTROL REGISTERS (MAIN)
  - 10.3.24 CONTOUR CONTROL REGISTER
  - 10.3.25 BASS CONTROL REGISTER (MAIN)
  - 10.3.26 TREBLE CONTROL REGISTER (MAIN)
  - 10.3.27 AUXILIARY CHANNEL SELECT REGISTER
  - 10.3.28 VOLUME CONTROL REGISTERS (AUXILIARY)
  - 10.3.29 BASS CONTROL REGISTER (AUXILIARY)
  - 10.3.30 TREBLE CONTROL REGISTER (AUXILIARY)
  - 10.3.31 FEATURE INTERFACE CONFIGURATION REGISTER
  - 10.3.32 I 2 S1 OUTPUT SELECT REGISTER
  - 10.3.33 I 2 S1 INPUT LEVEL ADJUST REGISTER
  - 10.3.34 I 2 S1 OUTPUT LEVEL ADJUST REGISTER
  - 10.3.35 I 2 S2 OUTPUT SELECT REGISTER
  - 10.3.36 I 2 S2 INPUT LEVEL ADJUST REGISTER
  - 10.3.37 I 2 S2 OUTPUT LEVEL ADJUST REGISTER
  - 10.3.38 BEEPER FREQUENCY CONTROL REGISTER
  - 10.3.39 BEEPER VOLUME CONTROL REGISTER
  - 10.3.40 BASS BOOST CONTROL REGISTER
- 10.4 Slave transmitter mode
11 I 2 S-BUS DESCRIPTION
12 APPLICATION INFORMATION
13 PACKAGE OUTLINES
- SOT274-1
- SOT393-1
14 SOLDERING
- 14.1 Introduction
- 14.2 Through-hole mount packages
- 14.3 Surface mount packages
- 14.4 Suitability of IC packages for wave, reflow and dipping soldering methods
15 DEFINITIONS
16 LIFE SUPPORT APPLICATIONS
17 PURCHASE OF PHILIPS I 2 C COMPONENTS

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

FEATURES

1.1

Demodulator and decoder section

Sound IF (SIF) input switch e.g. to select between
terrestrial TV SIF and SAT SIF sources

SIF AGC with 24 dB control range

SIF 8-bit Analog-to-Digital Converter (ADC)

Two-carrier multistandard FM demodulation
(B/G, D/K and M standard)

Decoding for three analog multi-channel systems
(A2, A2+ and A2*) and satellite sound

Programmable identification (B/G, D/K and M standard)
and different identification times.

1.2

DSP section

Digital crossbar switch for all digital signal sources and
destinations

Control of volume, balance, contour, bass, treble,
pseudo stereo, spatial, bass boost and soft mute

Plop-free volume control

Automatic Volume Level (AVL) control

Adaptive de-emphasis for satellite

Programmable beeper

Monitor selection for FM/AM DC values and signals,
with peak detection option

S-bus interface for a feature extension (e.g. Dolby

surround) with matrix, level adjust and mute.

1.3

Analog audio section

Analog crossbar switch with inputs for mono and stereo
(also applicable as SCART 3 input), SCART 1
input/output, SCART 2 input/output and line output

User defined full-level/

3 dB scaling for SCART outputs

Output selection of mono, stereo, dual A/B, dual A or
dual B

20 kHz bandwidth for SCART-to-SCART copies

Standby mode with functionality for SCART copies

Dual audio Digital-to-Analog Converter (DAC) from DSP
to analog crossbar switch, bandwidth of 15 kHz

Dual audio ADC from analog inputs to DSP

Two dual audio DACs for loudspeaker (Main) and
headphone (Auxiliary) outputs; also applicable for
L, R, C and S in the Dolby Pro Logic mode with feature
extension.

GENERAL DESCRIPTION

The TDA9870A is a single-chip Digital TV Sound
Processor (DTVSP) for analog multi-channel sound
systems in TV sets and satellite receivers.

2.1

Supported standards

The multistandard/multi-stereo capability of the
TDA9870A is mainly of interest in Europe, but also in
Hong Kong/Peoples Republic of China and South East
Asia. This includes B/G, D/K, I, M and L standard. In other
application areas there exists only subsets of those
standard combinations otherwise only single standards
are transmitted.

M standard is transmitted in Europe by the American
Forces Network (AFN) with European channel spacing
(7 MHz VHF, 8 MHz UHF) and monaural sound.

Korea has a stereo sound system similar to Europe and is
supported by the TDA9870A. Differences include
deviation, modulation contents and identification. It is
based on M standard.

An overview of the supported standards and sound
systems and their key parameters is given in Table 1.

The analog multi-channel sound systems (A2, A2+
and A2*) are 2-Carrier Systems (2CS).

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

2.1.1

NALOG

CARRIER SYSTEMS

Table 1

Frequency modulation

Table 2

Identification for A2 systems

STANDARD

SOUND

SYSTEM

CARRIER

FREQUENCY

(MHz)

FM DEVIATION (kHz)

MODULATION

BANDWIDTH/

DE-EMPHASIS

(kHz/

NOM.

MAX.

OVER

SC1

SC2

mono

4.5

mono

15/75

A2+

4.5/4.724

(L + R)

15/75 (Korea)

B/G

5.5/5.742

(L + R)

15/50

mono

6.0

mono

15/50

D/K

6.5/6.742

(L + R)

15/50

D/K

A2*

6.5/6.258

(L + R)

15/50

PARAMETER

A2/A2*

A2+ (KOREA)

Pilot frequency

54.6875 kHz = 3.5

line frequency

55.0699 kHz = 3.5

line frequency

Stereo identification
frequency

Dual identification
frequency

AM modulation depth

50%

117.5 Hz

line frequency

133

-------------------------------------

149.9 Hz

line frequency

105

-------------------------------------

274.1 Hz

line frequency

-------------------------------------

276.0 Hz

line frequency

-------------------------------------

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

2.1.2

ATELLITE SYSTEMS

An important specification for satellite TV reception is the

"Astra specification". The TDA9870A is suited for the reception

of Astra and other satellite signals.

Table 3

FM satellite sound

Notes

1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received.

2. A de-emphasis of 60

s, or in accordance with J17, is available.

3. m/st/d = mono, stereo or dual language sound.

4. Adaptive de-emphasis is compatible to transmitter specification.

ORDERING INFORMATION

CARRIER TYPE

CARRIER

FREQUENCY

(MHz)

MODULATION

INDEX

MAXIMUM

FM DEVIATION

(kHz)

MODULATION

BANDWIDTH/

DE-EMPHASIS

(kHz/

Main

6.50

(1)

0.26

mono

15/50

(2)

Sub

7.02/7.20

0.15

m/st/d

(3)

15/adaptive

(4)

Sub

7.38/7.56

Sub

7.74/7.92

Sub

8.10/8.28

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA9870A

SDIP64

plastic shrink dual in-line package; 64 leads (750 mil)

SOT274-1

TDA9870AH

QFP64

plastic quad flat package; 64 leads (lead length 1.6 mm);
body 14

2.7 mm

SOT393-1

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

BLOCK DIAGRAM

handbook, full pagewidth

MHB593

C-BUS

INTERFACE

INPUT SWITCH

AGC, ADC

FM (AM)

DEMODULATION

SUPPLY

SOUND IF

(SIF)

IDENTIFICATION

A2/SATELLITE

DECODER

AUDIO PROCESSING

SUPPLY

SCART,

DAC,

ADC

LEVEL

ADJUST

PEAK

DETECTION

ADC (2)

DAC (2)

TEST

TDA9870A

(TDA9870AH)

MOL

DAC (2)

ANALOG

CROSSBAR

SWITCH

CLOCK

SIF2

SIF1

9 (1)

20 (12)

10 (2)

12 (4)

3 (59)

13 (5)

4 (60)

5 (61)

ADDR1

ADDR2

18 (10)

XTALI

19 (11)

XTALO

21 (13)

SYSCLK

SCL

SDA

S-BUS

INTERFACE

27 (19)

26 (18)

25 (17)

24 (16)

22 (14)

23 (15)

SDI1

SDI2

SDO1

SDO2

SCK

DIGITAL
SUPPLY

DIGITAL

SELECT

15 (7)

64 (56)

35 (27)

17 (9)

16 (8)

VDDD1
VDDD2

VSSD3
VSSD4

CRESET

14 (6)

49 (41)

VSSD1
VSSD2

28 (20)

Vref3

Vref(n)

Vref(p)

VDEC2

VDDA

PCAPL

PCAPR

30 (22)

(51) 59

(30) 38

(46) 54

i.c.

(58) 2

i.c.

(57) 1

LOL

LOR

SCOL2

SCOR2

SCOL1

SCOR1

(44) 52

(43) 51

(54) 62

(55) 63

(40) 48

(39) 47

Iref

(64) 8

Vref1

(3) 11

VSSA1

(62) 6

VDEC1

(63) 7

MONOIN

EXTIL

EXTIR

SCIL2

SCIR2

SCIL1

(23) 31

(29) 37

(21) 29

(24) 32

(28) 36

(26) 34

SCIR1

(25) 33

(47) 55

(31) 39

(32) 40

(53)
61

MOR

(52)
60

AUXOL

(50)
58

AUXOR

(49)
57

TEST2

TEST1

i.c.

(34) 42

i.c.

(33) 41

i.c.

(36) 44

i.c.

(37) 45

VSSA3

VSSA2

Vref2

(38) 46

(45) 53

(35) 43

(48) 56

VSSA4

(42) 50

Fig.1 Block diagram.

The pin numbers given in parenthesis refer to the TDA9870AH version.

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

PINNING

SYMBOL

PIN

TYPE

(1)

DESCRIPTION

TDA9870A

TDA9870AH

i.c.

internally connected; note 2

i.c.

internally connected; note 2

ADDR1

C-bus slave address input 1

SCL

C-bus clock input

SDA

I/O

C-bus data input/output

SSA1

supply ground 1; analog front-end circuitry

DEC1

supply voltage decoupling 1; analog front-end circuitry

ref

resistor for reference current generator; analog front-end circuitry

I/O

general purpose input/output pin 1

SIF2

sound IF input 2

ref1

reference voltage 1; analog front-end circuitry

SIF1

sound IF input 1

ADDR2

C-bus slave address input 2

SSD1

supply ground 1; digital circuitry

DDD1

digital supply voltage 1; digital circuitry

CRESET

capacitor for Power-on reset

SSD4

supply ground 4; digital circuitry

XTALI

crystal oscillator input

XTALO

crystal oscillator output

I/O

general purpose input/output pin 2

SYSCLK

system clock output

SCK

I/O

S-bus clock input/output

I/O

S-bus word select input/output

SDO2

S-bus data output 2 (I

S2 output)

SDO1

S-bus data output 1 (I

S1 output)

SDI2

S-bus data input 2 (I

S2 input)

SDI1

S-bus data input 1 (I

S1 input)

TEST1

test pin 1; connected to V

SSD1

for normal operation

MONOIN

audio mono input

TEST2

test pin 2; connected to V

SSD1

for normal operation

EXTIR

external audio input right channel

EXTIL

external audio input left channel

SCIR1

SCART 1 input right channel

SCIL1

SCART 1 input left channel

SSD3

supply ground 3; digital circuitry

SCIR2

SCART 2 input right channel

SCIL2

SCART 2 input left channel

DEC2

supply voltage decoupling 2; audio analog-to-digital converter
circuitry

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Notes

1. Pin type: I = Input; O = Output; S = Supply.

2. Test pin: CMOS 3-state stage, pull-up resistor, can be connected to V

3. Test pin: CMOS level input, pull-up resistor, can be connected to V

4. Test pin: CMOS 3-state stage, can be connected to V

ref(p)

positive reference voltage; audio analog-to-digital converter
circuitry

ref(n)

reference voltage ground; audio analog-to-digital converter
circuitry

i.c.

internally connected; note 3

i.c.

internally connected; note 4

SSA2

supply ground 2; audio analog-to-digital converter circuitry

i.c.

internally connected; note 4

i.c.

internally connected; note 3

ref2

reference voltage 2; audio analog-to-digital converter circuitry

SCOR1

SCART 1 right channel output

SCOL1

SCART 1 left channel output

SSD2

supply ground 2; digital circuitry

SSA4

supply ground 4; audio operational amplifier circuitry

SCOR2

SCART 2 right channel output

SCOL2

SCART 2 left channel output

ref3

reference voltage 3; audio digital-to-analog converter and
operational amplifier circuitry

PCAPR

post-filter capacitor pin right channel, audio digital-to-analog
converter

PCAPL

post-filter capacitor pin left channel, audio digital-to-analog
converter

SSA3

supply ground 3; audio digital-to-analog converter circuitry

AUXOR

headphone (Auxiliary) right channel output

AUXOL

headphone (Auxiliary) left channel output

DDA

analog power supply voltage; analog circuitry

MOR

loudspeaker (Main) right channel output

MOL

loudspeaker (Main) left channel output

LOL

line output left channel

LOR

line output right channel

DDD2

digital supply voltage 2; digital circuitry

SYMBOL

PIN

TYPE

(1)

DESCRIPTION

TDA9870A

TDA9870AH

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

FUNCTIONAL DESCRIPTION

6.1

Demodulator and decoder section

6.1.1

SIF

INPUT

Two input pins are provided: SIF1 e.g. for terrestrial TV
and SIF2 e.g. for a satellite tuner. For higher SIF signal
levels the SIF input can be attenuated with an internally
switchable

10 dB resistor divider. As no specific filters are

integrated, both inputs have the same specification giving
flexibility in application. The selected signal is passed
through an AGC circuit and then digitized by an 8-bit ADC
operating at 24.576 MHz.

6.1.2

AGC

The gain of the AGC amplifier is controlled from the ADC
output by means of a digital control loop employing
hysteresis. The AGC has a fast attack behaviour to
prevent ADC overloads and a slow decay behaviour to
prevent AGC oscillations. For AM demodulation the AGC
must be switched off. When switched off, the control loop
is reset and fixed gain settings can be chosen
(see Table 14; subaddress 0).

The AGC can be controlled via the I

C-bus. Details can be

found in the I

C-bus register definitions (see Chapter 10).

6.1.3

IXER

The digitized input signal is fed to the mixers, which mix
one or both input sound carriers down to zero IF. A 24-bit
control word for each carrier sets the required frequency.
Access to the mixer control word registers is via the
I

C-bus.

6.1.4

AND

DEMODULATION

An FM or AM input signal is fed via a band-limiting filter to
a demodulator that can be used for either FM or AM
demodulation. Apart from the standard (fixed)
de-emphasis characteristic, an adaptive de-emphasis is
available for encoded satellite programs. A stereo decoder
recovers the left and right signal channels from the
demodulated sound carriers. Both the European and
Korean stereo systems are supported.

6.1.5

IDENTIFICATION

The identification of the FM sound mode is performed by
AM synchronous demodulation of the pilot signal and
narrow-band detection of the identification frequencies.
The result is available via the I

C-bus interface. A selection

can be made via the I

C-bus for B/G, D/K and M standard

and for three different modes that represent different
trade-offs between speed and reliability of identification.

6.1.6

RYSTAL OSCILLATOR

The circuitry of the crystal oscillator is fully integrated, only
the external 24.576 MHz crystal is needed (see Fig.10).

6.1.7

EST PINS

Test pins TEST1 and TEST2 are active HIGH and in
normal operating mode of the device they are connected
to V

SSD1

. Test functions are for manufacturing tests only

and are not available to customers. Without external
circuitry these pins are pulled down to LOW level with
internal resistors.

6.1.8

OWER FAIL DETECTOR

The power fail detector monitors the internal power supply
for the digital part of the device. If the supply has
temporarily been lower than the specified lower limit, the
Power-on reset bit POR (see Section 10.4.1), will be set to
logic 1. Bit CLRPOR (see Section 10.3.2) resets the
Power-on reset flip-flop to LOW. If this is detected, an
initialization of the TDA9870A has to be carried out to
ensure reliable operation.

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

6.1.9

OWER

ON RESET

The reset is active LOW. In order to perform a reset at
power-up, a simple RC circuit may be used which consists
of the integrated passive pull-up resistor and an external
capacitor connected to ground. The pull-up resistor has a
nominal value of 50 k

, which can easily be measured

between pins CRESET and V

DDD2

. Before the supply

voltage has reached a certain minimum, the state of the
circuit is completely undefined, and it remains in this
undefined state unless a reset is applied.

The reset is guaranteed to be active when:

The power supply is within the specified limits
(4.75 and 5.5 V)

The crystal oscillator is functioning

The voltage at pin CRESET is below 0.3V

DDD

(1.5 V if

DDD

= 5.0 V, typically below 1.8 V).

The required capacitor value depends on the gradient of
the rising power supply voltage. The time constant of the
RC circuit should be clearly larger than the rise time of the
power supply, to make sure that the reset condition is
always satisfied (see Fig.4), even considering the
tolerance spread. To avoid problems with a too slow
discharging of the capacitor at power-down, it may be
helpful to add a diode from pin CRESET to V

DDD

. It should

be noted that the internal ESD protection diode does not
help here as it only conducts at higher voltages. Under
difficult power supply conditions (e.g. very slow or
non-monotonic ramp-up), it is recommended to drive the
reset line from a microcontroller port or the like.

handbook, halfpage

MHB595

reset active
guaranteed

1.5

voltage

(V)

VCRESET

0.3VDDD

VDDD

4.75 V

Fig.4 Reset at power-on.

1999

Dec

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TD
A9870A

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

6.2

Digital signal pr

ocessing

ha
ndbook, full pagewidth

MHB112

from ADC

LEVEL ADJUST

DIGITAL

CROSSBAR

SELECT

LEVEL ADJUST

LEVEL ADJUST AND MUTE

LEVEL ADJUST

FILTER

MONITOR

SELECT

PEAK

DETECTION

MATRIX

FIXED

DE-EMPHASIS

MATRIX

VOLUME

SOFT-MUTE

BASS/TREBLE

BEEPER

Main

Auxiliary

DAC

C-bus

MATRIX

AUTOMATIC

VOLUME

LEVEL

SPATIAL

PSEUDO
VOLUME

BASS/TREBLE

BASS BOOST

CONTOUR

SOFT-MUTE

BEEPER

ADAPTIVE

DE-EMPHASIS

FILTER

Fig.5 DSP data flow diagram.

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

6.2.1

EVEL SCALING

All input channels to the digital crossbar switch (except for
the loudspeaker feedback path) are equipped with a level
adjust facility to change the signal level in a range from

15 to

15 dB (see Fig.5). It is recommended to scale all

input channels to be 15 dB below full-scale (

15 dB

full-scale) under nominal conditions.

6.2.2

FM (AM)

PATH

A high-pass filter suppresses DC offsets from the
FM demodulator, due to carrier frequency offsets, and
supplies the monitor/peak function with DC values and an
unfiltered signal, e.g. for the purpose of carrier detection.

The de-emphasis function offers fixed settings for the
supported standards (50, 60 and 75

s).

An adaptive de-emphasis is available for
Wegener-Panda 1 encoded programs.

A matrix performs the dematrixing of the A2 stereo, dual
and mono signals.

6.2.3

ONITOR

This function provides data words from a number of
locations of the signal processing paths to the I

C-bus

interface (2 data bytes). Signal sources include the
FM demodulator outputs, most inputs to the digital
crossbar switch and the outputs of the ADC. Source
selection and data read-out is performed via the I

C-bus.

Optionally, the peak value can be measured instead of
simply taking samples. The internally stored peak value is
reset to zero when the data is read via the I

C-bus.

The monitor function may be used, for example, for signal
level measurements or carrier detection.

6.2.4

OUDSPEAKER

AIN

)

CHANNEL

The matrix provides the following functions: forced mono,
stereo, channel swap, channel 1, channel 2 and spatial
effects.

There are fixed coefficient sets for spatial settings of 30%,
40% and 52%.

The Automatic Volume Level (AVL) function provides a
constant output level of

23 dB full-scale for input levels

between 0 and

29 dB full-scale. There are some fixed

decay time constants to choose from, i.e. 2, 4 and 8 s.

Pseudo stereo is based on a phase shift in one channel via
a second-order all-pass filter. There are fixed coefficient
sets to provide 90 degrees phase shift at frequencies of
150, 200 and 300 Hz.

Volume is controlled individually for each channel ranging
from +24 to

83 dB with 1 dB resolution. There is also a

mute position. For the purpose of a simple control software
in the microcontroller, the decimal number that is sent as
an I

C-bus data byte for volume control is identical to the

volume setting in dBs (e.g. the I

C-bus data byte +10 sets

the new volume value to +10 dB).

Balance can be realized by independent control of the left
and right channel volume settings.

Contour is adjustable between 0 and +18 dB with 1 dB
resolution. This function is linked to the volume setting by
means of microcontroller software.

Bass is adjustable between +15 and

12 dB with 1 dB

resolution and treble is adjustable between
+12 and

12 dB with 1 dB resolution.

For the purpose of a simple control software in the
microcontroller, the decimal number that is sent as an
I

C-bus data byte for contour, bass or treble is identical to

the new contour, bass or treble setting in dBs (e.g. the
I

C-bus data byte +8 sets the new value to +8 dB).

Extra bass boost is provided up to 20 dB with 2 dB
resolution. The implemented coefficient set serves merely
as an example on how to use this filter.

The beeper provides tones in a range from approximately
400 Hz to 30 kHz. The frequency can be selected via the
I

C-bus. The beeper output signal is added to the

loudspeaker and headphone channel signals. The beeper
volume is adjustable with respect to full-scale between
0 and

93 dB with 3 dB resolution. The beeper is not

effected by mute.

Soft mute provides a mute ability in addition to volume
control with a well defined time (32 ms) after which the soft
mute is completed. A smooth fading is achieved by a
cosine masking.

6.2.5

EADPHONE

UXILIARY

)

CHANNEL

The matrix provides the following functions: forced mono,
stereo, channel swap, channel 1 and channel 2
(or C and S in Dolby Surround Pro Logic mode).

Volume is controlled individually for each channel in a
range from +24 to

83 dB with 1 dB resolution. There is

also a mute position.

For the purpose of a simple control software in the
microcontroller, the decimal number that is sent as an
I

C-bus data byte for volume control is identical to the

volume setting in dB (e.g. the I

C-bus data byte +10 sets

the new volume value to +10 dB).

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Balance can be realized by independent control of the left
and right channel volume settings.

Bass is adjustable between +15 and

12 dB with 1 dB

resolution and treble is adjustable between
+12 and

12 dB with 1 dB resolution.

For the purpose of a simple control software in the
microcontroller, the decimal number that is sent as an
I

C-bus data byte for bass or treble is identical to the new

bass or treble setting in dB (e.g. the I

C-bus data byte +8

sets the new value to +8 dB).

The beeper provides tones in a range from approximately
400 Hz to 30 kHz. The frequency can be selected via the
I

C-bus. The beeper output signal is added to the

loudspeaker and headphone channel signals. The beeper
volume is adjustable with respect to full-scale between
0 and

93 dB with 3 dB resolution. The beeper is not

effected by mute.

Soft mute provides a mute ability in addition to volume
control with a well defined time (32 ms) after which the soft
mute is completed. A smooth fading is achieved by a
cosine masking.

6.2.6

EATURE INTERFACE

The feature interface comprises two I

S-bus input/output

ports and a system clock output. Each I

S-bus port is

equipped with level adjust facilities that can change the
signal level in a range from +15 to

15 dB with 1 dB

resolution. Outputs can be disabled to improve EMC
performance.

The I

S-bus output matrix provides the following functions:

forced mono, stereo, channel swap, channel 1 and
channel 2.

One example of how the feature interface can be used in
a TV set is to connect an external Dolby Surround Pro
Logic DSP, such as the SAA7710, to the I

S-bus ports.

Outputs must be enabled and a suitable master clock
signal for the DSP can be taken from pin SYSCLK.
A stereo signal from any source will be output on one of
the I

S-bus serial data outputs and the four processed

signal channels will be entered at both I

S-bus serial data

inputs. Left and right could then be output to the power
amplifiers via the Main channel, centre and surround via
the Auxiliary channel.

6.2.7

HANNEL FROM THE AUDIO

ADC

The signal level at the output of the ADC can be adjusted
in a range from +15 to

15 dB with 1 dB resolution.

The audio ADC itself is scaled to a gain of

6 dB.

6.2.8

HANNEL TO THE ANALOG CROSSBAR PATH

Level adjust with control positions 0, +3, +6 and +9 dB.

6.2.9

IGITAL CROSSBAR SWITCH

Input channels to the crossbar switch are from the audio
ADC, I

S1, I

S2, FM path and from the loudspeaker

channel path after matrix and AVL (see Fig.6).

Output channels comprise loudspeaker, headphone, I

S1,

S2 and the audio DACs for line output and SCART.

The I

S1 and I

S2 outputs also provide digital outputs from

the loudspeaker and headphone channels, but without the
beeper signals.

6.2.10

IGNAL GAIN

There are a number of functions that can provide signal
gain, e.g. volume, bass and treble control. Great care has
to be taken when using gain with large input signals in
order not to exceed the maximum possible signal swing,
which would cause severe signal distortion. The nominal
signal level of the various signal sources to the digital
crossbar switch should be 15 dB below digital full-scale
(

15 dB full-scale). This means that a volume setting of,

say, +15 dB would just produce a full-scale output signal
and not cause clipping, if the signal level is nominal.

Sending illegal data patterns via the I

C-bus will not cause

any changes of the current setting for the volume, bass,
treble, bass boost and level adjust functions.

6.2.11

XPERT MODE

The TDA9870A provides a special expert mode that gives
direct write access to the internal Coefficient RAM (CRAM)
of the DSP. It can be used to create user-defined
characteristics, such as a tone control with different corner
frequencies or special boost/cut characteristics to correct
the low-frequency loudspeaker and/or cabinet frequency
responses by means of the bass boost filter. However, this
mode must be used with great care.

More information on the functions of this device, such as
the number of coefficients per function, their default
values, memory addresses etc., can be made available on
request.

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

6.2.12

DSP

FUNCTIONS

Table 4

Overview of DSP functions

FUNCTION

EXPERT

MODE

PARAMETER

VALUE

UNIT

Bass control for loudspeaker and
headphone output

yes

control range

12 to +15

resolution

resolution at frequency

Treble control for loudspeaker and
headphone output

yes

control range

12 to +12

resolution

resolution at frequency

kHz

Contour for loudspeaker output

yes

control range

0 to +18

resolution

resolution at frequency

Bass boost for loudspeaker output

yes

control range

0 to +20

resolution

resolution at frequency

corner frequency

350

Volume control for each separate
channel in loudspeaker and
headphone output

control range

83 to +24

resolution

mute position at step

10101100

Soft mute for loudspeaker and
headphone output

processing time

Spatial effects

yes

anti-phase crosstalk positions

30, 40 and 52

Pseudo stereo

yes

90 degrees phase shift at frequency

150, 200 and 300

Beeper additional to the signal in the
loudspeaker and headphone channel

yes

beep frequencies

see Section 10.3.38

control range

0 to

resolution

mute position at step

00100000

Automatic Volume Level (AVL)

yes

step width

quasi continuously

AVL output level for an input level
between 0 and

29 dB full-scale

attack time

decay time constant

2, 4 and 8

General

3 dB lower corner frequency of DSP 10

1 dB bandwidth of DSP

14.5

kHz

Level adjust I

S1 and I

S2 inputs

yes

control range

15 to +15

resolution

Level adjust I

S1 and I

S2 outputs

yes

control range

15 to +15

resolution

mute position at step

00010000

Level adjust analog crossbar path

control positions

0, 3, 6 and 9

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

6.3.1

NALOG CROSSBAR SWITCH AND ANALOG MATRIX

There are a number of analog input and output ports with
the TDA9870A (see Figs 6 and 8). Analog source selector
switches are employed to provide the desired analog
signal routing capability. The analog signal routing is
performed by the analog crossbar switch section. A dual
audio ADC provides the connection to the DSP section
and a dual audio DAC provides the connection from the
DSP section to the analog crossbar switch. The digital
signal routing is performed by a digital crossbar switch.

The basic signal routing philosophy of the TDA9870A is
that each switch handles two signal channels at the same
time, e.g. left and right, language A and B, directly at the
source.

Each source selector switch is followed by an analog
matrix to perform further selection tasks, such as putting a
signal from one input channel, say language A, to both
output channels or for swapping left and right channels
(see Fig.7).

The analog matrix provides the functions given in Table 5.

Table 5

Analog matrix functions

All switches and matrices are controlled via the I

C-bus.

6.3.2

SCART

INPUTS

The SCART specification allows for a signal level of up to
2 V (RMS). Because of signal handling limitations, due to
the 5 V supply voltage of the TDA9870A, it is necessary to
have fixed 3 dB attenuators at the SCART inputs to obtain
a 2 V input. This results in a

3 dB SCART-to-SCART

copy gain. If 0 dB copy gain is preferred (with maximum
1.4 V input), there are 3 and 0 dB amplifiers at the outputs
of SCART 1 and SCART 2 and at the line output.

The input attenuator is realized by an external series
resistor in combination with the input impedance, both of
which form a voltage divider. With this voltage divider the
maximum SCART signal level of 2 V (RMS) is scaled
down to 1.4 V (RMS) at the input pin.

6.3.3

XTERNAL AND MONO INPUTS

The 3 dB input attenuators are not required for the external
and mono inputs, because those signal levels are under
control of the TV designer. The maximum allowed input
level is 1.4 V (RMS). By adding external series resistors,
the external inputs can be used as an additional SCART
input.

6.3.4

SCART

OUTPUTS

The SCART outputs employ amplifiers with two gain
settings. The gain can be set to 3 or 0 dB via the I

C-bus.

The 3 dB position is needed to compensate for the 3 dB
attenuation at the SCART inputs should
SCART-to-SCART copies with 0 dB gain be preferred
[under the condition of 1.4 V (RMS) maximum input level].
The 0 dB position is needed, for example, for an
external-to-SCART copy with 0 dB gain.

MODE

MATRIX OUTPUT

LEFT OUTPUT

RIGHT OUTPUT

left input

right input

left input

right input

handbook, halfpage

MGK110

ANALOG

MATRIX

left input

right input

left output

right output

Fig.7 Analog matrix.

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

6.3.5

INE OUTPUT

The line output can provide an unprocessed copy of the
audio signal in the loudspeaker channels. This can be
either an external signal that comes from the dual audio
ADC, or a signal from an internal digital audio source that
comes from the dual audio DAC. The line output employs
amplifiers with two gain settings. The 3 dB position is
needed to compensate for the attenuation at the SCART
inputs, while the 0 dB position is needed, for example, for
non-attenuated external or internal digital signals
(see Section 6.3.4).

6.3.6

OUDSPEAKER

AIN

)

AND HEADPHONE

UXILIARY

)

OUTPUTS

Signals from any audio source can be applied to the
loudspeaker and to the headphone output channels via the
digital crossbar switch and the DSP.

6.3.7

UAL AUDIO

DAC

The TDA9870A contains three dual audio DACs, one for
the connection from the DSP to the analog crossbar switch
section and two for the loudspeaker and headphone
outputs. Each of the three dual low-noise high-dynamic
range DACs consists of two 15-bit DACs with current
outputs, followed by a buffer operational amplifier.
The audio DACs operate with four-fold oversampling and
noise shaping.

6.3.8

UAL AUDIO

ADC

There is one dual audio ADC in the TDA9870A for the
connection of the analog crossbar switch section to the
DSP. The dual audio ADC consists of two bitstream
3rd-order sigma-delta audio ADCs and a high-order
decimation filter.

6.3.9

TANDBY MODE

The standby mode, selected by setting bit STDBY to
logic 1 (see Section 10.3.2) disables most functions and
reduces power dissipation. The analog crossbar switch
and the SCART section remain operational and can be
controlled by the I

C-bus to support copying of analog

signals from SCART-to-SCART.

Unused internal registers may lose their information in the
standby mode. Therefore, the device needs to be
initialized on returning to the normal operating mode. This
can be accomplished in the same way as after a Power-on
reset.

6.3.10

UPPLY GROUND

The different supply grounds V

are internally connected

via the substrate. It is recommended to connect all ground
pins by a copper plane close to the pins.

1999

Dec

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TD
A9870A

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

ndbook, full pagewidth

MHB114

SCART 1

SCART 2

FM/AM

part

external

ADC

6 dB

mono

LEVEL

ADJUST

ADC

LEVEL

ADJUST

DAC

OUTPUT

LEVEL

ADJUST

DAC

GAIN

DAC

Main

Auxiliary

Line

SCART 1

SCART 2

DAC

DIGITAL

MATRIX

DIGITAL

MATRIX

BUFFER

3 dB

BUFFER

3 dB

BUFFER

3 dB

ANALOG

MATRIX

ANALOG

MATRIX

ANALOG

MATRIX

OUTPUT

LEVEL

ADJUST

DIGITAL

MATRIX

DIGITAL

MATRIX

DIGITAL

MATRIX

AUTOMATIC

VOLUME

LEVEL

LOUDSPEAKER

CHANNEL

PROCESSING

HEADPHONE

CHANNEL

PROCESSING

STEREO

DECODER

FIXED

DE-EMPHASIS

ADAPTIVE

DE-EMPHASIS

FM/AM

DEMODULATOR

INPUT

LEVEL

ADJUST

INPUT

LEVEL

ADJUST

Fig.8 Audio signal flow diagram.

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

CHARACTERISTICS

SIF(p-p)

= 300 mV; AGCOFF = 0; AGCSLOW = 0; AGCLEV = 0; level and gain settings in accordance with note 1;

= 5 V; T

amb

= 25

C; settings in accordance with B/G standard; FM deviation

50 kHz; f

mod

= 1 kHz; FM sound

parameters in accordance with system A2; 1 k

measurement source resistance for AF inputs; with external

components of Fig.10; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

DDD1

digital supply voltage 1

4.75

5.0

5.5

SSD1

digital supply ground 1

note 2

0.0

DDD1

digital supply current 1

DDD1

= 5.0 V

DDD2

digital supply voltage 2

4.75

5.0

5.5

SSD2

digital supply ground 2

note 2

0.0

DDD2

digital supply current 2

DDD2

= 5.0 V; system clock

output disabled

0.1

0.4

SSD3

digital supply ground 3

note 2

0.0

SSD4

digital supply ground 4

note 2

0.0

DDA

analog supply voltage

4.75

5.0

5.5

DDA

analog supply current for
DAC part

DDA

= 5.0 V; digital silence

SSA1

analog ground for analog
front-end

note 2

0.0

SSA2

analog ground for audio ADC
part

note 2

0.0

SSA3

analog ground for audio DAC
part

note 2

0.0

SSA4

analog ground for SCART

0.0

Demodulator supply decoupling and references

DEC1

analog supply decoupling
voltage for demodulator part

3.0

3.3

3.6

ref1

analog reference voltage for
demodulator part

ref1(sink)

sink current at pin V

ref1

200

Audio supply decoupling and references

DEC2

analog supply decoupling
voltage for audio ADC part

3.0

3.3

3.6

ref2

reference voltage ratio for
audio ADCs

referenced to V

DEC2

and

SSA2

Vref2-VDEC2

impedance pins V

ref2

to V

DEC2

Vref2-VSSA2

impedance pins V

ref2

to V

SSA2

ref3

reference voltage ratio for
audio DAC and operational
amplifier

referenced to V

DDA

and

SSA3

Vref3-VDDA

impedance pins V

ref3

to V

DDA

Vref3-VSSA3

impedance pins V

ref3

to V

SSA3

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Power fail detector

th(pf)

power fail threshold voltage

3.9

Digital inputs and outputs

NPUTS

CMOS level input, pull-down (pins TEST1 and TEST2)

LOW-level input voltage

0.3V

DDD

HIGH-level input voltage

0.7V

DDD

input capacitance

input impedance

CMOS level input, hysteresis, pull-up (pin CRESET)

LOW-level input voltage

0.3V

DDD

HIGH-level input voltage

0.7V

DDD

hys

hysteresis voltage

1.3

input capacitance

input impedance

NPUTS

OUTPUTS

C-bus level input with Schmitt trigger, open-drain output stage, 400 kHz I

C-bus operation (pins SCL and SDA)

LOW-level input voltage

0.3V

DDD

HIGH-level input voltage

0.7V

DDD

hys

hysteresis voltage

0.05V

DDD

input leakage current

input capacitance

LOW-level output voltage

0.6

load capacitance

400

TTL/CMOS level, 4 mA 3-state output stage, pull-up (pins ADDR1, ADDR2, P1, P2, SCK, WS, SDO1, SDO2, SDI1
and SDI2)

LOW-level input voltage

0.8

HIGH-level input voltage

2.0

input capacitance

LOW-level output voltage

0.4

HIGH-level output voltage

2.4

load capacitance

100

input impedance

UTPUTS

CMOS level output, 4 mA 3-state output stage, slew rate controlled (pin SYSCLK)

LOW-level output voltage

0.3V

DDD

HIGH-level output voltage

0.7V

DDD

load capacitance

100

LIZ

3-state leakage current

= 0 to V

DDD

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

SIF1 and SIF2 analog inputs

SIF(max)(p-p)

maximum composite SIF input
voltage for clipping
(peak-to-peak value)

SIF input level adjust 0 dB

941

SIF input level adjust

10 dB

2976

SIF(min)(p-p)

minimum composite SIF input
voltage for lower limit of AGC
(peak-to-peak value)

SIF input level adjust 0 dB

SIF input level adjust

10 dB

188

AGC

AGC range

input frequency

9.2

MHz

input resistance

AGCLEV = 0

input capacitance

7.5

FM deviation

B/G standard; THD < 1%

100

kHz

FM(FS)

FM deviation full-scale level

terrestrial FM; level adjust
0 dB

150

kHz

C/N

FM carrier-to-noise ratio

bandwidth = 6 MHz;

white noise for S/N = 40 dB;
"CCIR468"; quasi peak

crosstalk attenuation
SIF1 to SIF2

= 4 to 9.2 MHz; note 3

Demodulator performance

THD + N

total harmonic distortion plus
noise

from FM source to any
output; V

= 1 V (RMS) with

low-pass filter

0.3

0.5

S/N

signal-to-noise ratio

SC1 from FM source to any
output; V

= 1 V (RMS);

"CCIR468"; quasi peak

SC2 from FM source to any
output; V

= 1 V (RMS);

"CCIR468"; quasi peak

3dB

3 dB bandwidth

from FM source to any
output

14.5

kHz

res

frequency response
20 Hz to 14 kHz

from FM to any output;
f

ref

= 1 kHz; inclusive

pre-emphasis and
de-emphasis

cs(dual)

dual signal channel separation note 4

cs(stereo)

stereo channel separation

note 5

AM suppression for FM

AM: 1 kHz, 30% modulation;
reference: 1 kHz, 50 kHz
deviation

S/N

AM demodulation

SIF level 100 mV (RMS);
54% AM; 1 kHz AF;
"CCIR468"; quasi peak

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

dB
Hz

-------

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

DENTIFICATION FOR

SYSTEMS

mod

pilot modulation for
identification

C/N

pilot sideband carrier-to-noise
ratio for identification start

ident

identification window

B/G stereo

slow mode

116.85

118.12

medium mode

116.11

118.89

fast mode

114.65

120.46

B/G dual

slow mode

273.44

274.81

medium mode

272.07

276.20

fast mode

270.73

277.60

ident(on)

total identification time ON

slow mode

medium mode

fast mode

0.5

ident(off)

total identification time OFF

slow mode

medium mode

fast mode

0.5

Analog audio inputs

ONO INPUT AND EXTERNAL INPUT

i(nom)(rms)

nominal level input voltage
(RMS value)

500

i(clip)(rms)

clipping level input voltage
(RMS value)

THD < 3%; note 6

1250

1400

input resistance

note 6

SCART

INPUTS

i(nom)(rms)

nominal level input voltage at
input pin (RMS value)

3 dB divider with external

15 k

resistor; note 7

350

i(clip)(rms)

clipping level input voltage at
input pin (RMS value)

3 dB divider with external

15 k

resistor; THD < 3%;

notes 6 and 7

1250

1400

input resistance

note 6

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

dB
Hz

-------

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Analog audio outputs

OUDSPEAKER

AIN

)

AND HEADPHONE

UXILIARY

)

OUTPUTS

o(clip)(rms)

clipping level output voltage
(RMS value)

THD < 3%

1250

1400

output resistance

150

250

375

L(AC)

AC load resistance

L(DC)

DC load resistance

load capacitance

offset(DC)

static DC offset voltage

mute

mute suppression

nominal input signal from
any source; f

= 1 kHz

ro(main,aux)

roll-off gain at 14.5 kHz for
Main and Auxiliary channels

from any source

PSRR

main,aux

power supply ripple rejection
for Main and Auxiliary
channels

ripple

= 70 Hz;

ripple

= 100 mV (peak);

Vref

= 47

signal from I

S-bus

SCART

OUTPUTS AND LINE OUTPUT

o(nom)(rms)

nominal level output voltage
(RMS value)

3 dB amplification

500

o(clip)(rms)

clipping level output voltage
(RMS value)

THD < 3%

1250

1400

output resistance

150

250

375

L(AC)

AC load resistance

L(DC)

DC load resistance

load capacitance

2.5

offset(DC)

static DC offset voltage

output amplifiers at 3 dB
position

mute

mute suppression

nominal input signal from
any source; f

= 1 kHz

bandwidth

from SCART, external and
mono sources;

3 dB bandwidth

kHz

from DSP sources;

3 dB bandwidth

14.5

kHz

PSRR

power supply ripple rejection

ripple

= 70 Hz;

ripple

= 100 mV (peak);

Vref

= 47

signal from I

S-bus

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Audio performance

THD + N

total harmonic distortion plus
noise

= V

= 1 V (RMS);

= 1 kHz; bandwidth

20 Hz to 15 kHz; note 8

from any analog audio
input to I

S-bus

0.1

0.3

from I

S-bus to any analog

audio output

0.1

0.3

SCART-to-SCART copy

0.1

0.3

SCART-to-Main copy

0.2

0.5

S/N

signal-to-noise ratio

reference voltage
V

= 1.4 V (RMS); f

= 1 kHz;

"CCIR468"; quasi peak;
note 8

from any analog audio
input to I

S-bus

from I

S-bus to any analog

audio output

SCART-to-SCART copy

SCART-to-Main copy

crosstalk attenuation

between any analog input
pairs; f

= 1 kHz

between any analog output
pairs; f

= 10 kHz

channel separation

between left and right of any
input pair

between left and right of any
output pair

gain from SCART-to-SCART
with

3 dB input voltage

divider

output amplifier in 3 dB
position; R

ext

= 15 k

10%

1.5

+1.1

output amplifier in 0 dB
position; R

ext

= 15 k

10%

4.5

3.0

1.9

Crystal specification (fundamental mode)

xtal

crystal frequency

24.576

MHz

load capacitance

series capacitance

parallel capacitance

pull

pulling sensitivity

changed from

18 to 16 pF

equivalent series resistance

at nominal frequency

equivalent series resistance of
unwanted mode

temperature range

+25

+70

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

-----------

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Notes

1. Definitions of levels and level setting:

a) The full-scale level for analog audio signals is 1.4 V (RMS).

b) The nominal level at the digital crossbar switch is defined at

15 dB (full-scale).

c) Nominal audio input levels for external and mono: 500 mV (RMS) at

9 dB (full-scale).

d) See also Tables 6 and 7.

2. All analog and digital supply ground pins are connected internally.

3. Set demodulator to AM mode. Apply an AM carrier (with 1 kHz and 100%) to one channel. Check AGC step. Switch

AGC off and set AGC to the gain step found. Measure the 1 kHz signal level of this channel and take it as a reference.
Switch to the other SIF input to which no signal is connected and which is terminated with 50

. Now measure the

1 kHz crosstalk signal level. The SIF source resistance should be low (50

4. FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output;

= 1 V (RMS) of modulated channel.

5. FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output;

= 1 V (RMS) of modulated channel. The stereo channel separation may be limited by adjustment tolerances of

the transmitter.

6. If the supply voltage for the TDA9870A is switched off, because of the ESD protection circuitry, all audio input pins

are short-circuited. To avoid a short-circuit at the SCART inputs a 15 k

resistor (

3 dB divider) has to be used.

7. The SCART specification allows a signal level of up to 2 V (RMS). Because of signal handling limitations due to the

5 V supply voltage for the TDA9870A, there is a need for fixed 3 dB attenuators at the SCART inputs. To achieve
SCART-to-SCART copies with 0 dB gain, there are 3 and 0 dB amplifiers at the outputs of SCART 1 and SCART 2
and at the line output. The attenuator is realized by an internal resistor that works together with an external series
resistor as a voltage divider. With this voltage divider the maximum SCART input signal level of 2 V (RMS) is scaled
down to 1.4 V (RMS) at the input pin. To avoid clipping, the 3 dB gain must not be used if the SCART input signal is
larger than 1.4 V (RMS).

8. ADC level adjust is 6 dB, all other level adjusts are 0 dB. If an external

3 dB divider is used set output buffer gain

to 3 dB, tone control to 0 dB, AVL off and volume control to 0 dB.

adjustment tolerance

drift

across temperature range

ageing

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

year

-----------

1999

Dec

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TD
A9870A

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

Table 6

Level setting FM at 0 dB (full-scale) = 1.4 V (RMS); note 1

Notes

1. Nominal level at digital crossbar is defined at

15 dB (full-scale). DAC gain setting 6 dB. Output buffer setting 0 dB. Nominal SCART output level

500 mV (RMS).

2. For stereo signals the output level is 6 dB lower. The level adjust has to be increased by 6 dB.

Table 7

Level setting SAT FM at 0 dB (full-scale) = 1.4 V (RMS)

2 CHANNEL

STANDARD

TRANSMITTER

NOMINAL

MODULATION

DEPTH

NOMINAL LEVEL AT

DEMODULATOR

OUTPUT

CARRIER 1

FREQUENCY

CARRIER 2

DE-EMPHASIS OF

CARRIER 1 AND

CARRIER 2

FM LEVEL

ADJUST SETTING

OF CARRIER 1

AND CARRIER 2

FREQUENCY

IDENT

15 kHz deviation

24 dB (full-scale);

note 2

4.5 MHz

4.724 MHz

+9 dB

B/G

27 kHz deviation

19 dB (full-scale)

5.5 MHz

5.742 MHz

+4 dB

D/K

27 kHz deviation

19 dB (full-scale)

6.5 MHz

6.742 MHz

+4 dB

27 kHz deviation

19 dB (full-scale)

6.5 MHz

6.25 MHz

+4 dB

27 kHz deviation

19 dB (full-scale)

6.5 MHz

5.742 MHz

+4 dB

SOURCE

TRANSMITTER

MAXIMUM

MODULATION

DEPTH

NOMINAL LEVEL AT

DEMODULATOR

OUTPUT

FM LEVEL

ADJUST

SETTING

MAXIMUM

LEVEL AT

CROSSBAR

DAC GAIN

SETTING

OUTPUT

BUFFER

NOMINAL SCART

OUTPUT VOLTAGE

SAT FM, stereo

50 kHz deviation

13 dB (full-scale)

+4 dB

9 dB (full-scale) +6 dB

0 dB

1 V (RMS)

SAT FM, mono

85 kHz deviation

9 dB (full-scale)

0 dB

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10 I

C-BUS CONTROL

10.1

Introduction

The TDA9870A is fully controlled via the I

C-bus. Control

is exercised by writing data to one or more internal
registers. Status information can be read from an array of
registers to enable the controlling microcontroller to
determine whether any action is required.

The device has an I

C-bus slave transceiver, in

accordance with the fast-mode specification, with a
maximum speed of 400 kbits/s. Information concerning the
I

C-bus can be found in brochure

C-bus and how to use

it" (order number 9398 393 40011). To avoid conflicts in a
real application with other ICs providing similar or
complementary functions, there are four possible slave
addresses available which can be selected by
pins ADDR1 and ADDR2 (see Table 8).

Table 8

Possible slave addresses

The I

C-bus interface remains operational in the standby

mode of the TDA9870A to allow control of the analog
source selectors with regard to SCART-to-SCART
copying.

The device will not respond to a `general call' on the
I

C-bus, i.e. when a slave address of 0000000 is sent by a

master.

The data transmission between the microcontroller and
the other I

C-bus controlled ICs is not disturbed when the

supply voltage of the TDA9870A is not connected.

10.2

Power-up state

At power-up the device is in the following state:

All outputs muted

No sound carrier frequency loaded

General purpose I/O pins ready for input (HIGH)

Input SIF1 selected with:

AGC on

Small hysteresis

SIF input level shift 0 dB.

Demodulators for both sound carriers set to FM with:

Identification for B/G, D/K, response time 1 s

Level adjust set to 0 dB

De-emphasis 50

Matrix set to mono.

Main channel set to FM input with:

Spatial off

Pseudo off

AVL off

Volume mute

Bass flat

Treble flat

Contour off

Bass boost flat.

Auxiliary channel set to FM input with:

Volume mute

Bass flat

Treble flat.

Feature interface all outputs off

Beeper off

Monitoring of carrier 1 FM demodulator DC output.

After power-up a device initialization has to be performed
via the I

C-bus to put the TDA9870A into the proper mode

of operation, in accordance with the desired TV standard,
audio control settings, etc.

ADDR2

ADDR1

SLAVE ADDRESS

LOW

HIGH

LOW

HIGH

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3

Slave receiver mode

As a slave receiver, the TDA9870A provides 46 registers for storing commands and data. These registers are accessed
via so-called subaddresses. A subaddress can be thought of as a pointer to an internal memory location.

Table 9

C-bus; slave address, subaddress and data format

Table 10 Explanation of Table 9

It is allowed to send more than one data byte per transmission to the TDA9870A. In this event, the subaddress is
automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register
locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with
ACK (acknowledge).

There is no `wrap-around' of subaddresses.

Commands and data are processed as soon as they have been completely received. Functions requiring more than one
byte will, thus, be executed only after all bytes for that function have been received. If the transmission is terminated
(STOP condition) before all bytes have been received, the incomplete data for that function are ignored.

Table 11 Format for a transmission employing auto-increment of subaddresses

Note

1. n data bytes with auto-increment of subaddresses.

Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the
functions of volume, bass and treble control, bass boost and level adjust.

Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will
then not be executed.

SLAVE ADDRESS

ACK

SUBADDRESS

ACK

DATA

ACK

BIT

FUNCTION

START condition

SLAVE ADDRESS

7-bit device address

data direction bit (write to device)

ACK

acknowledge by slave

SUBADDRESS

address of register to write to

DATA

data byte to be written into register

STOP condition

SLAVE ADDRESS

ACK

SUBADDRESS

ACK

DATA

BYTE A

(1)

DATA

ACK

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 12 Overview of the slave receiver registers

SUBADDRESS

(DECIMAL)

DATA

FUNCTION

MSB

LSB

AGC level shift, AGC gain selection

general configuration

monitor select, peak detector on/off

carrier 1 frequency; most significant part

carrier 1 frequency

carrier 1 frequency; least significant part

carrier 2 frequency; most significant part

carrier 2 frequency

carrier 2 frequency; least significant part

demodulator configuration

FM de-emphasis

FM matrix

channel 1 output level adjust

channel 2 output level adjust

set to logic 0; note 1

audio mute control

DAC output select

SCART 1 output select

SCART 2 output select

line output select

ADC output select

Main channel select

audio effects (AVL, pseudo and spatial)

volume control, Main left

volume control, Main right

contour control, Main

bass control, Main

treble control, Main

Auxiliary channel select

volume control, Auxiliary left

volume control, Auxiliary right

bass control, Auxiliary

treble control, Auxiliary

feature interface configuration

S1 output select

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Note

1. These bits have not been assigned to a function.

The following sub-sections provide a detailed description of the slave receiver registers.

10.3.1

AGC

GAIN REGISTER

If the automatic gain control function is switched off in the general configuration register, the contents of this register will
define a fixed gain of the AGC stage. The input voltages given are meant to generate a full-scale output from the SIF
ADC. If automatic gain control is on, the AGCGAIN setting is ignored. After switching off the automatic gain control
function, the latest gain control setting is copied to the AGC gain register.

If the AGC input level shift bit AGCLEV is set to logic 1 the input signal is scaled with

10 dB. The AGCLEV bit is also

active if the automatic gain function is enabled.

It should be noted that the input voltages should be considered as approximate target values.

Table 13 Subaddress 0 (note 1)

Note

1. The default setting at power-up is 00000000.

S1 input level adjust

S1 output level adjust

S2 output select

S2 input level adjust

S2 output level adjust

beeper frequency

beeper volume, Main and Auxiliary

bass boost, Main left and right

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

set to logic 0

AGCLEV

input signal scaled with

10 dB

input signal not scaled

AGCGAIN

gain control bits (see Table 14).

0 (LSB)

SUBADDRESS

(DECIMAL)

DATA

FUNCTION

MSB

LSB

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 14 Gain control bits

Note

1. The default setting at power-up is 00000000.

MSB

LSB

AGC GAIN

(dB)

SIF INPUT VOLTAGE

[mV (p-p)]

0/1

0.0

941/2976

0/1

0.8

861/2723

0/1

1.5

788/2490

0/1

2.3

720/2278

0/1

3.1

659/2084

0/1

3.9

603/1906

0/1

4.6

551/1744

0/1

5.4

504/1595

0/1

6.2

461/1459

0/1

7.0

422/1334

0/1

7.7

386/1221

0/1

8.5

353/1117

0/1

9.3

323/1021

0/1

10.1

295/934

0/1

10.8

270/855

0/1

11.6

247/782

0/1

12.4

226/715

0/1

13.2

207/654

0/1

13.9

189/598

0/1

14.7

173/547

0/1

15.5

158/501

0/1

16.3

145/458

0/1

17.0

132/419

0/1

17.8

121/383

0/1

18.6

111/350

0/1

19.4

101/321

0/1

20.1

93/293

0/1

20.9

85/268

0/1

21.7

78/245

0/1

22.5

71/224

0/1

23.2

65/205

0/1

24.0

59/188 (note 1)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.2

ENERAL CONFIGURATION REGISTER

Table 15 Subaddress 1 (note 1)

Note

1. The default setting at power-up is 11000000.

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

P2OUT

This bit controls the general purpose input/output pin P2. The contents of this bit
is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected
in the device status register (see Section 10.4.1, subaddress 0).

P1OUT

This bit controls the general purpose input/output pin P1. The contents of this bit
is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected
in the device status register (see Section 10.4.1, subaddress 0). P1OUT is
recommended to be used for switching an SIF trap for the adjacent picture carrier
in designs that employ such a trap.

STDBY

The TDA9870A is in the standby mode. Most functions are disabled and power
dissipation is somewhat reduced, but the analog selectors/matrices remain
operational to support analog copying from SCART-to-SCART.

The TDA9870A is in normal operating mode. On return from standby mode, the
device is in its Power-on reset mode and needs to be re-initialized.

INIT

Causes initialization of the TDA9870A to its default settings. This has the same
effect as a Power-on reset. If there is a conflict between the default settings and
any bit set to logic 1 in this register, the bits of this register have priority over the
corresponding default setting.

Automatically reset to logic 0 after initialization. When set to logic 0, the
TDA9870A is in normal operating mode.

CLRPOR

Resets the power fail detector to LOW.

This bit is automatically reset to logic 0 after bit POR in the device status register
has been reset.

AGCSLOW

A longer decay time is selected for input signals with strong video modulation
(intercarrier). This bit only has an effect when bit AGCOFF = 0.

Selects normal attack and decay times for the AGC.

AGCOFF

Forces the AGC block to a fixed gain as defined in the AGC gain register.

The automatic gain control function is enabled and the contents of the AGC gain
register is ignored.

0 (LSB)

SIFSEL

Selects pin SIF2 for input (recommended for satellite tuner).

Selects pin SIF1 for input (terrestrial TV).

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.3

ONITOR SELECT REGISTER

This register is used to define the signal source, the level of which is to be monitored, and if the peak level is to be
monitored. Peak level refers to the magnitude of the maximum excursion of a signal.

Audio magnitude/phase is related to the FM demodulator output. Phase information is provided, when it operates in
FM mode, while magnitude is supplied in AM mode.

Data can be read-out in the I

C-bus slave transmitter mode. By reading out level read-out registers

(subaddresses 5 and 6, see Section 10.4), the current peak level will be reset.

Table 16 Subaddress 2 (note 1)

Note

1. The default setting at power-up is 00000000.

Table 17 Monitor output

Table 18 Signal source (note 1)

Note

1. The term `crossbar' refers to the digital selector, where level-adjusted signals from various sources are available.

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

PEAKMON

selects the peak level of a source to be monitored

the last sample will be supplied

default value

monitor output (see Table 17)

signal source (see Table 18)

0 (LSB)

MONITOR OUTPUT

L input (channel 1, respectively)

R input (channel 2, respectively)

SIGNAL SOURCE

DC output of FM demodulator

audio magnitude/phase, FM demodulator output

crossbar input from FM/AM channel

don't care

crossbar input from I

S1 channel

crossbar input from I

S2 channel

crossbar input from audio ADC channel

input to Main channel DAC (without beeper)

L input

R input

-------------------------------------------

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.4

ARRIER

FREQUENCY REGISTER

The three bytes together constitute a 24-bit frequency
control word to represent the sound carrier (i.e. mixer)
frequency in accordance with the following formula:

Where:

data = 24-bit frequency control word

mix

= desired sound carrier frequency

clk

= 12.288 MHz (clock frequency of mixer)

= 16777216 (number of steps in a 24-bit word size).

Example: A 5.5 MHz sound carrier frequency will be
generated by sending the following sequence of data
bytes to the TDA9870A (data = 7509333 in decimal
notation or 729555 in hexadecimal):
01110010 10010101 01010101.

As three bytes are required to define a carrier frequency,
execution of this command starts only after all bytes have
been received. If an error occurs, e.g. a premature STOP
condition, partial data for this function is ignored.

The default setting at power-up is 00000000 for all three
bytes.

Most significant part at subaddress 3 and least significant
part at subaddress 5 (see Table 19).

Table 19 Subaddresses 3 to 5

data

mix

clk

---------

SUB-

ADDRESS

BIT

DESCRIPTION

7 (MSB)

carrier 1 frequency;
most significant part

carrier 1 frequency

carrier 1 frequency;
least significant part

0 (LSB)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.5

ARRIER

FREQUENCY REGISTER

Same as for sound carrier 1, except for subaddresses (subaddresses 6 to 8). If the carrier 2 frequency register is used,
it will be for the second FM sound carrier of a terrestrial or satellite FM program.

10.3.6

EMODULATOR CONFIGURATION REGISTER

It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial
2-carrier sound. Switching the identification off will reset the associated hardware to a defined state.

Table 20 Subaddress 9 (note 1)

Note

1. The default setting at power-up is 00000000.

Table 21 Identification mode

Table 22 Filter bandwidth channel 1 and channel 2

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

IDMOD1

these bits define the response time after which a FM sound mode identification
result may be expected; the longer the time, the more reliable the identification
(see Table 21)

IDMOD0

IDAREA

selects FM identification frequencies in accordance with the specification for
Korea

selects frequencies for Europe (B/G and D/K standard)

FILTBW1

selects filter bandwidth (see Table 22)

CH2MOD1

channel 2 receive mode: these bits control the hardware for the second sound
carrier (see Table 23)

CH2MOD0

FILTBW0

selects filter bandwidth (see Table 22)

0 (LSB)

CH1MODE

selects the hardware for the first sound carrier to operate in AM mode

FM mode is assumed; this applies to both terrestrial and satellite FM reception

IDENT MODE

slow

medium

fast

off/reset

FILTER

BANDWIDTH

FILTER MODES

CH1

CH2

narrow

recommended for nominal terrestrial broadcast conditions and
SAT with 2 carriers

extra wide

narrow

recommended only for high-deviation SAT mono carriers
(e.g. obsolete Main channel on Astra)

medium

recommended for moderately overmodulated broadcast conditions

wide

recommended for strongly overmodulated broadcast conditions

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 23 Channel 2 receive mode

10.3.7

EMPHASIS REGISTER

This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received
carrier. Bits B3 to B0 apply to sound carrier 1, bits B7 to B4 apply to sound carrier 2.

In the event of A2 reception, both groups must be set to the same characteristics.

Table 24 Subaddress 10 (note 1)

Notes

1. The default setting at power-up is 00000000.

2. The FM de-emphasis gain is 0 dB at 40 Hz.

Table 25 De-emphasis sound carrier 2

CHANNEL 2

don't care

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

ADEEM2

Activates the adaptive de-emphasis function, which is required for certain satellite
FM channels. The standard FM de-emphasis must then be set to 75

s (note 2).

The adaptive de-emphasis is off.

Time constant selection for FM de-emphasis (see Table 25).

ADEEM1

Activates the adaptive de-emphasis function, which is required for certain satellite
FM channels. The standard FM de-emphasis must then be set to 75

s (note 2).

The adaptive de-emphasis is off.

Time constant selection for FM de-emphasis (see Table 26).

0 (LSB)

DE-EMPHASIS

s (Europe)

s (M standard)

J17

off

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 26 De-emphasis sound carrier 1

10.3.8

MATRIX REGISTER

This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received
carrier and the related sound mode identification.

Table 27 Subaddress 11 (note 1)

Note

1. The default setting at power-up is 00000000.

Table 28 Dematrixing characteristics

Notes

1. CH1 input: audio signal from FM channel 1.

2. CH2 input: audio signal from FM channel 2.

3. For stereo Korea the dematrix applies 6 dB attenuation (see Table 6).

DE-EMPHASIS

s (Europe)

s (M standard)

J17

off

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

default value

dematrixing characteristics (see Table 28)

0 (LSB)

L OUTPUT

R OUTPUT

MODE

CH1 input; note 1

mono 1

CH2 input; note 2

mono 2

CH1 input; note 1

CH2 input; note 2

dual

CH2 input; note 2

CH1 input; note 1

dual swapped

2CH1 input

CH2 input

CH2 input; note 2

stereo Europe

stereo Korea; note 3

CH1 input

CH2 input

-----------------------------------------------------------

CH1 input

CH2 input

-----------------------------------------------------------

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.9

CHANNEL

LEVEL ADJUST REGISTER

This register is used to correct for standard and station-dependent differences of signal levels.

Table 29 applies to sound carrier 1.

Table 29 Subaddress 12

Note

1. The default setting at power-up is 00000000.

MSB

LSB

GAIN SETTING (dB)

+15

+14

+13

+12

+11

+10

0 (note 1)

mute

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.10 FM

CHANNEL

LEVEL ADJUST REGISTER

This register is used to correct for standard and station-dependent differences of signal levels. Table 30 applies to sound
carrier 2 in its FM and AM modes. In the event of A2, channels 1 and 2 should be adjusted to the same level.

Table 30 Subaddress 13

Note

1. The default setting at power-up is 00000000.

MSB

LSB

GAIN SETTING (dB)

+15

+14

+13

+12

+11

+10

0 (note 1)

mute

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.11 R

EGISTER

Set to logic 0. These bits have not been assigned to a function.

10.3.12 R

EGISTER

Set to logic 0. These bits have not been assigned to a function.

10.3.13 R

EGISTER

Set to logic 0. These bits have not been assigned to a function.

10.3.14 R

EGISTER

Set to logic 0. These bits have not been assigned to a function.

10.3.15 A

UDIO MUTE CONTROL REGISTER

When any of these bits are set to logic 1, the corresponding pair of output channels will be muted. A bit set to logic 0
allows normal signal output.

There is a soft-mute facility for the Main and Auxiliary output channels to provide click-free muting independent of the
volume control. This is switched on/off by bits MUTMAIN and MUTAUX.

Table 31 Subaddress 18 (note 1)

Note

1. The default setting at power-up is 11111111.

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

MUTI

mute I

S2 outputs

normal I

S2 outputs

MUTI

mute I

S1 outputs

normal I

S1 outputs

MUTDAC

mute internal DAC

normal internal DAC

MUTLINE

mute line outputs

normal line outputs

MUTSC2

mute SCART 2 outputs

normal SCART 2 outputs

MUTSC1

mute SCART 1 outputs

normal SCART 1 outputs

MUTAUX

mute Auxiliary outputs

normal Auxiliary outputs

0 (LSB)

MUTMAIN

mute Main outputs

normal Main outputs

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.17 SCART 1

OUTPUT SELECT REGISTER

This register is used to define both the signal source to be output at SCART 1 and the output channel selector mode.

Table 36 Subaddress 20 (note 1)

Note

1. The default setting at power-up is 00000001.

Table 37 Output channel selection

Table 38 Signal source selection

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

default value

SC1GAIN

Activates the 3 dB gain stage at the SCART 1 output buffers. As any SCART input
passes a 3 dB attenuator, this gain stage can be used to compensate that
attenuation, resulting in a 0 dB insertion loss when copying from SCART 2 input to
SCART 1 output. However, that gain must be used with great care, as it will cause
signal clipping at high input levels.

the audio signal output will be unchanged (0 dB gain)

output channel selection (see Table 37)

default value

signal source selection (see Table 38)

0 (LSB)

L OUTPUT

R OUTPUT

L input

R input

L input

R input

L input

SIGNAL SOURCE

SCART 1 input

SCART 2 input

external input

mono input

DAC input

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.18 SCART 2

OUTPUT SELECT REGISTER

This register is used to define both the signal source to be output at SCART 2 and the output channel selector mode.

Table 39 Subaddress 21 (note 1)

Note

1. The default setting at power-up is 00000000.

Table 40 Output channel selection

Table 41 Signal source selection

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

default value

SC2GAIN

Activates the 3 dB gain stage at the SCART 2 output buffers. As any SCART input
passes a 3 dB attenuator, this gain stage can be used to compensate that
attenuation, resulting in a 0 dB insertion loss when copying from SCART 1 input to
SCART 2 output. However, that gain must be used with great care, as it will cause
signal clipping at high input levels.

the audio signal output will be unchanged (0 dB gain)

output channel selection (see Table 40)

default value

signal source selection (see Table 41)

0 (LSB)

L OUTPUT

R OUTPUT

L input

R input

L input

R input

L input

SIGNAL SOURCE

SCART 1 input

SCART 2 input

external input

mono input

DAC input

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.19 L

INE OUTPUT SELECT REGISTER

By definition, the line output conveys the same signal as the Main (loudspeaker) channel, but in a non-processed form.
This register is used to characterize the signal to be output at the line output and define the output channel selector mode.

Table 42 Subaddress 22 (note 1)

Note

1. The default setting at power-up is 00000000.

Table 43 Output channel selection

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

set to logic 0

LINGAIN

activates the 3 dB gain stage at the line output buffers

the audio signal output will be unchanged (0 dB gain)

output channel selection (see Table 43)

set to logic 0

0 (LSB)

LINSEL

A signal from an analog source is being processed in the Main channel for line
output. Analog signal sources comprise SCART 1 input, SCART 2 input,
external input and mono input, i.e. any input to the ADC.

A signal from a digital source is being processed in the Main channel for line
output. Digital signal sources comprise FM, I

S1 input and I

S2 input.

L OUTPUT

R OUTPUT

L input

R input

L input

R input

L input

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.22 A

UDIO EFFECTS REGISTER

Switching the AVL off will reset the associated hardware to a defined state.

When the signal source for the Main channel is changed while the AVL is on, the AVL needs to be reset in order to avoid
excessive settling times. This can be achieved by switching the AVL off and on again.

The pseudo stereo function is based on an all-pass filter. A 90 degrees phase shift occurs at the frequencies stated in
Table 52. There is a gain of 3 dB in the left audio channel.

Table 50 Subaddress 25 (note 1)

Note

1. The default setting at power-up is 00000000.

Table 51 Spatial control setting

Table 52 Pseudo control setting

Table 53 AVL control mode

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

Default value.

SPATIAL1

These bits set the amount of the effect function (stereo base width expansion)
for stereo signals in the Main channel (see Table 51). This function should be
activated only in accordance with the result of the sound mode identification.

SPATIAL0

PSEUDO1

These bits set the amount of the effect function (pseudo stereo) for mono
signals in the Main channel (see Table 52). This function should be activated
only in accordance with the result of the sound mode identification.

PSEUDO0

AVL1

These bits set the mode of operation of the automatic volume level control
function at the entrance to the Main (loudspeaker) channel (see Table 53).

0 (LSB)

AVL0

SPATIAL SETTING (%)

off

PSEUDO SETTING (Hz)

off

300

200

150

AVL MODE

off/reset

short decay

medium decay

long decay

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.23 V

OLUME CONTROL REGISTERS

AIN

)

These two registers control the volume setting of the Main (loudspeaker) channel. The register at subaddress 26 applies
to the left channel signal, while the register at subaddress 27 applies to the right channel signal.

Balance control is exercised by offsetting the left and right channel volume settings.

Table 54 Subaddresses 26 and 27

MSB

LSB

VOLUME SETTING (dB)

+24

+23

+22

+21

+20

+19

+18

+17

+16

+15

+14

+13

+12

+11

+10

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

MSB

LSB

VOLUME SETTING (dB)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Note

1. The default setting at power-up is 10101100.

mute (note 1)

MSB

LSB

VOLUME SETTING (dB)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.24 C

ONTOUR CONTROL REGISTER

This register is used to apply the contour or loudness function (physiological volume control) to the left and right signal
channels of the Main channel by means of an extra bass boost. The gain setting must be chosen in accordance with the
volume control setting for the Main channel. For example, the contour gain could be incremented for every 5 dB, or so,
of decrease of the volume setting. This needs to be done by the microcontroller. The 0 dB contour setting is equal to
contour off.

Table 55 Subaddress 28

Note

1. The default setting at power-up is 00000000.

MSB

LSB

CONTOUR GAIN (dB)

0 (note 1)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.25 B

ASS CONTROL REGISTER

AIN

)

This register is used to apply bass control to the left and right signal channels of the Main channel.

Table 56 Subaddress 29

Note

1. The default setting at power-up is 00000000.

MSB

LSB

BASS SETTING (dB)

+15

+14

+13

+12

+11

+10

0 (note 1)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.28 V

OLUME CONTROL REGISTERS

UXILIARY

)

These two registers control the volume setting of the Auxiliary (headphone) channel. The register at subaddress 32
applies to the left channel signal, while the register at subaddress 33 applies to the right channel signal.

Balance control is exercised by offsetting the left and right channel volume settings.

Table 61 Subaddresses 32 and 33

MSB

LSB

VOLUME SETTING (dB)

+24

+23

+22

+21

+20

+19

+18

+17

+16

+15

+14

+13

+12

+11

+10

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

MSB

LSB

VOLUME SETTING (dB)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Note

1. The default setting at power-up is 10101100.

mute (note 1)

MSB

LSB

VOLUME SETTING (dB)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.29 B

ASS CONTROL REGISTER

UXILIARY

)

This register is used to apply bass control to the left and right signal channels of the Auxiliary channel.

Table 62 Subaddress 34

Note

1. The default setting at power-up is 00000000.

MSB

LSB

BASS SETTING (dB)

+15

+14

+13

+12

+11

+10

0 (note 1)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.30 T

REBLE CONTROL REGISTER

UXILIARY

)

This register is used to apply treble control to the left and right signal channels of the Auxiliary channel.

Table 63 Subaddress 35

Note

1. The default setting at power-up is 00000000.

MSB

LSB

TREBLE SETTING (dB)

+12

+11

+10

0 (note 1)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.31 F

EATURE INTERFACE CONFIGURATION REGISTER

Table 64 Subaddress 36 (note 1)

Note

1. The default setting at power-up is 00000000.

Table 65 System clock frequency selection

Note

1. With 16.384 MHz the duty cycle is 33%.

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

default value

SYSCL1

system clock frequency selection (see Table 65)

SYSCL0

SYSOUT

enables the output of a system (or master) clock signal at pin SYSCLK

the output will be off, thereby improving the EMC performance

SFORM

an MSB-aligned (MSB-first) serial output format is selected, i.e. a level change at
pin WS indicates the beginning of a new audio sample

the standard I

S-bus output format is selected

0 (LSB)

SOUT

enables the I

S-bus outputs (both serial data outputs plus serial bit clock and word

select) in a format determined by bit I

SFORM; the TDA9870A is then an I

S-bus

master

the outputs mentioned will be 3-stated, thereby improving the EMC performance

SYSCLK OUTPUT

FREQUENCY (MHz)

256f

8.192

384f

12.288

512f

16.384

(1)

768f

24.576

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.32 I

OUTPUT SELECT REGISTER

This register is used to define both the signal source to be output at I

S1 and the mode of the digital matrix for signal

selection.

Table 66 Subaddress 37 (note 1)

Note

1. The default setting at power-up is 00000000.

Table 67 Output selection

Table 68 Signal source selection (note 1)

Note

1. The Main and Auxiliary channel outputs will not contain the beeper signal.

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

default value

output selection (see Table 67)

default value

signal source selection (see Table 68)

0 (LSB)

L OUTPUT

R OUTPUT

L input

R input

L input

R input

L input

SIGNAL SOURCE

FM output

don't care

S1 input

S2 input

ADC output

AVL output

Auxiliary output

Main output

--------------

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.33 I

INPUT LEVEL ADJUST REGISTER

This register is used to adjust the input level at the I

S1 interface. Left and right signal channel are treated identically.

Table 69 Subaddress 38

Note

1. The default setting at power-up is 00000000.

MSB

LSB

GAIN SETTING (dB)

+15

+14

+13

+12

+11

+10

0 (note 1)

mute

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.34 I

OUTPUT LEVEL ADJUST REGISTER

This register is used to adjust the output level at the I

S1 interface. Left and right signal channel are treated identically.

Table 70 Subaddress 39

Note

1. The default setting at power-up is 00000000.

MSB

LSB

GAIN SETTING (dB)

+15

+14

+13

+12

+11

+10

0 (note 1)

mute

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.35 I

OUTPUT SELECT REGISTER

This register is used to define both the signal source to be output at I

S2 and the mode of the digital matrix for signal

selection.

Table 71 Subaddress 40 (note 1)

Note

1. The default setting at power-up is 00000000.

Table 72 Output selection

Table 73 Signal source selection (note 1)

Note

1. The Main and Auxiliary channel outputs will not contain the beeper signal.

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

default value

output selection (see Table 72)

default value

signal source selection (see Table 73)

0 (LSB)

L OUTPUT

R OUTPUT

L input

R input

L input

R input

L input

SIGNAL SOURCE

FM output

don't care

S1 input

S2 input

ADC output

AVL output

Auxiliary output

Main output

--------------

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.36 I

INPUT LEVEL ADJUST REGISTER

This register is used to adjust the input level at the I

S2 interface. Left and right signal channel are treated identically.

Table 74 Subaddress 41

Note

1. The default setting at power-up is 00000000.

MSB

LSB

GAIN SETTING (dB)

+15

+14

+13

+12

+11

+10

0 (note 1)

mute

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.37 I

OUTPUT LEVEL ADJUST REGISTER

This register is used to adjust the output level at the I

S2 interface. Left and right signal channel are treated identically.

Table 75 Subaddress 42

Note

1. The default setting at power-up is 00000000.

MSB

LSB

GAIN SETTING (dB)

+15

+14

+13

+12

+11

+10

0 (note 1)

mute

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.38 B

EEPER FREQUENCY CONTROL REGISTER

This register is used to select from sample beeper oscillator frequencies. The beeper output signal is added to the Main
and Auxiliary channel output DAC.

Due to the frequency response of the audio DACs upsampling filters, the 25 kHz beep is approximately 5 dB louder than
the 390 Hz beep.

Table 76 Subaddress 43 (note 1)

Note

1. The default setting at power-up is 00000000.

10.3.39 B

EEPER VOLUME CONTROL REGISTER

This register is used to set the beeper volume. The gain setting is relative to digital full-scale at the input to the Main and
Auxiliary channel output DACs. The beeper volume is independent of any other volume setting.

The beeper signal is added to the Main and Auxiliary channel output signals in the 2

domain. The beeper volume

should be set with great care, when the audio signals in the Main and Auxiliary channels are close to digital full-scale, to
avoid output signal distortion due to overload.

MSB

LSB

GENERATED FREQUENCY (Hz)

25000

7040

3580

1770

1270

900

640

390

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 77 Subaddress 44

Note

1. The default setting at power-up is 00100000.

MSB

LSB

GAIN SETTING (dB)

mute (note 1)

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.3.40 B

ASS BOOST CONTROL REGISTER

This register is used to select from a few sample bass boost settings to modify the frequency characteristics of the Main
channel (shelving filter). Bits B3 to B0 apply to the left channel, bits B7 to B4 apply to the right channel. This function
must be used with care in order to avoid clipping distortion at high volume settings.

More sophisticated control of the bass boost filter can be exercised in the expert mode (see Section 10.5). The user then
has full control over this second-order filter and can, within limits, realize bass equalizers with arbitrary centre
frequencies, Q factors and boost/cut settings.

Table 78 Subaddress 45 (note 1)

Note

1. The default setting at power-up is 00000000.

Table 79 Gain setting of right channel

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

gain setting of right channel (see Table 79)

gain setting of left channel (see Table 80)

0 (LSB)

GAIN SETTING (dB)

CORNER FREQUENCY (Hz)

350

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.4

Slave transmitter mode

As a slave transmitter, the TDA9870A provides 13 registers with status information and data, a part of which is for Philips
internal purposes only. These registers can be accessed by means of subaddresses.

Table 81 General format for reading data from the TDA9870A

Table 82 Explanation of Tables 81 and 83

Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the
TDA9870A. In this situation, the subaddress is automatically incremented after each data byte, which results in reading
the sequence of data bytes from successive register locations, starting at SUBADDRESS.

Table 83 Format of a transmission using automatic incrementing of subaddresses

Note

1. n data bytes with auto-increment of subaddresses.

Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master).
The subaddresses `wrap around' from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress,
the device will send a data pattern of all ones, i.e. FF in hexadecimal notation.

S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr

SLAVE ADDRESS

ACK

DATA NAm P

BIT

FUNCTION

START condition

SLAVE ADDRESS

7-bit device address

data direction bit (write to device)

ACK

acknowledge (by the slave)

SUBADDRESS

address of register to read from

repeated START condition

data direction bit (read from device)

DATA

data byte read from register

NAm

not acknowledge (by the master)

acknowledge (by the master)

STOP condition

S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr

SLAVE

ADDRESS

1 ACK

DATA BYTE

(1)

DATA NAm P

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 84 Overview of the slave transmitter registers; note 1

Notes

1. X indicates a bit that has not been assigned to a function. This bit is reserved for future extensions.

2. Registers from subaddress 251 to 255 are for Philips internal purposes only. They are considered as a set of

registers for the identification of individual members and some key parameters in a family of devices.

The following sub-sections provide a detailed description of the slave transmitter registers.

SUBADDRESS

(DECIMAL)

DATA

FUNCTION

MSB

LSB

device status (power-on, identification, etc.)

don't care; note 1

level read-out (MSB)

level read-out (LSB)

SIF level

251

test register 3; note 2

252

test register 2; note 2

253

test register 1; note 2

254

device identification code

255

software identification code

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.4.1

EVICE STATUS REGISTER

Table 85 Subaddress 0

10.4.2

EGISTER

Subaddress 1: These bits have not been assigned to a function. These bits are reserved for future extensions.

10.4.3

EGISTER

Subaddress 2: These bits have not been assigned to a function. These bits are reserved for future extensions.

10.4.4

EGISTER

Subaddress 3: These bits have not been assigned to a function. These bits are reserved for future extensions.

10.4.5

EGISTER

Subaddress 4: These bits have not been assigned to a function. These bits are reserved for future extensions.

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

P2IN

This bit reflects the status of the corresponding general purpose port of pin P2
(see Section 10.3.2).

P1IN

This bit reflects the status of the corresponding general purpose port of pin P1
(see Section 10.3.2).

don't care

IDDUA

This bit is logic 1 if an FM dual-language signal has been identified. When
neither IDSTE nor IDDUA are set, the received signal has to be assumed to be
FM mono.

IDSTE

This bit is logic 1 if an FM stereo signal has been identified.

0 (LSB)

POR

Power fail bit: the power supply for the digital part of the device, V

DDD2

, has

temporarily been lower than the specified lower limit. If this is detected an
initialization of the TDA9870A has to be carried out to ensure a reliable
operation.

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.4.6

EVEL READ

OUT REGISTERS

These two bytes constitute a word that provides data from
a location that has been specified with the monitor select
register. The most significant byte of the data is stored at
subaddress 5.

If peak-level monitoring has been selected, the peak-level
monitoring register is cleared and monitoring resumes
after its contents has been transferred to these two bytes.

Table 86 Subaddresses 5 and 6

10.4.7

SIF

LEVEL REGISTER

When the SIF AGC is on, bits B4 to B0 of this register
contain a number that gives an indication of the SIF input
level. That number corresponds to the AGC gain register
setting (see Section 10.3.1).

When the SIF AGC is off, this register returns the contents
of the AGC gain register.

Table 87 Subaddress 7

10.4.8

EST REGISTER

This register contains, as a binary number, the highest
memory address used for the Coefficient RAM (CRAM,
expert mode).

Table 88 Subaddress 251

10.4.9

EST REGISTER

This register contains, as a binary number, the highest
subaddress used for slave receiver registers.

Table 89 Subaddress 252

SUB-

ADDRESS

BIT

DESCRIPTION

7 (MSB) most significant bit or sign bit

0 (LSB)

7 (MSB)

0 (LSB)

least significant bit

BIT

NAME

VALUE

DESCRIPTION

7 (MSB)

bit not assigned

indication of SIF
input level

0 (LSB)

MSB

LSB

MSB

LSB

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

10.4.10 T

EST REGISTER

This register contains, as a binary number, the highest
subaddress used for slave transmitter (status) registers.

Table 90 Subaddress 253

10.4.11 D

EVICE IDENTIFICATION CODE

There will be several devices in the digital TV sound
processor family. This byte is used to identify the individual
family members.

Table 91 Subaddress 254

10.4.12 S

OFTWARE IDENTIFICATION CODE

It is likely that during the life time of this family of devices
several versions of the DSP software will be made, e.g., to
accommodate new application concepts, respond to
customer wishes, etc. This byte is used to identify the
different releases.

Table 92 Subaddress 255

10.5

Expert mode

In addition to the slave receiver and slave transmitter
modes previously described, there is a special `expert'
mode that gives direct write access to the internal CRAM
of the DSP.

In this mode, transferred data contains 12-bit coefficients.
As these coefficients bypass on-chip coefficient look-up
tables for many functions, they directly influence the
processing of signals within the DSP.

This mode must be used with great care. It can be used to
create user-defined characteristics, such as a tone control
with different corner frequencies or special boost/cut
characteristics to correct the low-frequency loudspeaker
and/or cabinet frequency responses.

As the coefficients do not fit into one data byte, they have
to be split and arranged (see Table 95). The most
significant bit is transferred first.

The general format described in Table 95 shows the
minimum number of data bytes required, i.e. two bytes for
the transfer of a single coefficient.

Should more than one coefficient be sent, then the CRAM
address will be automatically incremented after each
coefficient, resulting in writing the sequence of coefficients
into successive memory locations, starting at
CRAM ADDRESS. A transmission can start with any valid
CRAM address. If two coefficients are to be transferred,
they are arranged as shown in Table 96.

With any odd number of coefficients to be transferred, the
least significant nibble of the last byte is regarded as
containing don't care data.

As the transfer of coefficients cannot be accomplished
within one audio sample period, it is necessary that
received coefficients be buffered and made active all at the
same time to avoid audio signal transients. The receive
buffer is designed to store up to 8 coefficients in addition
to the CRAM address. Each byte that fits into the buffer is
acknowledged with ACK (acknowledge). If an attempt is
made to write more coefficients than the buffer can store,
the device acknowledges with NACK (not acknowledge)
and any further coefficients are ignored. Coefficients that
are already in the receive buffer remain intact.

An expert mode transfer ends when the I

C-bus STOP

condition or a repeated START condition has been
detected. Only those coefficients that have been received
during the last transmission will then be copied from the
buffer to the CRAM.

To make efficient and correct use of the expert mode, it is
recommended to transfer all coefficients for any one
function in a single transmission.

There is no checking of memory addresses and the
automatic incrementing of addresses does not stop at the
highest used CRAM address. The user of this expert mode
must be fully acquainted with the relevant procedures.

More information concerning the functions of this device,
such as the number of coefficients per function, their
default values, memory addresses, etc., can be supplied
on request at a later date.

MSB

LSB

MSB

LSB

MSB

LSB

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

Table 93 General format for entering the expert mode and writing coefficients into the TDA9870A

Table 94 Explanation of Table 93

Table 95 General format (notes 1, 2 and 3)

Notes

1. X = don't care.

2. MST = most significant third.

3. LST = least significant third.

Table 96 Transfer of two coefficients

SLAVE

ADDRESS

ACK

10000000

ACK

CRAM

ADDRESS

ACK

DATA

ACK

DATA

ACK

BIT

FUNCTION

START condition

SLAVE ADDRESS

7-bit device address

data direction bit (write to device)

ACK

acknowledge

10000000

pattern to enter the expert mode

CRAM ADDRESS

start address of coefficient RAM to write to

DATA

data byte containing part of a coefficient

STOP condition

BYTE

DATA

DESCRIPTION

1 data byte

2 MST of 1st coefficient

2 data byte

1 LST of 1st coefficient

BYTE

DATA

DESCRIPTION

1 data byte

2 MST of 1st coefficient

2 data byte

1 LST of 1st coefficient + 1 MST of 2nd coefficient

3 data byte

2 LST of 2nd coefficient

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

11 I

S-BUS DESCRIPTION

The feature interface of the TDA9870A contains two serial
audio inputs and outputs and associated clock signals.
It can be used to supply, for example, audio signals from
received TV programs to a digital audio output device
(AES/EBU format), or import serial audio signals from
other sources for reproduction through the TV set's
loudspeaker and/or headphone channels. Apart from such
simple data input or output, it is also possible to run audio
signals through an external DSP, which performs some
additional functions, such as room simulation, Dolby
Surround Pro Logic etc. and feed those signals back into
the loudspeaker and/or headphone channels of the
TDA9870A.

Two serial audio formats are supported at the feature
interface, i.e. the I

S-bus format and a very similar

MSB-aligned format. The difference is illustrated in Fig.9.

In both formats the left audio channel of a stereo sample
pair is output first and is placed on the serial data line (SDI
for input, SDO for output) when the Word Select line (WS)
is LOW. Data is written at the trailing edge of SCK and
read at the leading edge of SCK. The most significant bit
is sent first.

At power-up, the outputs of the feature interface are
3-stated to reduce EMC and allow for combinations with
other ICs. If output is desired, it has to be activated by
means of an I

C-bus command.

When the output is enabled, the serial audio data can be
taken from pins SDO1 and SDO2. Depending on the
signal source, switch and matrix positions, the output can
be either mono, stereo or dual language sound on either
output.

The word select output is clocked with the audio sample
frequency at 32 kHz. The serial clock output (SCK) is
clocked at a frequency of 2.048 MHz. This means, that
there are 64 clock pulses per pair of stereo output
samples, or 32 clock pulses per sample. Depending again
on the signal source, the number of significant bits on the
serial data outputs, SDO1 and SDO2, is between
14 and 18.

Apart from just feeding a digital audio device, such as a
DAC or an AES/EBU transmitter, the serial data outputs
can be connected directly to the serial inputs (loop-back
connection) or first to an external device, e.g. a feature
DSP such as the SAA7710 and then back to the serial
inputs. In all of these configurations, the SCK and WS
clocks will be generated by the TDA9870A, which then is
the I

S-bus master.

The serial data inputs, SDI1 and SDI2, are active at all
times, independent of the serial data outputs being on or
off. When the serial data outputs are off (either after
power-up or via the appropriate I

C-bus command) serial

data and clocks WS and SCK from a separate digital audio
source can be fed into the TDA9870A, be processed and
output in accordance with internal selector positions,
provided that the following criteria are met:

32 kHz audio sample frequency

32 clock bits per sample

External timing and data synchronized to TDA9870A.

In such cases, the external source is the I

S-bus master

and the TDA9870A is the I

S-bus slave.

To support synchronization of external devices or as a
master clock for them, a system clock output, SYSCLK, is
available from the TDA9870A. At power-up it is off. It can
be enabled and the output frequency set via an I

C-bus

command. Available output frequencies are
8.192, 12.288, 16.384 and 24.576 MHz.

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

12 APPLICATION INFORMATION

handbook, full pagewidth

1.5

10 k

47 pF

100 nF

C5
47

C1
4.7

VDDD2

VDDA

VSSA1

TEST1

Iref

VDEC1

VSSA3

MOR

AUXOL

PCAPL

PCAPR

SCOL2

SCOR2

SCOL1

SCOR1

i.c.

SCIL2

SCIL1

SCIR1

SCIR2

i.c.

Vref3

Vref2

Vref(n)

Vref(p)

VSSA2

VDEC2

VSSD3

VSSA4

VSSD2

AUXOR

LOR

i.c.

ADDR1

SCL

SDA

SIFSAT

CRESET

XTALI

XTALO

ADDR2

SIF1

SIFTV

SIF2

VDDD1

VSSD1

VSSD4

Vref1

SYSCLK

SCK

SDO2

SDO1

SDI2

SDI1

MONOIN

EXTIR

EXTIL

TEST2

LOL

MOL

470 nF

1.5

2.2

C33

C31

C28

C32

2.2

C30

2.2

C27

2.2

C25

2.2

C20

2.2

C19

2.2

C18

C15
47

C14
4.7

C16

2.2

C17

C21

10 nF

C29

10 nF

C26

10 nF

C24

10 nF

C23

10 nF

C13

330 nF C12

330 nF

C11

330 nF C10

330 nF

C22

10 nF

2.2

C34

C35

R19

5 V

15 k

270

24.576 MHz

MHB596

TDA9870A

(TDA9870AH)

(53) 61

(52) 60

(51) 59

(50) 58

(49) 57

(48) 56

(47) 55

(46) 54

(45) 53

(44) 52

(43) 51

(40) 48

(39) 47

(42) 50

(41) 49

(38) 46

(35) 43

(34) 42

(33) 41

(37) 45

(36) 44

(32) 40

(31) 39

(30) 38

(27) 35

(26) 34

(25) 33

(29) 37

(28) 36

(54) 62

(55) 63

(56) 64

4 (60)

5 (61)

6 (62)

7 (63)

8 (64)

9 (1)

10 (2)

11 (3)

12 (4)

13 (5)

14 (6)

17 (9)

18 (10)

15 (7)

16 (8)

19 (11)

22 (14)

23 (15)

24 (16)

20 (12)

21 (13)

25 (17)

26 (18)

27 (19)

30 (22)

31 (23)

32 (24)

28 (20)

29 (21)

3 (59)

2 (58)

1 (57)

Fig.10 Schematic for measurements.

The pin numbers given in parenthesis refer to the TDA9870AH version.

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

handbook, full pagewidth

MHB597

10 k

2.2 k

47 pF

100 nF

C6
470 nF

C2
470 nF

TDA9870A

(TDA9870AH)

VDDD2

VDDA

VSSA1

TEST1

Iref

VDEC1

VSSA3

MOR

AUXOL

PCAPL

PCAPR

SCOL2

SCOR2

SCOL1

SCOR1

i.c.

SCIL2

SCIL1

SCIR1

SCIR2

i.c.

Vref3

Vref2

Vref(n)

Vref(p)

VSSA2

VDEC2

VSSD3

VSSA4

VSSD2

AUXOR

LOR

i.c.

ADDR1

SCL

SDA

SIFSAT

CRESET

XTALI

XTALO

ADDR2

SIF1

SIFTV

SIF2

VDDD1

VSSD1

VSSD4

Vref1

SYSCLK

SCK

SDO2

SDO1

SDI2

SDI1

MONOIN

EXTIR

EXTIL

TEST2

LOL

MOL

(53) 61

(52) 60

(51) 59

(50) 58

(49) 57

(48) 56

(47) 55

(46) 54

(45) 53

(44) 52

(43) 51

(40) 48

(39) 47

(42) 50

(41) 49

(38) 46

(35) 43

(34) 42

(33) 41

(37) 45

(36) 44

(32) 40

(31) 39

(30) 38

(27) 35

(26) 34

(25) 33

(29) 37

(28) 36

(54) 62

(55) 63

(56) 64

4 (60)

5 (61)

6 (62)

7 (63)

8 (64)

9 (1)

10 (2)

11 (3)

12 (4)

13 (5)

14 (6)

17 (9)

18 (10)

15 (7)

16 (8)

19 (11)

22 (14)

23 (15)

24 (16)

20 (12)

21 (13)

25 (17)

26 (18)

27 (19)

30 (22)

31 (23)

32 (24)

28 (20)

470 nF

C10

29 (21)

3 (59)

2 (58)

1 (57)

2.2

470 nF

2.2

C39

C36

C32

470 pF

C38

470 pF

C40

C37

2.2

C35

2.2

C33

2.2

C29

2.2

C25

2.2

C23

2.2

C21

C16
47

C15
470 nF

C17

2.2

C19

C26

10 nF

C34

10 nF

C31

10 nF

C30

10 nF

C20

470 pF

C24

470 pF

C22

470 pF

C18

470 pF

C28

10 nF

C14

330 nF C13

330 nF

C12

330 nF C11

330 nF

C27

10 nF

2.2

470

C41

C42

R13

R12

5 V

15 k

R11

R10

15 k

270

24.576 MHz

2.2 k

100

0 V

POWER

5 V

Fig.11 Schematic for application.

L1 to L9 are ferrite beads.

The pin numbers given in parenthesis refer to the TDA9870AH version.

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

14 SOLDERING

14.1

Introduction

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.

14.2

Through-hole mount packages

14.2.1

OLDERING BY DIPPING OR BY SOLDER WAVE

The maximum permissible temperature of the solder is
260

C; solder at this temperature must not be in contact

with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg(max)

). If the

printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

14.2.2

ANUAL SOLDERING

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300

C it may remain in contact for up to

10 seconds. If the bit temperature is between
300 and 400

C, contact may be up to 5 seconds.

14.3

Surface mount packages

14.3.1

EFLOW SOLDERING

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

14.3.2

AVE SOLDERING

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

14.3.3

ANUAL SOLDERING

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

14.4

Suitability of IC packages for wave, reflow and dipping soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

4. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

MOUNTING

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

DIPPING

Through-hole mount DBS, DIP, HDIP, SDIP, SIL

suitable

(2)

suitable

Surface mount

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP,
SMS

not suitable

(3)

suitable

PLCC

(4)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(4)(5)

suitable

SSOP, TSSOP, VSO

not recommended

(6)

suitable

1999 Dec 20

Philips Semiconductors

Product specification

Digital TV Sound Processor (DTVSP)

TDA9870A

15 DEFINITIONS

16 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

17 PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

Philips Semiconductors a worldwide company

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905

Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777

Printed in The Netherlands

545004/02/pp

Date of release:

1999 Dec 20

Document order number:

9397 750 06064

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA9870AH

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TDA9870AH