1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

FEATURES

Complete 1.3 GHz single chip system

Four PNP band switch buffers (40 mA)

33 V output tuning voltage

In-lock detector

5-step ADC

15-bit programmable divider

Programmable reference divider ratio
(512, 640 or 1024)

Programmable charge-pump current (60 or 280

Programmable automatic charge-pump current switch

Varicap drive disable

Universal bus protocol I

C-bus or 3-wire bus:

bus protocol for 18 or 19 bits transmission

(3-wire bus)

extra protocol for 27 bits for test and features

(3-wire bus)

address plus 4 data bytes transmission (I

C-bus write

mode)

address plus 1 status byte transmission (I

C-bus

read mode)

three independent I

C-bus addresses

Low power and low radiation.

APPLICATIONS

TV tuners and front ends

VCR tuners.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TSA5526M

SSOP16

plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

TSA5526T

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

TSA5527M

SSOP16

plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

TSA5527T

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

TSA5526AM

SSOP16

plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

TSA5526AT

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

TSA5527AM

SSOP16

plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

TSA5527AT

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

QUICK REFERENCE DATA

Notes

1. One band switch buffer ON, I

= 40 mA.

2. One band switch buffer ON, I

= 40 mA; two buffers ON, maximum sum of I

= 50 mA.

3. The power dissipation is calculated as follows:

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CC1

supply voltage (+5 V)

4.5

5.5

CC2

band switch supply voltage (12 V)

CC1

13.5

CC1

supply current

CC2

band switch supply current

note 1

RF input frequency

1300

MHz

i(RF)

RF input voltage

= 80 to 150 MHz

dBm

= 150 to 1000 MHz

dBm

= 1000 to 1300 MHz

dBm

xtal

crystal oscillator input frequency

3.2

4.0

4.48

MHz

o(PNP)

PNP band switch buffers output
current

note 2

tot

total power dissipation

note 3

250

400

stg

storage temperature

+150

amb

operating ambient temperature

+85

CC1

CC2

(

)

CE satPNP

(

)

V33 2

(

)

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

GENERAL DESCRIPTION

The device is a single-chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier and the 33 V output.
Four high-current PNP band switch buffers are provided
for band switching. Two PNP buffers can be switched on
simultaneously. The sum of the collector currents is limited
to 50 mA.

Depending on the reference divider ratio (512, 640 or
1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz using a 4 MHz crystal.

The device can be controlled in accordance with the
I

C-bus format or the 3-wire bus format depending on the

voltage applied to the SW input (see Table 2). In the 3-wire
bus mode (SW = HIGH) pin 12 is the LOCK output.
The lock output is LOW when the PLL loop is locked. In the
I

C-bus mode (SW = LOW) the LOCK detector bit FL is set

to logic 1 when the loop is locked and is read on the SDA
line (status byte) during a read operation. The ADC input
is available on pin 12 for AFC control in the I

C-bus mode

only. The ADC code is read during a read operation on the
I

C-bus. In the test mode pin 12 is used as a test output for

ref

and

div

in the I

C-bus mode and the 3-wire bus mode

(see Table 6).

When the automatic charge-pump current switch mode is
activated, depending on the device given in Table 6, and
when the loop is phase-locked, the charge-pump current
value is automatically switched to LOW.

This action is taken to improve the carrier-to-noise ratio.
The status of this feature can be read in the ACPS flag
during a read operation on the I

C-bus (see Table 8).

C-bus format (SW = LOW)

Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four PNP band switch buffers, set the charge-pump
current and the reference divider ratio.

The device has three independent I

C-bus addresses

which can be selected by applying a specific voltage on the
CE input (see Table 5). The general address C2 is always
valid. When the I

C-bus format is fully used, TSA5526 and

TSA5527 are equal.

3-wire bus format (SW = V

CC1

or open-circuit)

Data is transmitted to the device during a HIGH level on
the CE input (enable line pin 15). The device is compatible
with 18-bit and 19-bit data formats. The first four bits are
used to program the PNP band switch buffers and the
remaining bits are used to control the programmable
divider. A 27-bit data format may also be used to set the
charge-pump current, the reference divider ratio and for
test purposes. The differences between TSA5526 and
TSA5527 are given in Table 1.

When the 27-bit format is used, the TSA5526 and
TSA5527 are equal and the reference divider is controlled
by the RSA and RSB bits (see Table 7 and
Figs 3, 4 and 5).

Table 1

Differences between TSA5526 and TSA5527

Notes

1. The selection of the reference divider is given by an automatic identification of the data word length.

2. The reference divider is set to 640 at power-on reset.

TYPE NUMBER

DATA WORD

REFERENCE DIVIDER

FREQUENCY STEP (kHz)

TSA5526

18-bit

512

(1)

62.5

TSA5526

19-bit

1024

(1)

31.25

TSA5527

19-bit

640

(2)

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

PINNING

SYMBOL

PIN

DESCRIPTION

RF signal input

ground

CC1

supply voltage (+5 V)

CC2

band switch supply voltage (+12 V)

BS4

PNP band switch buffer output 4

BS3

PNP band switch buffer output 3

BS2

PNP band switch buffer output 2

BS1

PNP band switch buffer output 1

charge-pump output

tune

tuning voltage output

bus format selection input, I

C-bus

or 3-wire

LOCK/ADC

lock detector output (3-wire bus/
ADC input (I

C-bus)

SCL

serial clock input

SDA

serial data input/output

chip enable/address selection input

XTAL

crystal oscillator input

Fig.2 Pin configuration.

handbook, halfpage

TSA5526
TSA5527

MBE326

BS4

BS3

BS2

BS1

LOCK/ADC

SCL

SDA

XTAL

CC1

CC2

Vtune

FUNCTIONAL DESCRIPTION

The device is controlled via the I

C-bus or the 3-wire bus

depending on the voltage applied to the SW input (pin 11).
A HIGH level on the SW input enables the 3-wire bus
inputs which are CE (Chip Enable), SDA (serial data input)
and SCL (serial clock input). A LOW level on the SW input
enables the I

C-bus inputs which are AS (Address

Selection input), SDA (serial data input/output) and SCL
(serial clock input). The bus format selection is given in
Table 2.

C-bus mode (SW = LOW); see Table 3

RITE MODE

(R/W = 0)

Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are required to
fully program the device. The bus transceiver has an
auto-increment facility which permits the programming of
the device within one single transmission
(address + 4 data bytes).

The device can also be partially programmed providing
that the first data byte following the address is Divider
Byte 1 (DB1) or the Control Byte (CB). The bits in the data
bytes are defined in Table 3.

The first bit of the first data byte transmitted indicates
whether frequency data (first bit = logic 0) or control and
band switch data (first bit = logic 1) will follow. Until an
I

C-bus STOP command is sent by the controller,

additional data bytes can be entered without the need to
readdress the device. The frequency register is loaded
after the 8th clock pulse of the second Divider Byte (DB2),
the control register is loaded after the 8th clock pulse of the
Control Byte (CB) and the band switch register is loaded
after the 8th clock pulse of the Band switch Byte (BB).

C-

BUS ADDRESS SELECTION

The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 3) in one system by applying a
specific voltage to the CE input.

The relationship between MA1 and MA0 and the input
voltage applied to the CE input is given in Table 5.

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

Table 2

Bus format selection

Table 3

C-bus data format

Table 4

Description of Table 3

Table 5

C-bus address selection

PIN

NAME

3-WIRE BUS MODE

C-BUS MODE

OPEN or HIGH

LOW

LOCK/ADC

LOCK/TEST output

ADC input/TEST output

SCL

clock input

SCL input

SDA

data input

SDA input/output

chip enable input

address selection input

BYTE

MSB

DATA BYTE

LSB

SLAVE

ANSWER

Address Byte (ADB)

MA1

MA0

R/W = 0

Divider Byte 1 (DB1)

N14

N13

N12

N11

N10

Divider Byte 2 (DB2)

Control Byte (CB)

RSA

RSB

Band switch Byte (BB)

BS4

BS3

BS2

BS1

SYMBOL

DESCRIPTION

acknowledge

MA1 and MA0

programmable address bits (see Table 5)

N14 to N0

programmable divider bits; N = N14

+ N13

+ ... + N1

2 + N0

charge-pump current; CP = 0 = 60

A; CP = 1 = 280

A (default)

T2 to T0

test bits (see Table 6); for normal operation T2 = 0, T1 = 0 and T0 = 1 (default)

RSA and RSB

reference divider ratio select bits (see Table 7)

tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON (default);
when OS = 1 tuning voltage is OFF (high impedance)

BS4 to BS1

PNP band switch buffers control bits; when BS

= 0 buffer n is OFF; when BS

= 1 buffer n

is ON

don't care

VOLTAGE APPLIED TO THE CE INPUT (SW = LOW)

MA1

MA0

0 V to 0.1V

CC1

Always valid

0.4V

CC1

to 0.6V

CC1

0.9V

CC1

to V

CC1

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

Table 6

Test bits

TSA5526; TSA5527

TSA5526A; TSA5527A

REMARKS

normal operation with automatic
charge-pump switch ON

automatic charge-pump switch OFF

normal operation with automatic
charge-pump switch OFF

automatic charge-pump switch ON

status at POR

charge-pump is OFF

charge-pump is sinking current

charge-pump is sourcing current

ref

is available at LOCK output

ref

is available at LOCK output

the ADC cannot be used
when test mode is active

div

is available at LOCK output

div

is available at LOCK output

the ADC cannot be used
when test mode is active

Table 7

Ratio select bits

EAD MODE

(R/W =

LOGIC

1); see Table 8

Data can be read from the device by setting the R/W bit to
logic 1. After the slave address has been recognized, the
device generates an acknowledge pulse and the first data
byte (status byte) is transferred on the SDA line (MSB
first). Data is valid on the SDA line during a HIGH level of
the SCL clock signal. A second data byte can be read from
the device if the microcontroller generates an
acknowledge on the SDA line (master acknowledge).
End of transmission will occur if no master acknowledge
occurs.

RSA

RSB

REFERENCE DIVIDER

640

1024

512

The device will then release the data line to allow the
microcontroller to generate a stop condition. The POR flag
is set to logic 1 at power-on. The flag is reset when an
end-of-data is detected by the device (end of a read
sequence). Control of the loop is made possible with the
in-lock flag (FL) which indicates when the loop is locked
(FL = logic 1).

The Automatic Charge-Pump Switch flag (ACPS) is LOW
when the automatic charge-pump switch mode is ON and
the loop is locked. In other conditions ACPS = logic 1.
When ACPS = logic 0, the charge-pump current is forced
to the LOW value.

A built-in ADC is available at pin 12 (I

C-bus only).

This converter can be used to apply AFC information to the
microcontroller from the IF section of the television.
The relationship between the bits A2 to A0 is given in
Table 9.

Table 8

Read data format

Notes

1. A = acknowledge.

2. POR = power-on reset flag (POR = logic 1 at power-on).

3. FL = in-lock flag (FL = logic 1 when the loop is locked).

4. ACPS = automatic charge-pump switch flag (active ACPS = logic 0; non-active ACPS = logic 1).

5. A2 to A0 = digital outputs of the 5-level ADC.

BYTE

MSB

DATA BYTE

LSB

SLAVE

ANSWER

Address Byte (ADB)

MA1

MA0

R/W = 1

(1)

Status Byte (SB)

POR

(2)

(3)

ACPS

(4)

(5)

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

Table 9

ADC levels

Note

1. Accuracy is

0.03V

CC1

3-wire bus mode (SW = open-circuit or V

CC1

);

see Figs 3, 4 and 5

During a HIGH level on the CE input, the data is clocked
into the data register at the HIGH-to-LOW transition of the
clock pulse. The first four bits control the band switch
buffers and are loaded into the internal band switch
register on the 5th rising edge of the clock pulse.
The frequency bits are loaded into the frequency register
at the HIGH-to-LOW transition of the chip enable line when
an 18-bit or 19-bit data word is transmitted.

At power-on the charge-pump current is set to 280

A, the

tuning voltage output is disabled (V

tune

= 33 V in

VOLTAGE APPLIED

AT ADC INPUT

(1)

0.6V

CC1

to V

CC1

0.45V

CC1

to 0.6V

CC1

0.3V

CC1

to 0.45V

CC1

0.15V

CC1

to 0.3V

CC1

0 to 0.15V

CC1

application; see Fig.12), the test bits T2, T1 and T0 are set
to the 0 0 1 state in the normal mode with ACPS OFF for
TSA55226; TSA5527 and ACPS ON for TSA5526A;
TSA5527A. RSB is set to logic 1 (TSA5526) or logic 0
(TSA5527). When an 18-bit data word is transmitted, the
most significant bit of the divider N14 is internally set to
logic 0 and bit RSA is set to logic 1. When a 19-bit data
word is transmitted, bit RSA is set to logic 0.

When a 27-bit word is transmitted, the frequency bits are
loaded into the frequency register on the 20th rising edge
of the clock pulse and the control bits at the HIGH-to-LOW
transition of the chip enable line. In this mode, the
reference divider is given by the RSA and RSB bits
(see Table 7). The test bits T2, T1 and T0, the
charge-pump bit CP, the ratio select bit RSB and the
OS bit can only be selected or changed with a 27-bit
transmission. They remain programmed if an 18-bit or a
19-bit transmission occurs. Only RSA is controlled by the
transmission length when the 18-bit or 19-bit format is
used.

A data word of less than 18 bits will not affect the
frequency register of the device. The definition of the bits
is unchanged compared to the I

C-bus mode.

The power-on detection threshold voltage V

POR

is fixed to

CC1

= 2 V at room temperature. Below this threshold, the

device is reset to the power-on state previously described.

Fig.3 Normal mode; 18-bit data format (RSA = 1).

For TSA5526 bit RSB = logic 1 at power-on; the reference divider is 512 or 1024.

For TSA5527 bit RSB = logic 0 at power-on; the reference divider is 640.

For TSA5526 and TSA5527 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB
remains as programmed with the 27-bit data word.

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. Short-circuit between V

CC1

and V

CC2

is allowed provided the voltage applied to V

CC2

is less than the 6 V maximum

rating at V

CC1

THERMAL CHARACTERISTICS

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling bipolar devices. Every pin withstands the ESD test in
accordance with

"MIL-STD-883C" category B (2000 V). Every pin withstands the ESD test in accordance with Philips

Semiconductors Machine Model 0

, 200 pF (200 V).

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

CC1

supply voltage; +5 V (pin 3)

0.3

+6.0

CC2

band switch supply voltage; +12 V (pin 4)

0.3

+16

i(RF)

prescaler input voltage (pin 1)

0.3

CC1

o(BSn)

band switch buffers output voltage (pins 5 to 8)

0.3

CC2

o(BSn)

band switch buffers output current

+50

o(CP)

charge-pump output voltage (pin 9)

0.3

CC1

o(tune)

output tuning voltage (pin 10)

0.3

+35

i(SW)

input switching voltage (pin 11)

0.3

CC1

o(LOCK)

lock output voltage (pin 12)

0.3

CC1

i(SCL)

serial clock input voltage (pin 13)

0.3

+6.0

i/o(SDA)

serial data input/output voltage (pin 14)

0.3

+6.0

o(SDA)

serial data output current

+10

i(CE)

chip enable input voltage (pin 15)

0.3

+6.0

i(xtal)

crystal oscillator input voltage (pin 16)

0.3

CC1

stg

storage temperature

+150

maximum junction temperature

+150

short-circuit time; every pin except pin 4 to pin 3 and every pin to pin 2; note 1

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

SO16

110

K/W

SSOP16

142

K/W

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

CHARACTERISTICS
V

CC1

= 4.5 to 5.5 V; V

CC2

= V

CC1

to 13.2 V; T

amb

20 to +85

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

CC1

supply voltage

4.5

5.5

CC2

band switch buffers supply voltage

CC1

13.5

CC1

supply current

at power-on

CC2

band switch buffers supply current

at power-on

0.5

1.0

one band switch buffer is
ON; I

source

= 40 mA

two band switch buffers are
ON;
I

source

= 40 mA + 5 mA

(any combination)

POR

supply voltage below which POR is active

1.5

2.0

RF input frequency

1300

MHz

divider ratio

15-bit frequency word

256

32767

14-bit frequency word

256

16383

xtal

crystal oscillator input frequency

xtal

= 25 to 300

3.2

4.48

MHz

xtal

crystal oscillator input impedance
(absolute value)

= 4 MHz

600

1 200

Prescaler (see Figs 6 and 7)

i(RF)

RF input level

= 80 to 150 MHz

dBm

= 150 to 1000 MHz

dBm

= 1000 to 1300 MHz

dBm

i(RF)

input impedance

see Fig.8

PNP band switch buffers outputs (pins 5 to 8)

output leakage current

CC2

= 13.5 V;

= 0 V

o(sat)

output saturation voltage

source

= 40 mA;

o(sat)

= V

CC2

0.2

0.4

LOCK output (PNP collector output) 3 wire bus mode (pin 12)

o(ool)

output current when out-of-lock

CC1

= 5.5 V; V

= 5.5 V

100

osat(ool)

output saturation voltage when
out-of-lock

source

= 200

o(sat)

= V

CC1

0.4

0.8

o(LOCK)

lock output voltage

0.01

0.4

ADC input (I

C-bus mode) pin 12

i(ADC)

ADC input voltage

see Table 9

CC1

IH(ADC)

HIGH level input current

ADC

= V

CC1

IL(ADC)

LOW level input current

ADC

= 0 V

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

SW input (bus format switch)

LOW level input voltage

1.5

HIGH level input voltage

CC1

HIGH level input current

= V

CC1

LOW level input current

= 0 V

100

CE input (chip enable/address selection)

LOW level input voltage

1.5

HIGH level input voltage

5.5

HIGH level input current

= 5.5 V

LOW level input current

= 0 V

SCL and SDA inputs

LOW level input voltage

1.5

HIGH level input voltage

3.0

5.5

HIGH level input current

BUS

= 5.5 V; V

CC1

= 0 V

BUS

= 5.5 V; V

CC1

= 5.5 V

LOW level input current

BUS

= 1.5 V; V

CC1

= 0 V

BUS

= 0 V; V

CC1

= 5.5 V

clk

clock frequency

100

400

kHz

SDA outputs (I

C-bus mode)

output leakage current

SDA

= 5.5 V

output voltage

sink

= 3 mA

0.4

Charge-pump output CP

ICPH

HIGH charge-pump current

CP = 1

280

ICPL

LOW charge-pump current

CP = 0

output voltage

in-lock; T

amb

= 25

1.95

LI(off)

off-state leakage current

T2 = 0; T1 = 1

0.5

+15

Tuning voltage output V

tune

LO(off)

leakage current when switched-off

OS = 1; V

tune

= 33 V

output voltage when the loop is closed

OS = 0; T2 = 0; T1 = 0;
T0 = 1; R

= 27 k

;

tune

= 33 V

0.2

32.7

3-wire bus timing (see Figs 6 and 7)

HIGH

clock high time

SU;DAT

data set-up time

HD;DAT

data hold time

SU;ENSCL

enable to clock set-up time

HD;ENDAT

enable to data hold time

enable between two transmissions

HD;ENSCL

enable to clock active edge hold time

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

APPLICATION INFORMATION

Tuning amplifier

The tuning amplifier is capable of driving the varicap
voltage without an external transistor. The tuning voltage
output must be connected to an external load of 27 k

which is connected to the tuning voltage supply rail.
Figs 11 and 12 show a possible loop filter. The component
values depend on the oscillator characteristics and the
selected reference frequency.

Crystal oscillator

The crystal oscillator uses a 4 MHz crystal connected in
series with an 18 pF capacitor thereby operating in the
series resonance mode. Connecting the oscillator to the
supply voltage is preferred but it can, however, also be
connected to ground.

Examples of I

C-bus sequences (SW = LOW)

Tables 10 to 14 show the various sequences where f

osc

= 100 MHz, BS4 = ON, I

= 280

A, N = 512, f

xtal

= 4 MHz,

S = START, A = acknowledge and P = STOP. The sequence is as follows:
START + address byte + divider byte 1 + divider byte 2 + control byte + band switch byte + STOP.

For the complete sequence see Table 10 (sequence 1) or Table 11 (sequence 2).

Table 10 Complete sequence 1

Table 11 Complete sequence 2

Table 12 Divider bytes only sequence

Table 13 Control and band switch bytes only sequence

Table 14 Control byte only sequence

Other sequences are not allowed in the write mode.

Table 15 One status byte acquisition

Notes

1. XX = the read status byte.

2. X = no acknowledge from the master means end of sequence.

(1)

(2)

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

Table 16 Two status byte acquisition

Notes

1. XX = the read status byte.

2. X = no acknowledge from the master means end of sequence.

Other I

C-bus addresses may be selected by applying an appropriate voltage to the CE input.

Examples of 3-wire bus sequences (TSA5526; SW = OPEN)

Table 17 18-bit sequence (f

osc

= 800 MHz, BS4 = ON)

The reference divider is automatically set to 512 unless RSB has been programmed to 0 during a 27-bit sequence
(see Table 19).

Table 18 19-bit sequence (f

osc

= 650 MHz, BS3 = ON)

The reference divider is automatically set to 1024 unless RSB has been programmed to 0 during a 27-bit sequence
(see Table 19).

Table 19 27-bit sequence (f

osc

= 750 MHz, BS1 = ON, N = 640, I

= 60

A, no test function)

Table 20 19-bit sequence

This sequence will program f

osc

to 600 MHz in 50 kHz steps. I

remains at 60

Table 21 18-bit sequence

This sequence will program f

osc

to 600 MHz in 50 kHz steps. I

remains at 60

Table 22 27-bit sequence (f

osc

= 650 MHz, BS1 = ON)

This sequence sets RSA to 0, RSB to 1 and CP to 1. After this sequence I

= 280

A, N = 1024 (19-bit transmission)

and N = 512 (18-bit transmission), RSB = 1.

(1)

(2)

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

PACKAGE OUTLINES

detail X

(A )

pin 1 index

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

1.75

0.25
0.10

1.45
1.25

0.25

0.49
0.36

0.25
0.19

10.0

9.8

4.0
3.8

1.27

6.2
5.8

0.7
0.6

0.7
0.3

8
0

0.25

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.0
0.4

SOT109-1

91-08-13
95-01-23

076E07S

MS-012AC

0.069

0.0098
0.0039

0.057
0.049

0.01

0.019
0.014

0.0098
0.0075

0.39
0.38

0.16
0.15

0.050

1.05

0.041

0.24
0.23

0.028
0.020

0.028
0.012

0.01

0.25

0.01

0.004

0.039
0.016

2.5

5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

Wave soldering

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

The longitudinal axis of the package footprint must be
parallel to the solder flow.

The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1996 Sep 24

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled
TV synthesizers

TSA5526; TSA5527

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

C components conveys a license under the Philips' I

C patent to use the

components in the I

C system provided the system conforms to the I

C specification defined by

Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors a worldwide company

SCA51

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands

537021/50/02/pp28

Date of release: 1996 Sep 24

Document order number:

9397 750 01258

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TSA5526

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TSA5526