2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

FEATURES

Dual postamplifier

Single 3.3 V power supply

Wideband operation from 50 kHz to 2.5 GHz (typical
value)

Fully differential

Channels are delay matched

On-chip DC-offset compensations without external
capacitor

Interfacing with positive or negative supplied logic

Switching possibility between channels

Positive Emitter Coupled Logic (PECL) or Current-Mode
Logic (CML) compatible data outputs adjustable from
200 to 800 mV (p-p) single-ended

Power-down capability for unused outputs and detectors

Rise and fall times 80 ps (typical value)

Possibility to invert the output of each channel
separately

Input level-detection circuits for Received Signal
Strength Indicator (RSSI) or Loss Of Signal (LOS)
detection, programmable from 0.4 to 400 mV (p-p)
single-ended, with open-drain comparator output for
direct interfacing with positive or negative logic

Reference voltage for output level and LOS adjustment

Automatic strongest input signal switch possibility
(TZA3019 version B)

HTQFP32 or HBCC32 plastic package with exposed
pad.

APPLICATIONS

Postamplifier for Synchronous Digital Hierarchy and
Synchronous Optical Network (SDH/SONET)
transponder

SDH/SONET wavelength converter

Crosspoint or channel switch

PECL driver

Fibre channel arbitrated loop

Protection ring

Monitoring

Signal level detectors

Swing converter CML 200 mV (p-p) to
PECL 800 mV (p-p)

Port bypass circuit

2.5 GHz clock amplification.

GENERAL DESCRIPTION

The TZA3019 is a low gain postamplifier multiplexer with a
dual RSSI and/or LOS detector that is designed for use in
critical signal path control applications, such as
loop-through, redundant channel switching or Wavelength
Division Multiplexing (WDM). The signal path is
unregistered, so no clock is required for the data inputs.
The signal path is fully differential and delay matched. It is
capable of operating from 50 kHz to 2.5 GHz.

The TZA3019 HTQFP32 and HBCC32 packages can be
delivered in three versions:

TZA3019AHT and TZA3019AV with two RSSI signals

TZA3019BHT and TZA3019BV with one RSSI and one
LOS signal

TZA3019CHT and TZA3019CV with two LOS signals.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TZA3019AHT

HTQFP32

plastic, heatsink thin quad flat package; 32 leads; body 5

1 mm

SOT547-2

TZA3019BHT

HTQFP32

plastic, heatsink thin quad flat package; 32 leads; body 5

1 mm

SOT547-2

TZA3019CHT

HTQFP32

plastic, heatsink thin quad flat package; 32 leads; body 5

1 mm

SOT547-2

TZA3019AV

HBCC32

plastic, heatsink bottom chip carrier; 32 terminals; body 5

0.65 mm

SOT560-1

TZA3019BV

HBCC32

plastic, heatsink bottom chip carrier; 32 terminals; body 5

0.65 mm

SOT560-1

TZA3019CV

HBCC32

plastic, heatsink bottom chip carrier; 32 terminals; body 5

0.65 mm

SOT560-1

TZA3019U

bare die; 2.22

2.22

0.28 mm

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

PINNING

SYMBOL

PIN

PAD

TYPE

(2)

DESCRIPTION

TZA3019xHT/xV

(1)

GND1A

ground for input 1 and LOS1 circuits

IN1

differential circuit 1 input; complimentary to pin IN1Q; DC bias level
is set internally at approximately

0.33 V

IN1Q

differential circuit 1 input; complimentary to pin IN1; DC bias level is
set internally at approximately

0.33 V

GND1A

ground for input 1 and LOS1 circuits

n.c

not connected

n.c

not connected

GND2A

ground for input 2 and LOS2 circuits

IN2

differential circuit 2 input; complimentary to pin IN2Q; DC bias level
is set internally at approximately

0.33 V

IN2Q

differential circuit 2 input; complimentary to pin IN2; DC bias level is
set internally at approximately

0.33 V

GND2A

ground for input 2 and LOS2 circuits

EE2A

negative supply voltage for input 2 and LOS2 circuits

LOSTH1

Input for level detector programming of input 1 circuit; threshold
level is set by connecting external resistors between pins
GND1A and V

ref

. When forced to V

EE2A

or not connected, the

LOS1 circuit will be switched off.

LOSTH2

Input for level detector programming of input 2 circuit; threshold
level is set by connecting external resistors between pins
GND2A and V

ref

. When forced to V

EE2A

or not connected, the

LOS2 circuit will be switched off.

n.c

not connected

LEVEL1

Input for programming output level of output 1 circuit; output level is
set by connecting external resistors between pins GND1A and V

ref

When forced to GND1A or not connected, pins OUT1 and OUT1Q
will be switched off.

LEVEL2

Input for programming output level of output 2 circuit; output level is
set by connecting external resistors between pins GND2A and V

ref

When forced to GND2A or not connected, pins OUT2 and OUT2Q
will be switched off.

ref

reference voltage for level circuit and LOS threshold programming;
typical value is

1.6 V; no external capacitor allowed

n.c

TEST

for test purposes only; to be left open-circuit in the application

EE2B

negative supply voltage for output 2 circuit

GND2B

ground for output 2 circuit

OUT2Q

PECL or CML compatible differential circuit 2 output;
complimentary to pin OUT2

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

Notes

1. The `x' in TZA3019xHT/xV represents versions A, B and C.

2. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output.

OUT2

PECL or CML compatible differential circuit 2 output;
complimentary to pin OUT2Q

GND2B

ground for output 2 circuit

n.c

not connected

n.c

not connected

GND1B

ground for output 1 circuit

OUT1Q

PECL or CML compatible differential circuit 1 output;
complimentary to pin OUT1

OUT1

PECL or CML compatible differential circuit 1 output;
complimentary to pin OUT1Q

GND1B

ground for output 1 circuit

EE1B

negative supply voltage for output 1 circuit

RSSI2

output of received signal strength indicator of detector

LOS2

O-DRN output loss of signal detector 2; detection of input 2 signal; direct

drive of positive or negative supplied logic via internal 5 k

resistor

RSSI1

output of received signal strength indicator of detector

LOS1

O-DRN output loss of signal detector 2; detection of input 2 signal; direct

drive of positive or negative supplied logic via internal 5 k

resistor

INV2

TTL

input to invert the signal of pins OUT2 and OUT2Q; directly positive
(inverted) or negative supplied logic driven

INV1

TTL

input to invert the signal of pins OUT1 and OUT1Q; directly of
positive (inverted) or negative supplied logic driven

TTL

input selector output 2 circuit; directly positive (inverted) or negative
supplied logic driven

TTL

input selector output 1 circuit; directly positive (inverted) or negative
supplied logic driven

EE1A

negative supply voltage for input 1 and LOS1 circuits

EEP

pad

negative supply voltage pad (exposed die pad)

SYMBOL

PIN

PAD

TYPE

(2)

DESCRIPTION

TZA3019xHT/xV

(1)

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

FUNCTIONAL DESCRIPTION

The TZA3019 is a dual postamplifier with multiplexer and
loss of signal detection see Figs 1, 2 and 3. The RF path
starts with the multiplexer, which connects an amplifier to
one of the two inputs. It is possible to invert the output for
easy layout of the Printed-Circuit Board (PCB). The signal
is amplified to a certain level. To guarantee this level with
minimum distortion over the temperature range and level
range, an active control part is added. The offset
compensation circuit following the inverter minimizes the
offset.

The Received Signal Strength Indicator (RSSI) or the Loss
Of Signal (LOS) detection uses a 7-stage `successive
detection' circuit. It provides a logarithmic output. The LOS
is followed by a comparator with a programmable
threshold. The input signal level-detection is implemented
to check if the input signal voltage is above the user
programmed level. This can insure that data will only be
transmitted when the input signal-to-noise ratio is sufficient
for low bit error rate system operation. A second
offset compensation circuit minimizes the offset of the
logarithmic amplifier.

RF input circuit

The input circuit contains internal 50

resistors

decoupled to ground via an internal common mode 12 pF
capacitor (see Fig.6).

The input pins are DC-biased at approximately

0.33 V by

an internal reference generator. The TZA3019 can be
DC-coupled, but AC-coupling is preferred. In case of
DC-coupling, the driving source must operate within the
allowable input range (

1.0 to +0.3 V). A DC-offset voltage

of more than a few millivolts should be avoided, since the
internal DC-offset compensation circuit has a limited
correction range. When AC-coupling is used, if no
DC-compatibility is required, the values of the coupling
capacitors must be large enough to pass the lowest input
frequency of interest. Capacitor tolerance and resistor
variation must be included for an accurate calculation.
Do not use signal frequencies around the low cut-off
circuit frequencies (f

3dB(l)

= 50 kHz for the postamplifiers

and f

3dB(l)

= 1 MHz for the LOS circuits).

RF output circuit

Matching the main amplifier outputs (see Fig.7) is not
mandatory. In most applications, the transmission line
receiving end will be properly matched, while very little
reflections occur.

Matching the transmitting end to absorb reflections is only
recommended for very sensitive applications.

In such cases, pull-up resistors of 100

should be

connected as close as possible to the IC from
pins OUT1 and OUT1Q, and pins OUT2 and OUT2Q to
V

EE1B

and V

EE2B

respectively. These matching resistors

are not needed in most applications.

Postamplifier level adjustment

The postamplifier boosts the signal up to PECL levels. The
output can be either CML- or PECL-level compatible,
adjusted by means of the voltage on pins LEVEL1
and LEVEL2. The DC voltages of pins OUT1 and OUT1Q,
and pins OUT2 and OUT2Q match with the DC-levels
on pins LEVEL1 and LEVEL2, respectively. Due to the
receiving end 50

load resistance, it means that at the

same level of V

o(p-p)

, V

LEVEL1

and V

LEVEL2

with

AC-coupling are not equal to V

LEVEL1

and V

LEVEL2

with

DC-coupling (see Figs 7 and 8).

The postamplifier is in power-down state when pin
LEVEL1 or LEVEL2 is connected to ground or not
connected (see Fig.8).

Postamplifier DC offset cancellation loop

Offset control loops connected between the inputs of the
buffers A1A and A2A and the outputs of the amplifiers A1B
and A2B (see Figs 1, 2 and 3) will keep the input of both
buffers at their toggle point during the absence of an input
signal. The active offset compensation circuit is integrated,
so no external capacitor is required. The loop time
constant determines the lower cut-off frequency of the
amplifier chain. The cut-off frequency of the offset
compensations is fixed internally at approximately 5 kHz.

handbook, halfpage

MGS555

420

12 pF

GND1A,
GND2A

IN1, IN2

IN1Q, IN2Q

VEE1A,
VEE2A

Fig.6 RF input circuit.

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

handbook, full pagewidth

100

1000

200

MGS557

400

600

800

Vlevel (% of Vref)

Vo(se)(p-p)

(mV)

DC-coupled

AC-coupled

Fig.8 Output signal as a function of V

level

TTL logic input of selector and inverter

The logic levels are differently defined for positive or
negative logic (see Fig.9). It should be noted that positive
logic levels are inverted if a negative supply voltage is
used.

Outputs as a function of switch input pins S1, S2,
INV1 and INV2

See Tables 1, 2, 3 and 4.

The default values for the switch input pins S1, S2, INV1
and INV2 if not connected, is zero.

Table 1

OUT1 and OUT1Q as function of input S1

Table 2

OUT2 and OUT2Q as function of input S2

Table 3

OUT1 and OUT1Q as function of INV1

Table 4

OUT2 and OUT2Q as function of INV2

OUT1

OUT1Q

IN1

IN1Q

IN2

IN2Q

OUT2

OUT2Q

IN2

IN2Q

IN1

IN1Q

INV1

OUT1

OUT1Q

IN1 or IN2

IN1Q or IN2Q

IN1 or IN2

INV2

OUT2

OUT2Q

IN1 or IN2

IN1Q or IN2Q

IN1 or IN2

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

RSSI and LOS detection

The TZA3019 allows AC-signal level detection. This can
prevent the outputs from reacting to noise during the
absence of a valid input signal, and can insure that data
only will be transmitted when the signal-to-noise ratio of
the input signal is sufficient to insure low bit error rate
system operation.

The RSSI detection circuit uses seven limiting amplifiers in
a `successive detection' topology to closely approximate
logarithmic response over a total range of 70 dB. The
detectors provide full-wave rectification of the AC signals
presented at each previous amplifier stage. Their outputs
are current drivers. Each cell incorporates a low-pass filter,
being the first step in recovering the average value of the
demodulated signal of the input frequency. The summed
detector output currents are converted to a voltage by an
internal load resistor. This voltage is buffered and
available in the A and B versions of the TZA3019. When
V

RSSI

is used V

LOSTH

must be connected to GND to

prevent the LOS comparator from switching to the standby
mode. The LOS comparator detects an input signal above
a fixed threshold, resulting in a LOW-level at the LOS
circuit output.The threshold level is determined by the
voltage on pins LOSTH1 or LOSTH2 (see Fig.10). A filter
with a time constant of 1

s nominal is included to prevent

noise spikes from triggering the level detector.

The comparator (with internal 3 dB hysteresis) drives an
open-drain circuit with an internal resistor (5 k

) for direct

interfacing to positive or negative logic (see Fig.11). Only
available in the B and C versions of the TZA3019.

The response is independent of the sign of the input signal
because of the particular way the circuit has been built.
This is part of the demodulating nature of the detector,
which results in an alternating input voltage being
transformed to a rectified and filtered quasi DC-output
signal. For the TZA3019 the logarithmic voltage slope is

= 1/13 dB/mV and is essentially temperature and supply

independent through four feedback loops in the reference
circuit. The internal LOS detector output voltage is based
on V

ref

. The demodulator characteristic depends on the

waveform and the response depends roughly on the input
signal RMS value. This influences high frequencies, a
square wave input of 2.4 GHz (LOS circuit bandwidth
of 2.4 GHz) offsets the intercept voltage by 20%. V

LOSTH

can be calculated using the following formulae:

(1)

where S = sensitivity.

Example: a 200 mV (p-p) single-ended 1.2 GB/s PRBS
signal has an RSSI from 1003 mV.

A full understanding of the offset control loop is useful. The
primary purpose of the loop is to extend the lower end of
the dynamic range in any case where the offset voltage of
the first stage might be high enough to cause later stages
to prematurely enter limiting, caused by the high DC-gain
of the amplifier system. The offset is automatically and
continuously compensated via a feedback path from the
last stage. An offset at the output of the logarithmic
converter is equivalent to a change of amplitude at the
input. Consequently, with DC-coupling, signal absence,
either LOW-level or HIGH-level is detected as a full signal,
only signals with an average value equal to zero give zero
output.

Version B can be used for an auto function, which switches
the strongest input signal to output 1 and the weakest to
output 2. To achieve this output V

RSSI2

must be used as

the reference voltage for input V

LOSTH

. Then the output

LOS1 can switch S1 and S2.

LOSTH

RSSI

20log

Vi 18

(

)

handbook, halfpage

LOS1,
LOS2

LOW-level

LOS1,
LOS2

HIGH-level

0.8

0.64

0.48

0.32

0.96

1.12

MGS564

VLOSTH1, VLOSTH2 (% of Vref)

VRSSI1, VRSSI2 (V)

Vi(se)(p-p)

(mV)

(1)

(3)

(2)

0.16

Fig.10 Loss of signal assert level.

(1) PRBS pattern input signal with a frequency <1 GHz.

(2) Linearity error typically 0.5 dB.

(3)

= 1/12.5 dB/mV.

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

handbook, halfpage

MGS561

VEE

ILOS

GND

LOS1,
LOS2

GND1A,
GND2A

5 k

56 k

TZA3019

handbook, halfpage

MGS563

GND

56 k

VCC

ILOS

LOS1,
LOS2

GND1A,
GND2A

5 k

TZA3019

Fig.11 Loss of signal outputs, pins LOS1 and LOS2.

< 7 V.

b. Negative supply and positive logic.

c. Positive supply and positive logic.

a. Negative supply and negative logic.

handbook, halfpage

MGS562

VCC

5.6 k

VEE

ILOS

GND

LOS1,
LOS2

GND1A,
GND2A

5 k

TZA3019

Supply current

For the supply currents I

EE1B

and I

EE2B

, see Fig.12.

Using a positive supply voltage

Although the TZA3019 has been designed to use a single

3.3 V supply voltage (see Fig.13), a +3.3 V supply

(see Fig.14) can also be used. However, care should be
taken with respect to RF transmission lines. The on-chip
signals refer to the various ground pins as being positive
supply pins in a +3.3 V application. The external
transmission lines will most likely be referred to the
pins V

EE1A

, V

EE2A

, V

EE1B

and V

EE2B

, being the system

ground. The RF signals will change from one reference
plane to another when interfacing the RF inputs and
outputs. A positive supply application is very vulnerable to
interference with respect to this point. For a successful
+3.3 V application, special care should be taken when
designing the PCB layout in order to reduce the influence
of interference and to keep the positive supply voltage as
clean as possible.

MGS566

0.5

Vo(se)(p-p) (V)

0.8

0.2

IEE1B,

IEE2B

(mA)

(1)

(1) I

EE1B

and I

EE2B

at 25

Fig.12 Supply current as a function of output

voltage

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).

THERMAL CHARACTERISTICS

Note

1. JEDEC standard.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

negative supply voltage

5.5

+0.5

DC voltage

pins IN1, IN1Q, IN2, IN2Q, LOSTH1, LOSTH2, LEVEL1, LEVEL2,
V

ref

, TEST, OUT2Q, OUT2, OUT1Q, OUT1, V

EEP

, GND1A,

GND2A, GND1B and GND2B

0.5

pins LOS1, LOS2, INV1, INV2, S1 and S2

0.5

+ 7

DC current

pins IN1, IN1Q, IN2 and IN2Q

+20

pins LOSTH1, LOSTH2, LEVEL1 and LEVEL2

pins V

ref,

TEST, LOS1 and LOS2

pins OUT1, OUT1Q, OUT2 and OUT2Q

+30

pins INV1, INV2, S1 and S2

tot

total power dissipation

1.2

stg

storage temperature

+150

junction temperature

150

amb

ambient temperature

+85

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-s)

thermal resistance from junction to
solder point (exposed die pad); note 1

K/W

th(j-a)

thermal resistance from junction to
ambient; note 1

1s2p multi-layer test board

K/W

th(s-a)

thermal resistance from solder point to
ambient (exposed die pad); note 1

1s2p multi-layer test board

K/W

th(s-a)(req)

required thermal resistance from
solder point to ambient

LOS circuits switched on

= 200 mV (p-p) single-ended;

both output circuits

K/W

= 800 mV (p-p) single-ended;

both output circuits

K/W

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

CHARACTERISTICS
Typical values at T

amb

= 25

C and V

3.3 V; minimum and maximum values are valid over the entire ambient

temperature range and supply voltage range; all voltages referenced to ground; unless otherwise specified; note 1.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

UPPLY PINS

EE1A

, V

EE1B

, V

EE2A

AND

EE2B

negative supply voltage

3.13

3.3

3.47

EE1A

EE2A

negative supply current

LOS circuit power-down

LOS circuit switched on

EE1B

EE2B

negative supply current

amplifier power-down

= 200 mV (p-p)

single-ended; one output
circuit

= 800 mV (p-p)

single-ended; one output
circuit

tot

total power dissipation

power-down

100

200

300

both LOS circuits switched on

= 200 mV (p-p)

single-ended; both output
circuits

220

380

555

= 800 mV (p-p)

single-ended; both output
circuits

450

660

925

temperature coefficient

LOS circuit switched on; I

EE1A

;

EE2A

= 800 mV (p-p)

single-ended; I

EE1A

; I

EE2A

junction temperature

+125

amb

ambient temperature

+25

+85

Inputs multiplexer and loss of signal detector

PECL

CML

INPUT PINS

IN1, IN1Q, IN2

AND

IN2Q

i(p-p)

input voltage swing
(peak-to-peak value)

single-ended; note 2

500

i(bias)

DC input bias voltage

0.28

0.33

0.4

DC and AC input window
voltage

note 3

1.0

+0.3

input resistance

single-ended

input capacitance

single-ended; note 3

0.6

0.8

1.2

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

Postamplifier

MPLIFIERS

A1A, A1B, A2A

AND

A2B

small signal voltage gain

= 200 mV (p-p)

single-ended; note 4

= 800 mV (p-p)

single-ended; note 4

signal path data rate

notes 5 and 9

2500

Mbits/s

3dB(l)

low

3 dB cut-off frequency

DC compensation

note 3

kHz

3dB(h)

high

3 dB cut-off frequency

2.0

GHz

propagation delay

note 3

150

200

250

propagation delay
difference

at the same signal levels;
note 3

total jitter

20 bits of the 28.5kbits
pattern; notes 3 and 6

crosstalk

crosstalk of IC only

110

PECL

CML

OUTPUT PINS

OUT1, OUT1Q, OUT2

AND

OUT2Q

o(se)(p-p)

single-ended output voltage
(peak-to-peak value)

load

200

800

temperature coefficient
output level

-1

mV/K

rise time

20% to 80%; note 5

fall time

80% to 20%; note 5

output resistance

single-ended

100

130

output capacitance

single-ended; note 3

0.6

0.8

1.2

EVEL CONTROL INPUT PINS

LEVEL1

AND

LEVEL2

input voltage

ref

input resistance

measured to
GND1A or GND2A

150

350

600

Multiplexer and inverter switch

PECL

CML

INPUT PINS

IN1, IN1Q, IN2

AND

IN2Q

OS(red)

input offset reduction

= 200 mV (p-p)

single-ended; note 7

= 800 mV (p-p)

single-ended; note 7

io(cor)

input offset voltage
correction range

peak-to-peak value
single-ended

+10

n(i)(eq)(rms)

equivalent input noise
voltage (RMS value)

= 800 mV (p-p)

single-ended; note 3

170

noise factor

note 3

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

WITCH CIRCUIT

assert time

multiplexer and inverter

100

200

de-assert time

multiplexer and inverter

160

TTL

INPUT PINS

S1, S2, INV1

AND

INV2

LOW-level input voltage

positive logic

2.0

+ 7.3 V

negative logic

0.3

2.5

HIGH-level input voltage

negative logic

1.3

+0.3

positive logic

0.3

+0.8

input resistance

measured to V

EE1A

or V

EE2A

100

180

400

input current

+10

Received Signal Strength Indicator and Loss Of Signal detector

RSSI

AND

LOS

CIRCUIT

i(se)(p-p)

single-ended input voltage
swing (peak-to-peak value)

0.4

400

dynamic range

LOS

LOS sensitivity

50 MHz, square; note 8

12.5

mV/dB

620 MHz, square; note 8

10.7

11.9

mV/dB

1.2 GHz, square; note 8

11.1

12.2

mV/dB

100 MB/s PRBS (2

1);

note 8

11.2

12.7

14.2

mV/dB

1.2 GB/s PRBS (2

1);

note 8

10.9

12.4

13.9

mV/dB

100 GB/s PRBS (2

- 1

);

note 8

10.7

11.9

mV/dB

sens

temperature coefficient
sensitivity

V/dbK

linearity error

see Fig.10

0.5

OS(red)

input offset reduction

notes 3 and 7

io(cor)

input offset voltage
correction range

peak-to-peak value
single-ended

3dB(l)

low

3 dB cut-off frequency

0.5

MHz

3dB(h)

high

3 dB cut-off frequency note 8

1.5

2.5

GHz

LOS

CIRCUIT

hys

LOS

LOS hysteresis

input signal waveform
dependency

2.0

3.0

4.0

assert time

note 3

de-assert time

note 3

NPUT PINS

LOSTH1

AND

LOSTH2

input voltage

input resistance

measured to V

EE1A

or V

EE2A

150

350

600

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

Notes

1. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true

differential excitation).

2. Minimum signal with limiting output.

3. Guaranteed by design.

4. G

5. Based on

3dB cut-off frequency.

6. V

= 100 mV (p-p) single-ended and V

= 200 mV (p-p) single-ended.

7. Input offset reduction =

8. Sensitivity depends on the waveform and is therefore a function of

3 dB cut-off frequency see equation (1).

9. Low limit can go as low as DC if input signal overrides input offset voltage correction range.

UTPUT PINS

LOS1

AND

LOS2

output voltage

3.5

o(sink)

output sink current

output resistance

internal output series
resistance

3.5

6.5

UTPUT PINS

RSSI1

AND

RSSI2

output voltage

output current

Band gap reference circuit

UTPUT PIN

REF

ref

reference voltage

1.45

1.6

1.8

ext

allowed external
capacitance

o(sink)

output sink current

500

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

------

-----------

APPLICATION INFORMATION

RF input and output connections

Striplines, or microstrips, with an odd mode characteristic
impedance of Z

= 50

must be used for the differential

RF connections on the PCB. This applies to both the signal
inputs and the signal outputs. The two lines in each pair
should have the same length.

Grounding and power supply decoupling

The ground connection on the PCB needs to be a large
copper filled area connected to a common ground plane
with an inductance as low as possible.

All V

pins (one at each corner and the exposed die pad)

need to be connected to a common supply plane with an
inductance as low as possible. This plane should be
decoupled to ground. To avoid high frequency resonance,
multiple bypass capacitors should not be mounted at the
same location. To minimize low frequency switching noise
in the vicinity of the TZA3019, the power supply line should
be filtered once using a beaded capacitor circuit with a low
cut-off frequency (see Figs 13 and 14).

The V

connection on the PCB also needs to be a large

copper area to improve heat transfer to the PCB and thus
support IC cooling.

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

handbook, full pagewidth

,,,

IN1

IN1Q

GND1A

IN2

IN2Q

GND2A

OUT2

OUT2Q

GND2B

GND1B

GND2B

OUT1

OUT1Q

GND1B

LOS2

LEVEL2

EE1A

EE2A

LOSTH1

INV2

INV1

LOSTH2

EE1B

EE2B

LOS1

0603

5 mm

0603

LEVEL1

ref

TEST

0603

signal

/
V

EEP

GND

Boundary of 200 mm

area

To central
VEE decoupling

MGS567

HTQFP

Fig.13 PCB layout for negative supply voltage.

In order to enable heat flow out of the package, the following measures have to be taken:

(1) Solder the 3

3 mm

die pad to a plane with maximum size.

(2) Add a plane with minimum 200 mm

in an inner layer, surrounded by ground layers.

(3) Use maximum amount of vias to connect two planes.

(4) Use minimum of openings in heat transport area between hot plane and ground planes.

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

handbook, full pagewidth

IN1

IN1Q

GND1A

IN2

IN2Q

GND2A

OUT2

OUT2Q

GND2B

GND1B

GND2B

OUT1

OUT1Q

GND1B

LOS2

LEVEL2

EE1A

EE2A

LOSTH1

INV2

INV1

LOSTH2

EE1B

EE2B

LOS1

0603

HTQFP

0603

5 mm

0603

LEVEL1

ref

TEST

0603

signal

/
V

EEP

GND

Boundary of 200 mm

area

To central
VEE decoupling

MGS568

Fig.14 PCB layout for positive supply voltage.

In order to enable heat flow out of the package, the following measures have to be taken:

(1) Solder the 3

3 mm

die pad to a plane with maximum size.

(2) Add a plane with minimum 200 mm

in an inner layer, surrounded by ground layers.

(3) Use maximum amount of vias to connect two planes.

(4) Use minimum of openings in heat transport area between hot plane and ground planes.

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

BONDING PAD LOCATIONS

Note

1. All x and y coordinates represent the position of the

centre of the pad in

m with respect to the centre of the

die (see Fig.15)

SYMBOL

PAD

COORDINATES

(1)

GND1A

928

+710

IN1

928

+553

IN1Q

928

+396

GND1A

928

+239

n.c.

928

+81

n.c.

928

GND2A

928

239

IN2

928

396

IN2Q

928

553

GND2A

928

710

EE2A

707

928

LOSTH1

550

928

LOSTH2

393

928

n.c.

236

928

LEVEL1

928

LEVEL2

+79

928

VREF

+236

928

n.c.

+393

928

TEST

+550

928

EE2B

+707

928

GND2B

+928

710

OUT2Q

+928

553

OUT2

+928

396

GND2B

+928

239

n.c.

+928

n.c.

+928

+81

GND1B

+928

+239

OUT1Q

+928

+396

OUT1

+928

+553

GND1B

+928

+710

EE1B

+707

+928

RSSI2

+550

+928

LOS2

+393

+928

RSSI1

+236

+928

LOS1

+79

+928

INV2

+928

INV1

236

+928

-393

+928

-550

+928

EE1A

707

+928

SYMBOL

PAD

COORDINATES

(1)

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

2000 Apr 10

Philips Semiconductors

Preliminary specification

2.5 Gbits/s dual postamplifier with level
detectors and 2

2 switch

TZA3019

DATA SHEET STATUS

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DATA SHEET STATUS

PRODUCT

STATUS

DEFINITIONS

(1)

Objective specification

Development

This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.

Preliminary specification

Qualification

This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

Product specification

Production

This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000

Philips Semiconductors a worldwide company

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

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Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
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Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
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Hungary: see Austria

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TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

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Tel. +31 40 27 82785, Fax. +31 40 27 88399

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Tel. +64 9 849 4160, Fax. +64 9 849 7811

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Tel. +41 1 488 2741 Fax. +41 1 488 3263

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Printed in The Netherlands

403510/50/01/pp

Date of release:

2000 Apr 10

Document order number:

9397 750 06019

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TZA3019

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TZA3019