2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

FEATURES

Pin compatible with the NE/SA5224 and NE/SA5225 but
with extended power supply range and less external
component count

Wideband operation from 1.0 kHz to 150 MHz typical

Applicable in 155 Mbits/s SDH/SONET receivers

Single supply voltage from 3.0 to 5.5 V

Positive Emitter Coupled Logic (PECL) compatible data
outputs

Programmable input signal level detection which can be
adjusted using a single external resistor

On-chip DC offset compensation without external
capacitor.

APPLICATIONS

Digital fibre optic receiver in short, medium and long
haul optical telecommunications transmission systems
or in high speed data networks

Wideband RF gain block.

GENERAL DESCRIPTION

The TZA3034 is a high gain limiting amplifier that is
designed to process signals from fibre optic preamplifiers
like the TZA3033. It is pin compatible with the NE/SA5224
and NE/SA5225 but with extended power supply range,
and needs less external components. Capable of
operating at 155 Mbits/s, the chip has input signal level
detection with a user-programmable threshold. The data
and level detection status outputs are differential outputs
for optimum noise margin and ease of use.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TZA3034T

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

TZA3034TT

TSSOP16

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

TZA3034U

bare die in waffle pack carriers; die dimensions 1.55

1.55 mm

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

BLOCK DIAGRAM

The numbers in brackets refer to the pad numbers of the bare die version.

Fig.1 Block diagram.

handbook, full pagewidth

MGR281

(3, 4, 6, 9)
3

15 (29)

(17) 9

16 (30)

(1, 14)
1

(11, 12)
6

(13)
7

2
(2, 10, 15, 21, 26)

(19, 20, 22, 25)
11

(27, 28)
14

25 k

DC-OFFSET

COMPENSATION

RECTIFIER

BAND GAP

REFERENCE

1 k

TZA3034

SUB

TEST

AGND

VCCA

STQ

(18) 10

(16) 8

JAM

(23) 12

DOUTQ

(24) 13

DOUT

DGND

VCCD

Vref

RSET

5 (8)

DINQ

4 (7)

DIN

Fig.2 Pin configuration of TZA3034T.

handbook, halfpage

TZA3034T

MGR282

SUB

TEST

AGND

DIN

DINQ

VCCA

JAM

STQ

DGND

DOUTQ

DOUT

VCCD

Vref

RSET

Fig.3 Pin configuration of TZA3034TT.

handbook, halfpage

TZA3034TT

MBK997

SUB

TEST

AGND

DIN

DINQ

VCCA

JAM

STQ

DGND

DOUTQ

DOUT

VCCD

Vref

RSET

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

PINNING

Note

1. Pin type abbreviations: O = Output, I = Input, S = power Supply and A = Analog function.

SYMBOL

PIN

TZA3034T

TZA3034TT

PAD

TZA3034U

TYPE

(1)

DESCRIPTION

SUB

1, 14

substrate pin; must be at the same potential as pin AGND

TEST

2, 10, 15,

21, 26

for test purpose only; to be left open in the application

AGND

3, 4, 6, 9

analog ground; must be at the same potential as pin DGND

DIN

differential input; complementary to pin DINQ; DC bias level is set
internally at approximately 2.1 V

DINQ

differential input; complementary to pin DIN; DC bias level is set
internally at approximately 2.1 V

CCA

11, 12

analog supply voltage; must be at the same potential as pin V

CCD

input for connection of capacitor to set time constant of level detector
input filter (optional); the capacitor should be connected between
V

CCA

and pin CF

JAM

PECL-compatible input; controls the output buffers,
pins DOUT and DOUTQ; when a LOW signal is applied, the output
buffers will follow the input signal; when a HIGH signal is applied, the
output buffers will latch into LOW and HIGH states respectively;
when not connected, pin JAM is actively pulled LOW

STQ

PECL-compatible status output of the input signal level detector;
when the input signal is below the user-programmed threshold level,
this output is HIGH; complementary to pin ST

PECL-compatible status output of the input signal level detector;
when the input signal is below the user-programmed threshold level,
this output is LOW; complementary to pin STQ

DGND

19, 20, 22,

digital ground; must be at the same potential as pin AGND

DOUTQ

PECL-compatible differential output; this pin will be forced into a
HIGH condition when pin JAM is HIGH; complementary to pin DOUT

DOUT

PECL-compatible differential output; this pin will be forced into a
LOW condition when pin JAM is HIGH; complementary to
pin DOUTQ

CCD

27, 28

digital supply voltage; must be at the same potential as V

CCA

ref

band gap reference voltage; typical value is 1.2 V; internal series
resistor of 1 k

RSET

input signal level detector threshold setting; nominal DC voltage is
V

CCA

1.5 V; threshold level is set by connecting an external resistor

between V

CCA

and pin RSET or by forcing a current into pin RSET;

default value for this resistor is 180 k

which corresponds with

approximately 4 mV (p-p) differential input signal

n.c.

5, 31, 32

not connected

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

FUNCTIONAL DESCRIPTION

The TZA3034 accepts up to 155 Mbits/s SDH/SONET
data streams, with amplitudes from 2 mV up to 1.5 V (p-p)
single-ended. The input signal will be amplified and limited
to differential PECL output levels (see Fig.1).

The input buffer A1 presents an impedance of
approximately 4.5 k

to the data stream on the inputs

pin DIN and pin DINQ. The input can be used both
single-ended and differential, but differential operation is
preferred for better performance.

Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3034, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.

An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
The outcome of this test is available at the PECL outputs,
pins ST and STQ. This flag can also be used to prevent
the PECL outputs pins DOUT and DOUTQ from reacting
to noise in the absence of a valid input signal, by
connecting pin STQ to pin JAM. This guarantees that data
will only be transmitted when the input signal-to-noise ratio
is sufficient for low bit error rate system operation.

PECL logic

The logic level symbol definitions for PECL are shown in
Fig.4.

Input biasing

The inputs, pins DIN and DINQ, are DC biased at
approximately 2.1 V by an internal reference generator
(see Fig.5). The TZA3034 can be DC coupled, but
AC coupling is preferred. In case of DC coupling, the
driving source must operate within the allowable input
signal range (1.3 V to V

CCA

). Also a DC offset voltage of

more than a few millivolts should be avoided, since the
internal DC offset compensation circuit has a limited
correction range.

If AC coupling is used to remove any DC compatibility
requirement, the coupling capacitors must be large
enough to pass the lowest input frequency of interest.
For example, 1 nF coupling capacitors react with the
internal 4.5 k

input bias resistors to yield a lower

3 dB

frequency of 35 kHz. This then sets a limit on the
maximum number of consecutive pulses that can be
sensed accurately at the system data rate. Capacitor
tolerance and resistor variation must be included for an
accurate calculation.

DC-offset compensation

A control loop connected between the inputs of buffer A3
and amplifier A1 (see Fig.1) will keep the input of buffer A3
at its toggle point in the absence of any input signal.
Because of the active offset compensation which is
integrated in the TZA3034, no external capacitor is
required. The loop time constant determines the lower
cut-off frequency of the amplifier chain, which is set at
approximately 850 Hz.

Input signal level detection

The TZA3034 allows for user-programmable input signal
level detection and can automatically disable the switching
of the PECL outputs if the input signal is below a set
threshold. This prevents the outputs from reacting to noise
in the absence of a valid input signal, and insures that data
will only be transmitted when the signal-to-noise ratio of
the input signal is sufficient for low bit-error-rate system
operation. Complementary PECL flags (pins ST and STQ)
indicate whether the input signal is above or below the
programmed threshold level.

The input signal is amplified and rectified before being
compared to a programmable threshold reference. A filter
is included to prevent noise spikes from triggering the level
detector. This filter has a nominal 1

s time constant and

additional filtering can be achieved by using an external
capacitor between V

CCA

and pin CF (the internal driving

impedance nominally is 25 k

). The resultant signal is

then compared to a threshold current through pin RSET.
This current can be set by connecting an external resistor
between V

CCA

and pin RSET, or by forcing a current into

pin RSET (see Fig.6).

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

The relationship between the threshold current and the
detected input voltage is approximately:

(1)

In the formulas (1) and (3), the voltage on pin DIN and
pin DINQ is measured as peak-to-peak value.

Since the voltage on pin RSET is held constant at 1.5 V
below V

CCA

, the current flowing into this pin will be:

(2)

Combining these two formulas results in a general formula
to calculate R

ADJ

for a given input signal level detection:

(3)

Example: Detection should occur if the differential voltage
of the input signals drops below 4 mV (p-p). In this case, a
reference current of 0.0018

0.004 = 7.2

A should flow

into pin RSET. This can be set using a current source or
simply by connecting a resistor of the appropriate value.
The resistor must be connected between V

CCA

and

pin RSET. In this example the value would be:

The hysteresis is fixed internally at 3 dB electrical. In the
example of above, a differential level below 4 mV (p-p) of
the input signal will drive pin ST to LOW, and an input
signal level above 5.7 mV (p-p) will drive pin ST to HIGH.

A function is provided to automatically disable the signal
transmission when the chip senses that the input signal is
below the programmed threshold level. This function can
be put into operation by connecting pin JAM with pin STQ.
When the input signal is below the programmed threshold
level, the data outputs are then forced to a predetermined
state (pin DOUT = LOW and pin DOUTQ = HIGH).

Response time of the input signal level detection circuit is
determined by the time constant of the input capacitors,
together with the filter time constant (1

s internal plus the

additional capacitor at pin CF). For SDH/SONET
applications, couple capacitors of 1.5 nF are
recommended, leading to a high-pass frequency of
approximately 30 kHz and a maximum assert time of
30

Dissipation

Since the thermal resistance from junction to ambient
R

th(j-a)

of the TSSOP package is higher than the thermal

resistance of the SO package (see Chapter "Thermal
characteristics"), the dissipation should be considered
when using the TZA3034TT version.

The formula to calculate the worst case die temperature is:

(4)

where

= junction temperature

amb

= ambient temperature

th(j-a)

= thermal resistance from junction to ambient

max

= maximum power dissipation.

For the TZA3034T (SO package), the worst case die
temperature T

= 85 + 115

0.3 = 119.5

C which is below

the maximum operating temperature.

For the TZA3034TT (TSSOP package), the worst case die
temperature T

= 85 + 150

0.3 = 130

C which is higher

than the maximum operating temperature, and therefore
strongly discouraged. It is recommended to lower the
thermal resistance from junction to ambient, e.g. by means
of a dedicated board layout.

However, if the ambient temperature is limited to 75

C or

the power supply is limited to 3.3

0.3 V, the junction

temperature will stay below the maximum value without
further precautions.

PECL output circuits

The output circuit of ST and STQ is given in Fig.7.

The output circuit of DOUT and DOUTQ is given in Fig.8.

Some PECL termination schemes are given in Fig.9.

RSET

0.0018

DIN

DINQ

(

)

[ ]

RSET

1.5

ADJ

------------- A

[ ]

ADJ

830

DIN

DINQ

(

)

----------------------------------------

[ ]

ADJ

830

0.004

---------------

207.5 k

amb

th j

(

)

max

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134.

HANDLING

This device is ESD sensitive and should be handled with care. Precautions should be taken to avoid damage through
electrostatic discharge. This is particularly important during assembly and handling of the bare die. Additional safety can
be obtained by bonding the V

and GND pads first, the remaining pads may then be bonded to their external

connections in any order.

THERMAL CHARACTERISTICS

Note

1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single-sided

1.6 mm FR4 epoxy printed-circuit board with 35

m thick copper traces. The measurements are performed

in still air.

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

supply voltage

0.5

DC voltage

pins DIN, DINQ, CF, JAM and RSET

0.5

+ 0.5

pins STQ, ST, DOUTQ and DOUT

+ 0.5

pin V

ref

0.5

+3.2

DC current

pins DIN, DINQ, CF and JAM

pins STQ, ST, DOUTQ and DOUT

+10

pin V

ref

+2.5

pin RSET

tot

total power dissipation

300

stg

storage temperature

+150

junction temperature

150

amb

ambient temperature

+85

SYMBOL

PARAMETER

CONDITION

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient note 1

SO16 package

115

K/W

TSSOP16 package

150

K/W

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

CHARACTERISTICS
For typical values T

amb

= 25

C and V

= 3.3 V; minimum and maximum values are valid over the entire ambient

temperature range and supply voltage range; all voltages are measured with respect to ground; unless otherwise
specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage

3.3

5.5

CCD

digital supply current

notes 1 and 2

CCA

analog supply current

note 2

tot

total power dissipation

notes 1 and 2

110

300

junction temperature

+125

amb

ambient temperature

+25

+85

Input signal pins DIN and DINQ

i(se)(p-p)

single-ended input signal
voltage (peak-to-peak)

note 3

0.002

1.5

i(dif)(p-p)

differential input signal voltage
(peak-to-peak)

note 3

0.004

3.0

absolute input signal voltage

1.3

2.1

CCA

IO(eq)

equivalent input signal offset
voltage

IO(cor)

input offset voltage correction

note 4; positive

note 4; negative

input resistance

single-ended

2.9

4.5

7.6

input capacitance

single-ended; note 5

2.5

n(i)(rms)

equivalent input RMS noise
voltage

notes 5 and 6

Input signal level detect pin RSET

RSET

reference current

notes 5 and 7

RSET

reference voltage

referred to V

CCA

1.65

CCA

1.5

CCA

1.4

th(p-p)

threshold adjusting range
(single-ended and
peak-to-peak)

= 155 Mbit/s PRBS

1 sequence;

note 5

hys

hysteresis

electrically measured

filter resistance

filter time constant

CF = 0; note 5

0.5

1.0

2.0

PECL output pins DOUT and DOUTQ

LOW-level output voltage

note 8

1.89

1.6

HIGH-level output voltage

note 8

1.1

0.9

rise time

20% to 80%; note 5

1.5

2.2

fall time

80% to 20%; note 5

1.5

2.2

PWD

pulse width distortion

note 5

0.3

3dB(l)

low frequency

3 dB point

0.85

1.5

kHz

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

Notes

1. PECL outputs (pins DOUT, DOUTQ, ST and STQ) are not connected.

2. Maximum currents are specified at T

= 125

C, V

= 5.5 V and worst case processing.

3. 2 mV (p-p) single-ended is the minimum input signal to achieve full clipping of the output signal. Typical an input

signal of 0.5 mV (p-p) single-ended results in a Bit Error Rate (BER) of less than 10

4. If the input is DC coupled, the preceding amplifier's output offset voltage should not exceed these limits, in order to

avoid malfunctioning of the DC offset compensation circuit.

5. Specifications guaranteed by design and characterisation. Each device is tested at full operating speed to guarantee

RF functionality.

7. The reference current can be set by connecting a resistor between V

CCA

and pin RSET. The corresponding input

signal level detect range is from 2 to 12 mV (p-p) single-ended. See Section "Input signal level detection" for detailed
information.

8. R

= 50

connected to a level of V

2 V (see Fig.9).

9. Internal pull-down resistor of 500 k

to DGND.

10. Internal series resistor of 1 k

3dB(h)

high frequency

3 dB point

150

MHz

PECL output pins ST and STQ

LOW-level output voltage

note 8

1.89

1.6

HIGH-level output voltage

note 8

1.1

0.9

load capacitance

= 1 k

100

= 50

1000

PECL input pin JAM

LOW-level input voltage

1.49

HIGH-level input voltage

1.165

I(JAM)

JAM input current

note 9

+20

Reference voltage output pin V

ref

ref

reference voltage

note 10

1.165

1.20

1.235

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Input RMS noise

total output RMS noise

low frequency gain

---------------------------------------------------------------

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

TYPICAL PERFORMANCE CHARACTERISTICS

Fig.10 Total power supply current as function of

junction temperature.

PECL outputs not connected.

(1) V

= 5.5 V.

(2) V

= 3.0 V.

handbook, halfpage

120

MGR944

ICC

(mA)

Tj (

(2)

(1)

Fig.11 Differential output voltage as function of

junction temperature.

handbook, halfpage

1.5

1.0

1.4

MGR945

120

Tj (

1.3

1.2

1.1

Vo(dif)

(V)

o(dif)

= V

DOUT

DOUTQ

Fig.12 Differential output voltage as function of

differential input voltage.

handbook, halfpage

1.1

1.2

1.3

1.4

MGR946

Vi(dif)(p-p) (V)

Vo(dif)

(V)

o(dif)

= V

DOUT

DOUTQ

Fig.13 Differential output rise time and fall time as

function of differential input voltage.

handbook, halfpage

1.0

1.2

1.4

1.8

1.6

2.0

MGR947

(ns)

t r

t f

Vi(dif)(p-p) (V)

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

Fig.14 Differential output rise time and fall time as

function of junction temperature.

handbook, halfpage

120

2.0

0.4

1.2

MGR948

1.6

0.8

(ns)

Tj (

Fig.15 Status detect level as function of I

RSET

i(dif)

= V

DIN

DINQ

(1) Input high threshold for 1 0 1 0 pattern (pin ST = HIGH).

(2) Input high threshold for 2

1 PRBS pattern (pin ST = HIGH).

(3) Input low threshold for 1 0 1 0 pattern (pin ST = LOW).

(4) Input low threshold for 2

1 PRBS pattern (pin ST = LOW).

handbook, halfpage

MGR949

IRSET (

(1)

(2)

(3)

(4)

Vi(dif)

(mV)

Fig.16 Status detect level as function of junction

temperature.

handbook, halfpage

120

MGR950

Tj (

Vi(dif)

(mV)

(1)

(2)

(3)

(4)

i(dif)

= V

DIN

DINQ

(1) Input high threshold for I

RSET

= 45

A (pin ST = HIGH).

(2) Input low threshold for I

RSET

= 45

A (pin ST = LOW).

(3) Input high threshold for I

RSET

= 10

A (pin ST = HIGH).

(4) Input low threshold for I

RSET

= 10

A (pin ST = LOW).

Fig.17 Status detect hysteresis as function of

RSET

(1) 1 0 1 0 pattern.

(2) 2

1 PRBS pattern.

handbook, halfpage

MGR951

hys

(dB)

(1)

IRSET (

(2)

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

Fig.18 Status detect hysteresis as function of

junction temperature.

(1) I

RSET

= 10

(2) I

RSET

= 45

handbook, halfpage

120

MGR952

hys

(dB)

Tj (

(2)

(1)

Fig.19 Status detect ratio as function of I

RSET

handbook, halfpage

0.003

0.001

0.002

MGR953

Ratio

(A/V)

IRSET (

(2)

(1)

where V

i(dif)

= input low threshold (pin ST = LOW).

(1) 2

1 PRBS pattern.

(2) 1 0 1 0 pattern.

Ratio

RSET

i dif

(

)

--------------

Fig.20 Pulse Width Distortion (t

PWD

) as function of

differential input voltage.

handbook, halfpage

0.1

0.2

0.3

MGR954

tPWD

(ns)

Vi(dif)(p-p) (V)

Fig.21 V

RSET

as function of junction temperature.

RSET

= V

CCA

1.5 V.

(1) V

= 5.5 V.

(2) V

= 3.0 V.

handbook, halfpage

120

1.55

1.51

1.49

1.53

MGR955

Tj (

(2)

(1)

VRSET

(V)

2002

Jul

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

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Fig.25 STM1/OC3 receiver using the TZA3033T and TZA3034.

(1) Ferrite bead e.g. Murata BLM10A700S.

The numbers in brackets refer to the pad numbers of the bare die version.

width

MGR285

(23) 12

DOUTQ

OUT

OUTQ

(24) 13

DOUT

1 k

1.5 nF

100 nF

31 pF

noise filter:
1-pole, 100 MHz

100

135 k

TZA3033T

TZA3034

(1, 14)

(19, 20, 22, 25)

SUB

(16)

JAM

(17)

STQ

(18)

(3, 4, 6, 9)

AGND

VCC

(11, 12)

VCCA

(30)

RSET

(13)

(29)

Vref

(27, 28)

VCCD

DGND

data out

level detect
status

VCC

2 V

5 (8)

DINQ

4 (7)

DIN

22 nF

680 nF

100 nF

29.2

4.5

64.4 nH

optional noise filter:
3-pole, 120 MHz Bessel

(1)

GND

10 nF

IPhoto

DREF

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

BONDING PADS

Note

1. The x and y coordinates represent the position of the

centre of the pad with respect to the centre of the die
(see Fig.26).

SYMBOL

PAD

COORDINATES

(1)

SUB

235.7

+647.8

TEST

392.8

+647.8

AGND

532.8

+647.8

AGND

647.8

+507.1

n.c.

647.8

+350.0

AGND

647.8

+210.0

DIN

647.8

+70.0

DINQ

647.8

70.0

AGND

647.8

210.0

TEST

647.8

350.0

CCA

647.8

507.1

CCA

532.8

647.8

392.8

647.8

SUB

235.7

647.8

TEST

78.6

647.8

JAM

+61.4

647.8

STQ

+218.5

647.8

+375.6

647.8

DGND

+532.7

647.8

DGND

+647.8

507.1

TEST

+647.8

350.0

DGND

+647.8

210.0

DOUTQ

+647.8

70.0

DOUT

+647.8

+70.0

DGND

+647.8

+210.0

TEST

+647.8

+350.0

CCD

+647.8

+507.1

CCD

+532.7

+647.8

ref

+392.7

+647.8

RSET

+235.6

+647.8

n.c.

+78.5

+647.8

n.c.

78.6

+647.8

SYMBOL

PAD

COORDINATES

(1)

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

Fig.26 Bonding pad locations of TZA3034U.

(1) Typical value.

handbook, full pagewidth

AGND

VCCD

TEST

DGND

DOUT

DOUTQ

DGND

TEST

DGND

AGND

DIN

DINQ

AGND

TEST

VCCA

n.c.

TZA3034U

CCA

GND

TEST

SUB

n.c.

RSET

ref

CCD

SUB

TEST

STQ

DGND

MGR283

1.55

(1)

1.55

(1)

Table 1

Physical characteristics of bare die

PARAMETER

VALUE

Glass passivation

2.1

m PSG (PhosphoSilicate Glass) on top of 0.65

m oxynitride

Bonding pad dimension

minimum dimension of exposed metallization is 90

m (pad size = 100

100

Metallization

1.22

m W/AlCu/TiW

Thickness

380

m nominal

Size

1.55

1.55 mm (2.4 mm

)

Backing

silicon; electrically connected to GND potential through substrate contacts

Attache temperature

<440

C; recommended die attache is glue

Attache time

<15 s

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

PACKAGE OUTLINES

detail X

(A )

pin 1 index

UNIT

max.

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

inches

1.75

0.25
0.10

1.45
1.25

0.25

0.49
0.36

0.25
0.19

10.0

9.8

4.0
3.8

1.27

6.2
5.8

0.7
0.6

0.7
0.3

8
0

0.25

0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.0
0.4

SOT109-1

97-05-22
99-12-27

076E07

MS-012

0.069

0.010
0.004

0.057
0.049

0.01

0.019
0.014

0.0100
0.0075

0.39
0.38

0.16
0.15

0.050

1.05

0.041

0.244
0.228

0.028
0.020

0.028
0.012

0.01

0.25

0.01

0.004

0.039
0.016

2.5

5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

UNIT

(1)

(2)

(1)

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

EIAJ

0.15
0.05

0.95
0.80

0.30
0.19

0.2
0.1

5.1
4.9

4.5
4.3

0.65

6.6
6.2

0.4
0.3

0.40
0.06

8
0

0.13

0.1

0.2

1.0

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75
0.50

SOT403-1

MO-153

95-04-04
99-12-27

0.25

detail X

(A )

2.5

5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

max.

1.10

pin 1 index

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 220

C for

thick/large packages, and below 235

C for small/thin

packages.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. For more detailed information on the BGA packages refer to the

"(LF)BGA Application Note" (AN01026); order a copy

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

(1)

SOLDERING METHOD

WAVE

REFLOW

(2)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA

not suitable

suitable

HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS

not suitable

(3)

suitable

PLCC

(4)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(4)(5)

suitable

SSOP, TSSOP, VSO

not recommended

(6)

suitable

2002 Jul 19

Philips Semiconductors

Product specification

SDH/SONET STM1/OC3 postamplifier

TZA3034

DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

DATA SHEET

STATUS

(1)

PRODUCT

STATUS

(2)

DEFINITIONS

Objective data

Development

This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Preliminary data

Qualification

This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips Semiconductors
reserves the right to change the specification without notice, in order to
improve the design and supply the best possible product.

Product data

Production

This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order to
improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.

DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products

for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

Bare die

All die are tested and are guaranteed to

comply with all data sheet limits up to the point of wafer
sawing for a period of ninety (90) days from the date of
Philips' delivery. If there are data sheet limits not
guaranteed, these will be separately indicated in the data
sheet. There are no post packing tests performed on
individual die or wafer. Philips Semiconductors has no
control of third party procedures in the sawing, handling,
packing or assembly of the die. Accordingly, Philips
Semiconductors assumes no liability for device
functionality or performance of the die or systems after
third party sawing, handling, packing or assembly of the
die. It is the responsibility of the customer to test and
qualify their application in which the die is used.

SCA74

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Philips Semiconductors a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands

403510/04/pp

Date of release:

2002 Jul 19

Document order number:

9397 750 09951

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TZA3034U/C2

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TZA3034U/C2