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Электронный компонент: UAA3202

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DATA SHEET
Preliminary specification
File under Integrated Circuits, IC01
1997 Aug 12
INTEGRATED CIRCUITS
UAA3202M
Frequency Shift Keying (FSK)
receiver
1997 Aug 12
2
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
FEATURES
Low cost single-chip FSK receiver
Superheterodyne architecture with high integration level
Few external low cost components
Wide supply voltage range
Low power consumption
Wide frequency range, 150 to 450 MHz
High sensitivity
IF band determined by application
High selectivity
Very low spurious radiation,
-
60 dBm
(meets FTZ 17TR2100)
Automotive temperature range
Power-down mode
SSOP20 package.
Applications
Keyless entry systems
Car alarm systems
Remote control systems
Security systems
Telemetry systems
Wireless data transmission
Domestic appliances.
GENERAL DESCRIPTION
The UAA3202M is a fully integrated single-chip receiver,
primarily intended for use in VHF and UHF systems
employing direct Frequency Shift Keying (FSK)
modulation. The UAA3202M incorporates a SAW
stabilized local oscillator, balanced mixer, IF amplifier,
limiter, Received Signal Strength Indicator (RSSI), RSSI
comparator, FSK demodulator, data filter and data slicer.
The device features a power-down mode in order to
minimize the average receiver supply current.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CC
supply voltage
3.5
-
6
V
I
CC
supply current for
operating mode on
V
PWD
= 0 V; R
2
= 560
2.0
3.4
4.7
mA
operating mode off
V
PWD
= V
CC
-
3
30
A
P
sens
sensitivity
f
i
= 433.92 MHz;
f
mod
= 250 Hz square wave;
f =
25 kHz; BER
3%
-
-
-
94
dBm
T
amb
operating ambient temperature
-
40
-
+85
C
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UAA3202M
SSOP20
plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
1997 Aug 12
3
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MHA797
1.5 k
50 k
30 k
150 k
150 k
1.4 k
1.5 k
MIXER
BIAS
OSCILLATOR
LIMITER
AMPLIFIER
20
19
18
17
16
15
14
13
12
11
12
3
4
5
6
7
8
9
1
0
IF
AMP
V
CC
RSSI
V
ref
V
ref
PHASE
SHIFT
PHASE
DETECTOR
UAA3202M
BUFFER
MON
MOP
V
CC
OSC
OSE
V
EO
V
EE
COMP
CPB
CPA
FA
V
EM
MXIN
LIN
RSSI
DMOD
LFB
CPC
PWD
DATA
1997 Aug 12
4
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
PINNING
SYMBOL
PIN
DESCRIPTION
MON
1
negative mixer output
MOP
2
positive mixer output
V
CC
3
positive supply voltage
OSC
4
oscillator collector
OSE
5
oscillator emitter
V
EO
6
negative supply voltage for oscillator
V
EE
7
negative supply voltage
COMP
8
RSSI comparator output
CPB
9
comparator input B
CPA
10
comparator input A
DATA
11
data output
PWD
12
power-down control input
CPC
13
comparator input C
DMOD
14
demodulator frequency adjustment
RSSI
15
RSSI current output
LFB
16
limiter feedback
LIN
17
limiter input
MXIN
18
mixer input
V
EM
19
negative supply voltage for mixer
FA
20
IF amplifier output
Fig.2 Pin configuration.
handbook, halfpage
MON
MOP
VCC
OSC
OSE
VEO
VEE
COMP
CPB
CPA
FA
VEM
MXIN
LIN
RSSI
DMOD
LFB
CPC
PWD
DATA
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
UAA3202M
MHA796
1997 Aug 12
5
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
FUNCTIONAL DESCRIPTION
The device is based on the superheterodyne architecture
incorporating a mixer, local oscillator, IF amplifier, limiter,
RSSI, RSSI comparator, FSK demodulator, data filter,
data slicer and power-down circuitry. The device employs
a low IF frequency of typically 1 MHz in order to allow IF
filtering by means of external low cost R, L and C
components. If image rejection is required it can be
achieved by applying a matching external front-end SAW
filter. The device provides a wide IF range of 300 kHz in
order to allow the use of a SAW stabilized oscillator.
The on-chip local oscillator provides the injection signal for
the mixer. Tuning of the on-chip local oscillator is not
necessary. The oscillator frequency is determined by an
external 1-port SAW resonator. The RF input signal is fed
to the mixer and down converted to the IF frequency. After
amplification and filtering the RF signal is applied to a
limiter. The IF filter order and characteristics are
determined by the external low cost R, L and C
components. The limiter amplifier provides a RSSI signal
which can be routed to an on-chip RSSI level comparator
in order to derive a field strength indication for external
use. The limited IF signal is fed to the FSK demodulator.
The demodulator centre frequency is determined by an
external capacitor. No alignment is necessary for the FSK
demodulator. After filtering the demodulated data signal is
fed to a data slicer and is made available at the data
output. The data filter characteristics are determined by
external capacitors. The data slicer employs an adaptive
slice reference in order to track frequency offsets.
The device is switched from power-down to operating
mode and vice versa by means of a control input.
Extremely low supply current is drawn when the device is
in power-down mode. Measures are taken to allow fast
receiver settling when the device is switched from
power-down to operating mode.
Mixer
The mixer is a single balanced emitter coupled mixer with
internal biasing. Matching of the RF source impedance to
the mixer input requires an external matching network.
Oscillator
The oscillator consists of an on-chip transistor in common
base configuration. An external tank and SAW resonator
determines the oscillator frequency. Oscillator alignment is
not necessary. Oscillator bias is controlled by an external
resistor.
Post mixer amplifier
The Post Mixer Amplifier (PMA) is a differential input,
single-ended output amplifier. It separates the first and
second IF filters from each other. Amplifier gain is provided
in order to reduce the influence of the limiter noise figure
on the total noise figure.
Limiter
The limiter is a single-ended input multiple stage amplifier
with high total gain. Amplifier stability is achieved by
means of an external DC feedback capacitor, which is also
used to determine the lower limiter cut-off frequency.
An RSSI signal proportional to the limiter input signal is
provided.
IF filters
IF filtering with high selectivity is realized by means of
external low cost R, L and C components. The first IF filter
is located directly following the mixer output. An external
L/C network assembles a band-pass with low sensitivity in
order to meet the bandwidth of an elliptic low-pass filter
external to the device and is located in front of the limiter.
The filter source impedance is determined by the drive
impedance of the IF amplifier. In order to improve the IF
filter selectivity below the pass-band a high-pass
characteristic is added by means of a DC blocking
capacitor in front of the limiter input and by means of the
limiter DC feedback capacitor.
RSSI
The RSSI signal is a current proportional to the limiter input
level (RF input power). By means of an external resistor
the resulting RSSI voltage level is set in order to fit the
application. The RSSI voltage is available to external
circuits and is fed to the input of the RSSI level
comparator. For RSSI filtering an external capacitor is
connected.
RSSI level comparator
The RSSI level comparator compares the RSSI level with
a fixed and independent internal reference voltage. If the
RSSI level exceeds the internal reference voltage a logic
HIGH signal is generated. The level comparator provides
some hysteresis in order to avoid spurious oscillation.
The output of the level comparator is designed as an
open-collector with internal pull-up.
1997 Aug 12
6
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
FSK demodulator
The limited IF signal is converted into baseband data by
means of a quadrature FM demodulator consisting of an
all-pass filter and a mixer stage. No alignment of the
demodulator is necessary. The demodulator centre
frequency is set by a capacitor external to the device.
The demodulator provides a large audio bandwidth in
order to allow high data rate applications.
The demodulator can detect a small IF frequency deviation
even if a relatively large IF frequency offset is
encountered.
Data filters
After demodulation a two-stage data filtering circuit is
provided in order to suppress unwanted frequency
components. Two R/C low-pass filters with on-chip
resistors are provided which are separated by a buffer
stage.
Data slicer
Data detection is provided by means of a level comparator
with adaptive slice reference. After the first data filter stage
the pre-filtered data is split into two parts. One part passes
the second data filter stage and is fed to the positive
comparator input.
The other path is fed to an integration circuit with a large
time constant in order to derive the average value
(DC component) as an adaptive slice reference which is
presented to the negative comparator input. The adaptive
reference enables the received data over a large range of
demodulator frequency offsets to be detected.
The integration circuit consists of a simple R/C low-pass
filter with on-chip resistor. The level comparator output is
designed as an open-collector with internal pull-up.
Power-down circuitry
The device provides a power-down mode. While in
power-down mode the device disables the majority of the
internal circuits and consumes extremely low current.
Measures are taken to allow fast receiver settling when
normal operation is resumed. Thus circuits with large time
constants are only powered down partly or provide a high
impedance during power-down in order to avoid the
discharge of external capacitors as much as possible.
Power-down mode is entered when the control input is
active HIGH. The control input provides an internal pull-up
resistor of high impedance.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k
series resistor.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
supply voltage
-
0.3
+8.0
V
T
amb
operating ambient temperature
-
40
+85
C
T
stg
storage temperature
-
55
+125
C
V
esd
electrostatic handling
note 1
pins 4 and 5
-
2000
+1500
V
pins 18 and 19
-
1500
+2000
V
all other pins
-
2000
+2000
V
SYMBOL
PARAMETER
VALUE
UNIT
R
th j-a
thermal resistance from junction to ambient in free air
125
K/W
1997 Aug 12
7
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
DC CHARACTERISTICS
V
CC
= 3.5 V; T
amb
= 25
C; for application diagram see Fig.11; unless otherwise specified.
Notes
1. The given values are valid for the whole temperature range from T
amb
=
-
40 to +85
C.
2. Tune RF input frequency until IF = 1 MHz.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
CC
supply voltage
3.5
-
6
V
I
CC
supply current for
note 1
operating mode on
V
PWD
= 0 V;
R
2
= 560
2.0
3.4
4.7
mA
operating mode off
V
PWD
= V
CC
-
3
30
A
V
PWD(on)
PWD voltage for operating mode ON
0
-
300
mV
V
PWD(off)
PWD voltage for operating mode OFF
V
CC
-
0.3
-
V
CC
V
I
PWD(on)
PWD current for operating mode ON
V
PWD
= 0 V
-
30
-
10
-
3
A
I
PWD(off)
PWD current for operating mode OFF
V
PWD
= V
CC
-
1
3
A
Oscillator
V
OSC(DC)
DC operating point pin 4
3.28
3.34
3.40
V
Mixer
V
MXIN(DC)
DC operating point pin 18
0.68
0.78
0.88
V
V
MOP(DC)
DC operating point pin 2
2.78
2.98
3.18
V
V
MON(DC)
DC operating point pin 1
2.78
2.98
3.18
V
Post mixer amplifier
V
FA(DC)
DC operating point pin 20
2.14
2.27
2.40
V
Limiter
V
LIN(DC)
DC operating point pin 17
3.45
3.49
3.50
V
V
LFB(DC)
DC operating point pin 16
2.76
2.81
2.86
V
V
RSSI(DC)
DC operating point pin 15
2.21
2.36
2.51
V
Demodulator
V
DMOD(DC)
DC operating point pin 14
1.63
1.83
2.03
V
Data slicer
V
CPC(DC)
DC operating point pin 13
note 2
1.43
1.93
2.43
V
V
CPA(DC)
DC operating point pin 10
note 2
1.43
1.93
2.43
V
V
CPB(DC)
DC operating point pin 9
note 2
1.43
1.93
2.43
V
V
OH(DAT)
HIGH-level data output voltage
I
DATA
=
-
10
A
V
CC
-
0.5
-
V
CC
V
V
OL(DAT)
LOW-level data output voltage
I
DATA
= 200
A
0
-
0.6
V
RSSI comparator
V
OH(RSSI)
HIGH-level comparator output voltage
I
RSSI
=
-
10
A
V
CC
-
0.5
-
V
CC
V
V
OL(RSSI)
LOW-level comparator output voltage
I
RSSI
= 200
A
0
-
0.6
V
1997 Aug 12
8
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
AC CHARACTERISTICS
V
CC
= 3.5 V; T
amb
= 25
C; for application diagram see Fig.11; f
i
= 433.92 MHz;
f =
25 kHz; f
mod
= 250 Hz square
wave, i.e. 500 bits/s; unless otherwise specified.
Notes
1. Measured at the RF input connector of the test board.
2. Measured at test point A in Fig.11.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System performance
P
sens
sensitivity
BER
3%
-
-
-
94
dBm
P
i(max)
maximum input power
BER
3%
-
-
-
30
dBm
rad
spurious radiation
note 1
-
-
-
60
dBm
t
st
receiver settling time
P
i
= P
sens
+ 10 dB; see Fig.5
-
2
5
ms
B
IF
IF bandwidth range
P
i
= P
sens
+ 3 dB
850
1000
1150
kHz
f
D
data frequency
140
-
250
Hz
Mixer
G
mix
mixer conversion gain
31
33
35
dB
R
o(mix)
mixer output resistance
2.7
3
3.3
k
Post mixer amplifier
IP3
PMA
interception point (mixer + PMA)
note 2
-
38
-
35
-
dBm
G
PMA
PMA gain
note 2
9
10.4
12
dB
P
<1dB
compression (mixer + PMA)
P
i
=
-
45 dBm
0
-
1
dBm
BW
PMA
PMA LP cut-off frequency
5
-
-
MHz
R
oPMA
PMA output resistance
1.2
1.4
1.6
k
Limiter
G
lim
limiter gain
60
63.5
67
dB
B
lim
limiter LP cut-off frequency
2
5
8
MHz
R
i(lim)
limiter input resistance
40
50
60
k
Demodulator
G
DMOD
demodulator gain
note 2
0.8
1
1.2
f
c(DMOD)
demodulator centre frequency
800
1000
1200
kHz
f
frequency deviation
20
25
70
kHz
R
o(DMOD)
demodulator output resistance
24
30
36
k
Data slicer
B
DS
data slicer bandwidth
35
50
-
kHz
R
o(DS)
data slicer output resistance
120
150
180
k
RSSI comparator
V
o(RSSI)
RSSI output voltage
see Fig.3
-
-
-
-
V
o(COMP)
COMP output voltage
see Fig.4
-
-
-
-
P
th(on)
threshold for switching COMP output
voltage to HIGH
-
99.5
-
95.5
-
91.5
dBm
P
hys(W)
hysteresis width of COMP output voltage
1
2
4
dBm
mV
kHz
----------
1997 Aug 12
9
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
Fig.3 RSSI output voltage as a function of RF input power.
(1) T
amb
= 85
C.
(2) T
amb
= 25
C.
(3) T
amb
=
-
40
C.
handbook, full pagewidth
2.7
2.8
MHA811
Vo(RSSI)
(V)
2.6
2.5
2.4
-
100
-
90
-
80
-
70
-
60
-
50
Pi (dBm)
(1)
(2)
(3)
Fig.4 Comparator output voltage as a function of HF input power.
handbook, halfpage
MHA812
Phys(W)
3.0
0.6
Vo(COMP)
(V)
Pth(ON)
-
97.5
-
95.5
Pi (dBm)
1997 Aug 12
10
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
INTERNAL CIRCUITRY
Table 1
Equivalent pin circuits and pin voltages for rough test of printed circuit board; V
CC
= 3.5 V; no input signal
PIN
SYMBOL
DC VOLTAGE
(V)
EQUIVALENT CIRCUIT
1
MON
2.98
2
MOP
2.98
3
V
CC
-
4
OSC
3.34
5
OSE
-
6
V
EO
0
7
V
EE
0
8
COMP
-
9
CPB
1.93
10
CPA
1.93
MHA798
VEE
1.5 k
1.5 k
2
1
VCC
VEM
MHA799
6 k
4
5
VEE
MHA800
1 k
8
VCC
VEE
MHA801
150 k
150
10
9
VCC
VEE
1997 Aug 12
11
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
11
DATA
-
12
PWD
-
13
CPC
1.93
14
DMOD
1.83
PIN
SYMBOL
DC VOLTAGE
(V)
EQUIVALENT CIRCUIT
MHA802
1 k
11
VCC
VEE
MHA803
300 k
12
VCC
MHA804
30 k
13
VCC
VEE
MHA805
14
VCC
VEE
1997 Aug 12
12
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
15
RSSI
2.36
16
LFB
2.81
17
LIN
3.49
PIN
SYMBOL
DC VOLTAGE
(V)
EQUIVALENT CIRCUIT
MHA806
15
VCC
MHA807
16
VCC
VEE
MHA808
50 k
17
VCC
VEE
1997 Aug 12
13
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
18
MXIN
0.78
19
V
EM
0
20
FA
2.27
PIN
SYMBOL
DC VOLTAGE
(V)
EQUIVALENT CIRCUIT
MHA809
15
18
19
MHA810
1.2 k
20
VCC
VEE
1997 Aug 12
14
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
TEST INFORMATION
Tuning procedure for AC tests
1. Turn on the signal generator (f
i
= 433.92 MHz; no modulation; RF input level =
-
60 dBm).
2. Tune C6 (RF stage input) to obtain a peak voltage on test point A (see Fig.11).
3. Turn on modulation (f
i
= 433.92 MHz; f
mod
= 250 Hz square wave;
f = 25 kHz; RF input level =
-
60 dBm).
4. Check that data is appearing on the data output (pin 11) and proceed with the AC tests.
AC test conditions
Table 2
Test signals
The reference signal level P
ref
for the following tests is defined as the minimum input level in dBm to give a
BER
3
10
-
2
(e.g. 15 bit errors per second for 500 bits/s).
Table 3
Test results
P
1
is the maximum available power from signal generator 1 at the input of the test board; P
2
is the maximum available
power from signal generator 2 at the input of the test board.
Notes
1. The power-down voltage V
PWD
alternates between operating mode ON (100 ms) and OFF (100 ms); see Fig.5.
2. Probe of spectrum analyzer connected to test point A.
3. Spectrum analyzer connected to the input of the test board.
TEST
SIGNAL
FREQUENCY
(MHz)
DATA SIGNAL
MODULATION
FREQUENCY
DEVIATION
1
433.92
250 Hz square wave
FM (FSK)
25 kHz
2
433.92
-
no modulation
-
3
433.82
-
no modulation
-
TEST
GENERATOR
RESULT
1
2
Sensitivity into pin MXIN
(see Fig.6)
modulated test
signal 1; P
1
-
94 dBm
-
BER
3
10
-
2
(e.g. 15 bit errors per second for 500 bits/s)
Maximum input power
(see Fig.6)
modulated test
signal 1; P
1
-
30 dBm
(minimum P
max
)
-
BER
3
10
-
2
(e.g. 15 bit errors per second for 500 bits/s)
Receiver turn-on time; note 1
test signal 1;
P
1
= P
ref
+ 10 dB
-
check that the first 10 bits are correct; error
counting is started 10 ms after PWD
switched to operating mode: ON
Intercept point (mixer + PMA)
see note 2 and Fig.7
test signal 3;
P
1
=
-
55 dBm
test signal 2;
P
2
= P
1
IP3 = P
1
+
1
/
2
IM3 (dB); IP3
-
38 dBm
Spurious radiation see note 3
and Fig.8
-
-
no spurious radiation (25 MHz
-
1 GHz)
with level higher than
-
60 dBm
(maximum P
spur
)
1 dB compression point
(mixer + PMA) see note 2
and Fig.9
test signal 3;
P
11
=
-
70 dBm;
P
12
=
-
45 dBm
(minimum P
1dB
)
-
(P
o1
+ 70 dB)
-
[P
o2
+ 45 dB (minimum
P
1 dB
)]
1 dB, where P
o1
, P
o2
is the output
power for test signals with P
11
or P
12
,
respectively
1997 Aug 12
15
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
Fig.5 Timing diagram for pulsed power-down voltage.
handbook, full pagewidth
t (ms)
500
300
400
200
100
0
0
3.5
VPWD
(V)
MHA834
Fig.6 Test configuration A (single generator).
(1) For test circuit see Fig.11.
(2) For BER test facility see Fig.10.
TEST CIRCUIT
(1)
(2)
GENERATOR 1
50
MED900
BER TEST
FACILITY
Fig.7 Test configuration B (IP3).
(1) For test circuit see Fig.11.
SPECTRUM
ANALYZER
WITH
PROBE
TEST CIRCUIT
(1)
GENERATOR 1
50
2-SIGNAL
POWER
COMBINER
50
GENERATOR 2
50
MED901
f
f = 100 kHz
f
f
IM3
1997 Aug 12
16
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
Fig.8 Test configuration C (spurious radiation).
(1) For test circuit see Fig.11.
SPECTRUM
ANALYZER
INPUT IMPEDANCE
50
TEST CIRCUIT
(1)
MED902
Fig.9 Test configuration D (1 dB compression point).
(1) For test circuit see Fig.11.
SPECTRUM
ANALYZER
WITH
PROBE
TEST CIRCUIT
(1)
GENERATOR 1
50
MED903
Fig.10 BER test facility.
DEVICE
UNDER TEST
SIGNAL
GENERATOR
MASTER
CLOCK
BIT PATTERN
GENERATOR
PRESET
DELAY
DATA
COMPARATOR
INTEGRATE
AND DUMP
RX data
BER TEST BOARD
to error counter
TX data
MED904
delayed
TX data
1997 Aug 12
17
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
APPLICATION INFORMATION
andbook, full pagewidth
MHA814
1.5 k
50 k
30 k
150 k
150 k
1.4 k
1.5 k
MIXER
BIAS
OSCILLATOR
LIMITER
AMPLIFIER
20
19
18
17
16
15
14
13
12
11
12
3
4
5
6
7
8
9
1
0
PMA
V
CC
RSSI
V
ref
V
ref
PHASE
SHIFT
PHASE
DETECTOR
C7
L5
L4
C1
C16
C18
C3
C24
C14
C13
C2
SAWR
432.92 MHz
R3
R2
(1)
COMP
UAA3202M
V
CC
V
CC
data
output
power-down
C17
C12
C25
C22
test point
A
C23
R4
V
CC
C19
L2
L3
C20
C5
C4
C8
C9
C11
C10
L1
C6
BUFFER
Fig.11 Application diagram.
(1)
Stray inductance.
1997 Aug 12
18
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
Table 4
Application component list for Fig.11
Table 5
Surface Acoustic Wave Resonator (SAWR) data
COMPONENT
VALUE
TOLERANCE
DESCRIPTION
R2
560
2%
TC = 50 ppm/K
R3
220
2%
TC = 50 ppm/K
R4
820 k
2%
TC = 50 ppm/K
C1
4.7
F
20%
-
C2
150 pF
10%
TC = 0
30 ppm/K; tan
10
10
-
4
; f = 1 MHz
C3
100 nF
10%
TC = 0
30 ppm/K; tan
10
10
-
4
; f = 1 MHz
C4
100 pF
10%
TC = 0
30 ppm/K; tan
10
10
-
4
; f = 1 MHz
C5
2.7 pF
10%
TC = 0
150 ppm/K; tan
30
10
-
4
; f = 1 MHz
C6
3 to 10 pF
-
TC = 0
300 ppm/K; tan
20
10
-
4
; f = 1 MHz
C7
56 pF
10%
TC = 0
30 ppm/K; tan
10
10
-
4
; f = 1 MHz
C8
33 pF
10%
TC = 0
30 ppm/K; tan
10
10
-
4
; f = 1 MHz
C9
100 pF
10%
TC = 0
30 ppm/K; tan
10
10
-
4
; f = 1 MHz
C10
5.6 pF
10%
TC = 0
30 ppm/K; tan
20
10
-
4
; f = 1 MHz
C11
100 pF
10%
TC = 0
30 ppm/K; tan
10
10
-
4
; f = 1 MHz
C12
100 nF
10%
tan
25
10
-
3
; f = 1 kHz
C13
2.2 nF
10%
tan
25
10
-
3
; f = 1 kHz
C14
33 nF
10%
tan
25
10
-
3
; f = 1 kHz
C16
3.9 pF
10%
TC = 0
150 ppm/K; tan
30
10
-
4
; f = 1 MHz
C17
10 nF
10%
tan
25
10
-
3
; f = 1 kHz
C18
1.8 pF
10%
TC = 0
150 ppm/K; tan
30
10
-
4
; f = 1 MHz
C19
39 pF
10%
TC = 0
30 ppm/K; tan
10
10
-
4
; f = 1 MHz
C20
3.3 pF
10%
TC = 0
150 ppm/K; tan
30
10
-
4
; f = 1 MHz
C22
18 pF
5%
TC = 0
30 ppm/K; tan
10
10
-
4
; f = 1 MHz
C23
47 nF
10%
tan
25
10
-
3
; f = 1 kHz
C24
22 pF
5%
TC = 0
30 ppm/K; tan
10
10
-
4
; f = 1 MHz
C25
1 nF
10%
tan
25
10
-
3
; f = 1 kHz
L1
10 nH
10%
Q
min
= 50 to 450 MHz; TC = 25 to 125 ppm/K
L2
150
H
10%
Q
min
= 45 to 800 kHz; C
stray
1 pF
L3
220
H
10%
Q
min
= 45 to 800 kHz; C
stray
1 pF
L4
33 nH
10%
Q
min
= 45 to 450 MHz; TC = 25 to 125 ppm/K
L5
470
H
10%
Q
min
= 45 to 800 kHz; C
stray
1 pF
DESCRIPTION
SPECIFICATION
Type
one-port
Centre frequency
432.92 MHz
75 kHz
Maximum insertion loss
1.5 dB
Typical loaded Q
1600 (50
load)
Temperature drift
0.032 ppm/K
2
Turnover temperature
43
C
1997 Aug 12
19
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
LAYOUT OF PRINTED-CIRCUIT BOARD FOR AC APPLICATION
Fig.12 Printed-circuit board layout.
handbook, full pagewidth
MHA813
VCC
SAWR
C1
C3
R3
C16
L4
R2
L5
C2
C18
C24 C21
C14
C7
L2
UAA3202M
C13
COMP
POWER
DOWN
DATA
C20
C9
C10
L3
C11
C8
C19
C6
C4
C12
C25
R4
C23
C22
C17
L1
C5
b. Component side.
a. Copper side.
1997 Aug 12
20
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
PACKAGE OUTLINE
UNIT
A
1
A
2
A
3
b
p
c
D
(1)
E
(1)
e
H
E
L
L
p
Q
(1)
Z
y
w
v
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
mm
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
0.65
7.9
7.6
0.9
0.7
0.9
0.5
8
0
o
o
0.13
1.25
0.2
0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
1.03
0.63
SOT339-1
MO-150AE
93-09-08
95-02-04
X
w
M
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
1
10
20
11
y
0.25
pin 1 index
0
2.5
5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
A
max.
2.0
1997 Aug 12
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Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
"IC Package Databook" (order code 9398 652 90011).
Reflow soldering
Reflow soldering techniques are suitable for all SSOP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250
C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45
C.
Wave soldering
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1)
.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260
C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150
C within
6 seconds. Typical dwell time is 4 seconds at 250
C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300
C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320
C.
1997 Aug 12
22
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1997 Aug 12
23
Philips Semiconductors
Preliminary specification
Frequency Shift Keying (FSK) receiver
UAA3202M
NOTES
Internet: http://www.semiconductors.philips.com
Philips Semiconductors a worldwide company
Philips Electronics N.V. 1997
SCA55
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Printed in The Netherlands
547027/1200/01/pp24
Date of release: 1997 Aug 12
Document order number:
9397 750 02306