2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

CONTENTS

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING INFORMATION

7.1

Pinning

7.2

Pin description

FUNCTIONAL DESCRIPTION

8.1

RF receiver front-end and RF VCO

8.2

Channel filter and AGC

8.3

RF VCO

8.4

RF LO section

8.5

RF fractional-N synthesizer PLL

8.6

Clock PLL

8.7

Control

OPERATING MODES

9.1

Basic operating mode

9.2

AGC gain look-up table

9.3

RF PLL synthesizer

9.4

Clock PLL synthesizer

PROGRAMMING

10.1

Serial programming bus

10.2

Data format

10.3

LIMITING VALUES

THERMAL CHARACTERISTICS

DC CHARACTERISTICS

AC CHARACTERISTICS

SERIAL BUS TIMING CHARACTERISTICS

APPLICATION INFORMATION

PACKAGE OUTLINE

SOLDERING

18.1

Introduction to soldering surface mount
packages

18.2

Reflow soldering

18.3

Wave soldering

18.4

Manual soldering

18.5

Suitability of surface mount IC packages for
wave and reflow soldering methods

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

FEATURES

Low noise wide dynamic range for zero IF receivers

79 dB gain control range; in steps of 1 dB

Channel filters

96 dB voltage gain

Fully integrated fractional-N synthesizer with AFC
control capability

Fully integrated RF VCO with integrated supply voltage
regulator

Fully differential design to minimize crosstalk

Supply voltage from 2.4 to 3.3 V

3-wire serial interface bus

HVQFN24 package.

APPLICATIONS

WCDM-FDD receiver for GSM hand-portable equipment

Dual mode GSM/GPRS/EDGE/UMTS handset.

GENERAL DESCRIPTION

The UAA3580 is a BiCMOS integrated circuit receiver
intended for the Third Generation Partnership Project
(3GPP) specification for the Universal Mobile
Telecommunication System (UMTS).

The circuit is specially designed for the Frequency Division
Duplex (FDD) mode of the Wide Code Division Multiple
Access (WCDMA) that operates in the 2110 to 2170 MHz
band.

The UAA3580 contains the whole analog receive chain
from Radio Frequency (RF) Low Noise Amplifier (LNA) to
baseband IQ outputs including a channel filter, a complete
RF Phase-Locked Loop (PLL) with a fully integrated
Voltage Controlled Oscillator (VCO), and a clock PLL that
generates a programmable UMTS system clock from an
external 26 MHz reference signal.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

CCA

analog supply voltage

2.6

3.3

DDD

digital supply voltage

1.6

2.8

amb

ambient temperature

+70

TYPE

NUMBER

PACKAGE

VERSION

NAME

DESCRIPTION

UAA3580HN

HVQFN24

plastic, heatsink very thin quad flat package; no leads
24 terminals; body 4

0.90 mm

SOT616-1

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

7.2

Pin description

Table 1

HVQFN24 package

SYMBOL

PIN

DESCRIPTION

VCOGND

RF VCO ground

CCA(RF)

analog supply voltage for the RF receiver

RFGND

RF receiver ground

RFIP

RF positive input

RFIN

RF negative input

IFGND

IF section ground

RXCEN

receiver chip enable input

CCA(IF)

analog supply voltage for the IF section

differential receive baseband positive in-phase output

differential receive baseband negative in-phase output

differential receive baseband positive in-quadrature output

differential receive baseband negative in-quadrature output

DATA

serial bus data input

CLK

serial bus clock input

serial bus enable input

DDD

digital supply voltage

UMTSCLKO

UMTS system clock output

REXT

external charge pump biasing resistor connection

REFIN

reference clock input

CCA(SYN)

analog supply voltage for the synthesizer

CPCLKO

charge pump clock output

CCA(CP)

analog supply voltage for the charge pump section

RFCPO

RF charge pump output

CAPVCOREG

decoupling capacitor for the VCO regulator

die pad

ground

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

FUNCTIONAL DESCRIPTION

The receiver consists of an RF receiver front-end, an
RF VCO, a channel filter, Automatic Gain Control (AGC),
a RF fractional-N synthesizer PLL, a clock PLL, a
Power-up reset circuit and a 3-wire serial programming
bus.

8.1

RF receiver front-end and RF VCO

The front-end receiver converts the aerial RF signal from
WCMDA (2.11 to 2.17 GHz) band down to a Zero
Intermediate Frequency (ZIF). The first stage is a
differential low noise amplifier matched to 50

using an

external balun. The LNA is followed by an IQ down-mixer
which consists of two mixers in parallel but driven by
quadrature out-of-phase LO signals. The In phase (I) and
Quadrature phase (Q) ZIF signals are then low-pass
filtered, to provide protection from high frequency offset
interference, and fed into the channel filter.

8.2

Channel filter and AGC

The front-end zero IF I and Q outputs are applied to the
integrated low-pass channel filter with a provision for
4

8 dB gain steps in front of the filter. The filter is a

self-calibrated fifth-order low-pass filter with a cut-off
frequency around 2.4 MHz. Once filtered the zero IF
I and Q outputs are further amplified with provision for
47

1 dB steps and DC offset compensation. The zero IF

output buffer provides close rail-to-rail output signal.

8.3

RF VCO

The RF VCO is fully integrated and self-calibrated on
manufacturing tolerances. It consists of 16 different
frequency ranges that are selected internally, depending
on the frequency programmation. It covers the necessary
bandwidth of 4.22 to 4.34 GHz and is tuned via the RF
charge pump and external loop filter. An internal supply
voltage regulator using the pin CAPVCOREG as external
decoupling capacitor supplies the RF VCO and minimizes
parasitic coupling and pushing. The regulator and the RF
VCO are turned on by the RXCEN signal.

8.4

RF LO section

The RF LO section covering the 4.22 to 4.34 GHz band is
driven by the internal RF VCO module. It includes the LO
buffering for the RF PLL and a divide-by-two circuit to
generate the quadrature LO signals to drive the RX IQ
down-mixer.

8.5

RF fractional-N synthesizer PLL

A high performance RF fractional-N synthesizer PLL is
included on-chip which enables the frequency of the RF
VCO to be synthesized. The frequency is set via the 3-wire
serial programming bus.

The PLL is based on Sigma-Delta (

) fractional-N

synthesis that enables the required channel frequency,
including Automatic Frequency Control (AFC) from a free
running external 26 MHz GSM reference frequency, to be
obtained. Very low close in-phase noise is achieved which
allows a wider PLL loop bandwidth and a shorter settling
time. The programmable main dividers are controlled by a
second-order (

) modulus controller. They divide the RF

VCO signals down to frequencies of 26 MHz (in
programmable 12 Hz steps). Their phase is then
compared in a digital Phase/Frequency Detector (PFD) to
the 26 MHz reference clock signal. The phase error
information is fed back to the RF VCO via the charge pump
circuit that `sources' into or `sinks' current from the loop
filter capacitor, thus changing the VCO frequency so that
the loop is finally brought into phase-lock.

The RF synthesizer division range enables an external
reference frequency of 13 to 26 MHz to be used.

8.6

Clock PLL

The clock PLL is based on SD fractional-N synthesis that
allows the UMTS system clock, including AFC from a
non-corrected external 26 MHz GSM reference frequency,
to be obtained. The PLL comprises a fully integrated RC
VCO. The PLL output is a low harmonic content waveform,
the frequency of which can be programmed to
15.36, 30.72 or 61.44 MHz. The default value is
30.72 MHz.

8.7

Control

The control of the chip is done via the 3-wire serial bus and
pin RXCEN. At power-up the clock PLL section is
automatically enabled, the other sections are enabled
when the RXCEN signal is set HIGH (also via the 3-wire
bus). The power-up signal is detected on pin V

DDD

when

the voltage rises. The V

DDD

pin, if the supply voltage is

maintained, enables the programming parameters to be
retained in memory.

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

OPERATING MODES

9.1

Basic operating modes

The circuit can be powered up into different operating
modes, depending on the control bits RXON and SYNON,
via the 3-wire bus. This defines three main modes called
IDLE, SYN and RX mode.

The voltage level applied to pin RXCEN must be set HIGH
to enable the device. The VCO and the PLL sections are
enabled in SYN mode. In the RX mode every section is
enabled (receive part, VCO and PLL sections).

Table 2

Selection of operating mode

9.2

AGC gain look-up table

The AGC gain is set via the AGC[8:0] bits; see Table 3.

MODE

SYNON

RXON

IDLE

SYN

Table 3

AGC gain look-up table

AGC8

AGC7

AGC6

AGC5

AGC4

AGC3

AGC2

AGC1

AGC0

ATTENUATION FROM

MAXIMUM GAIN (dB)

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

AGC8

AGC7

AGC6

AGC5

AGC4

AGC3

AGC2

AGC1

AGC0

ATTENUATION FROM

MAXIMUM GAIN (dB)

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

The AGC[8:0] code required to program the AGC attenuation (AGC

att

) can be calculated from the following formulas:

AGC[8:0] = (511

AGC

att

)

if 0 < AGC

att

< 11

AGC[8:0] = (391

AGC

att

)

if 12 < AGC

att

< 19

AGC[8:0] = (271

AGC

att

)

if 20 < AGC

att

< 27

AGC[8:0] = (151

AGC

att

)

if 28 < AGC

att

< 35

AGC[8:0] = (95

AGC

att

)

if 36 < AGC

att

< 43

AGC[8:0] = (151

AGC

att

)

if 44 < AGC

att

< 51

AGC[8:0] = (95

AGC

att

)

if 52 < AGC

att

< 59

AGC[8:0] = (135

AGC

att

)

if 60 < AGC

att

< 67

AGC[8:0] = (79

AGC

att

)

if 68 < AGC

att

< 79

Where (X)

is the binary code of the integer X.

AGC8

AGC7

AGC6

AGC5

AGC4

AGC3

AGC2

AGC1

AGC0

ATTENUATION FROM

MAXIMUM GAIN (dB)

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

9.3

RF PLL synthesizer

The RF fractional-N synthesizer is set via the 3-wire bus
with the FRAC and CH chains. CH sets the integer divider
ratio and FRAC the fractional divider ratio. They both
provide the LO frequency in accordance with the following
equation:

Where

Where K

is the integer value of FRAC[21:0], N

is the

integer value of CH[8:0] and f

ref

is the external frequency

reference applied to pin REFIN.

Example: to obtain a f

RFLO

frequency of 2.14 GHz with an

error less than

PLL

must be set to 164 and K

frac(RX)

to 1290555 if the reference frequency is 26 MHz. It should
be noted that some particular frequencies can be obtained
in two ways; N

= x and K

frac(RX)

= 0.25 provides the

same frequency as N

= x

1 and K

frac(RX)

= 0.75

9.4

Clock PLL synthesizer

9.4.1

AFC

MODE

The clock PLL is based on the SD fractional-N synthesizer
that allows to derive the UMTS system clock including AFC
from a non-corrected external 26 MHz only GMS
reference. The clock PLL frequency with the AFC
correction word is given by the following equation:

Where

AFC represents the integer value of AFC[11:0] and f

ref

the external reference frequency applied to pin REFIN.

9.4.2

LOCK

PLL

MODES

The clock PLL synthesizer is controlled by bits CLKon and
CLKoff. At power-up the clock PLL synthesizer is
automatically on when pin RXCEN is set HIGH. The
control, done with CLKon, will be reset at the rising edge
of RXCEN. For application which do not require the UMTS
clock system, the clock PLL can be powered-down with bit
CLKoff set to logic 1.

Table 4

Clock mode

Notes

1. Hard power-down of the clock PLL done with RXCEN.

2. Power-down achieved via the 3-wire bus, reset by

RXCEN.

3. Power-down achieved via the 3-wire bus, no effect by

RXCEN in this mode. This mode will be reset if V

DDD

is not maintained.

4. X = don't care.

9.4.3

LOCK

PLL

OUTPUT DIVIDER

The clock PLL output divider ratio is set in accordance with
Table 5.

Table 5

Clock mode; note 1

Note

1. X = don't care.

RFLO

ref

-----------

frac(RX)

--------

1
2

---

CLKPLL

ref

AFC

-----------------------

AFC

231
512

----------

AFC

------------

RXCEN CLKon CLKoff

DESCRIPTION

CLKPLL synthesizer
enabled (default)

CLKPLL synthesizer
disabled; note 1

CLKPLL synthesizer
disabled; note 2

(4)

CLKPLL synthesizer
disabled; note 3

CLKoff

CLK1

CLK0

DESCRIPTION

UMTSCLKO output
disabled

clock divider ratio set to
default

clock divider ratio set to 2

clock divider ratio set to 4

clock divider ratio set to 8

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

10 PROGRAMMING

10.1

Serial programming bus

A simple 3-wire unidirectional serial bus is used to program
the circuit. The 3 lines are DATA, CLK and EN.

The data sent to the device is loaded in bursts framed
by EN. Programming clock edges are ignored until EN
goes active LOW. The programmed information is loaded
into the addressed latch when EN goes HIGH (inactive).
This is allowed when CLK is in either state without causing
any consequences to the data register. Only the last
21 bits serially clocked into the device are retained within
the programming register. Additional leading bits are
ignored, and no check is made on the number of clock
pulses.

The fully static CMOS design uses virtually no current
when the bus is inactive. It can always capture new
programming data even during Power-down of the
synthesizer.

10.2

Data format

Data is entered with the most significant bit first. The
leading bits make up the data field, while the trailing four
bits are an address field. The address bits are decoded on
the rising edge of EN. This produces an internal load pulse
to store the data in the address latch.

To ensure that data is correctly loaded on first power-up,
EN should be held LOW and only taken HIGH after having
programmed an appropriate register. To avoid erroneous
divider ratios, the pulse is inhibited during the period when
data is read by the frequency dividers. This condition is
guaranteed by respecting a minimum EN pulse width after
data transfer.

10.3

Register contents

Table 6

Table 7

Description of symbols used in Table 6

CONTROL BITS

ADDRESS

for test purposes only; all bits must be set to zero for normal operation; this is a forbidden address

FRAC[15:0]

SYNON

CH[8:0]

FR[21:16]

SYNON

AGC[8:0]

RXON

AFC[11:0]

CKO[1:0]

CLKoff

CLKon

SYMBOL

BITS

DESCRIPTION

SYNON

3-wire bus

RXON

3-wire bus

AGC

automatic gain control

integer division ratio for the RF PLL

FRAC

fractional division ratio for the RF PLL

AFC

automatic frequency control for the clock PLL

CLKoff

clock PLL disabled

CKO

integer division ratio for the clock PLL

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

Table 8

11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).

12 THERMAL CHARACTERISTICS

CONTROL

ADDRESS

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

DDD

digital supply voltage

0.3

+2.8

CCA

analog supply voltage

0.3

+3.3

tot

total power dissipation

300

amb

ambient temperature

+80

stg

storage temperature

+150

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from
junction to ambient

in free air; on a 4 layer PCB and
with soldered exposed die pad

K/W

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

13 DC CHARACTERISTICS
V

CCA

= 2.6 V; V

CCA(CP)

= 2.6 V;T

amb

= 25

C; unless otherwise specified.

Notes

1. Receive mode: All circuits are active.

2. Receive mode: All circuits are active with the clock PLL off (CLKoff = 1).

3. Synthesizer mode: RF PLL and clock PLL are active.

4. Standby mode: Clock PLL is active.

5. Sleep mode: RXCEN set LOW, DATA, CLK and EN are in high-impedance.

6. Receive mode: DC voltage supplied from the IC.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies

CCA

analog supply voltage

on pins V

CCA(RF)

, V

CCA(IF)

CCA(CP)

and V

CCA(SYN)

2.6

2.8

3.3

DDD

digital supply voltage

1.6

1.8

2.8

CCA(tot)

total analog supply current

receive mode; note 1

receive mode; note 2

synthesizer mode; note 3

standby mode; note 4

sleep mode; note 5

CCA(RF)

analog supply current for the RF
VCO section

CCA(IF)

analog supply current for the RX
section

CCA(SYN)

analog supply current for the
synthesizer

CCA(CP)

analog supply current for the
charge pump

0.9

DDD

digital supply current

1.1

Baseband IQ section; pins IN, IP, QP and QN

O(IQ)(CM)

IQ common mode output voltage

0.5(V

+ V

) or

0.5(V

+ V

); note 6

1.15

1.25

1.35

RF VCO section; pin CAPVCOREG

O(CAPVCOREG)

output voltage

CLKPLL section; pin UMTSCLKO

O(UMTSCLKO)

output voltage

0.8

Reference voltage; pin REXT

REXT

reference voltage for the charge
pump

ext

= 1.8 k

360

Control section; pins DATA, CLK, EN and RXON

HIGH-level input voltage

0.9

LOW-level input voltage

0.3

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

14 AC CHARACTERISTICS
V

CCA

= 2.6 V; T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

RF receiver inputs; pins RFIN and RFIP

i(RF)

RF input frequency

2.11

2.17

GHz

input resistance

170

input capacitance

input power matching

with external balun

noise figure

in receive mode with
maximum gain

3.2

1 dB compression point

in receive mode with
maximum gain

dBm

input referred 3rd-order
intercept point

in receive mode with
maximum gain;
interference 20 MHz
away from channel
bandwidth

dBm

input referred 2nd-order
intercept point

in receive mode with
maximum gain;
interferers 190 MHz away
from channel bandwidth

dBm

phase noise

at 15 MHz offset

135

dBc/Hz

Baseband IQ section; pins IP, IN, QP and QN

v(max)

maximum voltage gain

100

v(min)

minimum voltage gain

AGC

tot

total AGC range

step(AGC)

AGC gain step

AGC

tot(lin)

total AGC linearity

0.5

+0.5

v(IQ)

voltage gain mismatch
between the I and Q paths

0.5

quadrature phase error
between the I and Q paths

peak error

deg

o(max)

maximum output voltage per
pin

L(diff)

= 10 k

;

THD < 3%

0.75

o(max)

maximum output current per
pin

o(p-p)

= 1.75 V at 1 MHz;

L(diff)

= 10 k

;

L(diff)

= 20 pF

650

offset(diff)

differential output offset
voltage

+20

3dB

3 dB high-pass corner

frequency

2nd-order high-pass
frequency

kHz

3dB

3 dB low-pass corner

frequency

5th-order low-pass
frequency

2.25

2.4

2.55

MHz

(g)

group delay variation

100 kHz < f

< 2 MHz

260

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

LPF

LPF attenuation

= 5 MHz

= 10 MHz

= 15 to 60 MHz

RF synthesizer; pin RFCPO

RFLO

synthesizer frequency

2.11

2.17

GHz

comp(RF)

RF comparison frequency

MHz

PLL

frequency resolution

comp

= 13 to 26 MHz

0.05

ppm

comp

= 26 MHz

6.2

close-in-phase noise

at 2 kHz offset

dBc/Hz

sink

sink current

ext

= 1.8 k

; THD = 1%

170

200

230

source

source current

ext

= 1.8 k

; THD = 1%

170

200

230

o(CP)

charge pump output voltage

charge pump current
within specified range

0.4

CCA

0.4

PFD gain

ext

= 1.8 k

; THD = 1%

A/rad

leak(CP)

charge pump leakage current
in off state

over full charge pump
voltage range

Fractional-N synthesizer;

where

integer divider ratio

130

507

frac

fractional divider ratio

0.25

0.75

Integrated RF VCO; pin RFCPO

RF frequency

RFCPO

= 0 to 3.3 V

4.22

4.34

GHz

VCO

VCO gain

RFCPO

= 1.3 V

MHz/V

tune

tuning voltage

0.4

CCA

0.4

VCC

pushing

tbf

MHz/V

cal(VCO)

VCO calibration time

after RXON = LO

CLKPLL synthesizer; pin CPCLKO

CLKPLL

synthesizer frequency

CPCLKO

= 0 to 3.3 V

122.88

MHz

comp

comparison frequency

MHz

PLL

frequency resolution

ref

= 26 MHz

0.477

ppm

AFC

cor

AFC correction range

ppm

sink

sink current

ext

= 1.8 k

; THD = 1%

170

200

230

source

source current

ext

= 1.8 k

; THD = 1%

170

200

230

o(CP)

charge pump output voltage

charge pump current
within specified range

0.4

CCA

0.4

PFD gain

ext

= 1.8 k

; THD = 1%

A/rad

leak(CP)

charge pump leakage current
in off state

over full charge pump
voltage range

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

RFLO

ref

-----------

frac(RX)

--------

1
2

---

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

Fractional-N synthesizer;

where

integer divider ratio

AFC

fractional divider ratio

0.4512

0.4532

Integrated CLKPLL VCO; pin CPCLKO

VCO

CLKPLL frequency

CPCLKO

= 0 to 3.3 V

100

140

MHz

VCO

VCO gain

CPCLKO

= 1.3 V

MHz/V

tune

tuning voltage

0.4

CCA

0.4

Output CLKPLL buffer; pin UMTSCLKO

UMTSCLKO

frequency range

15.36

30.72

61.44

MHz

divider ratio

close-in-phase noise

at 2 kHz offset for
30.72 MHz

dBc/Hz

phase noise

at 3.84 MHz offset for
30.72 MHz

110

dBc/Hz

o(p-p)

output voltage (peak-to-peak
value)

= 10 k

Low noise crystal amplifier; pin REFIN

REF

reference frequency

MHz

i(REF)(rms)

input voltage (RMS value)

400

i(REF)

input resistance

REF

= 26 MHz

tbf

i(REF)

input capacitance

REF

= 26 MHz

tbf

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

CLKPLL

ref

AFC

------------------------

AFC

231
512

----------

AFC

------------

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

15 SERIAL BUS TIMING CHARACTERISTICS
V

CCA

= 2.6 V; V

CCA(CP)

= 2.6 V; V

DDD

= 1.6 V; T

amb

= 25

C; unless otherwise specified.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Serial clock; pin CLK

i(r)

input rise time

i(f)

input fall time

cyc

clock period

Enable; pin EN

d(START)

delay to rising clock edge

200

d(END)

delay from last falling clock edge

100

minimum inactive pulse width

400

su;EN

enable set-up time to next clock

200

Register serial input data; pin DATA

su;DATA

input data to clock set-up time

h;DATA

input data to clock hold time

handbook, full pagewidth

MGU575

tsu;DAT

td(START)

th;DAT

ti(f)

ti(r)

td(END)

tsu;EN

Tcyc

CLK

DATA

MSB

LSB

ADDRESS

Fig.3 Serial bus timing diagram.

2002

Oct

Philips Semiconductors

Objectiv

e specification

Wideband code division m

ultiple access

frequency division duple

x z
ero IF receiv

AA3580

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APPLICA

TION INFORMA

TION

handbook, full pagewidth

ATA

DATA

CLK

REXT

REFGND

FCA238

UAA3580

RXCEN

CAPVCOREG

RFCPO

CPCLKO

REFIN

UAA3581

TCEN

IFGND

LC MATCH AND

BIAS CHOKES

SAW

LC MATCH

differential to
single-ended

GSMCLKO

UMTSCLKO

REFIN

isolator

UAA3592

BATTERY

ceramic duplexer

antenna

or switch

ICTL

reg

det

DDD

CPGND

VCOTUNE

CAPVCOREG

VDDD

CCA(IF)

VCCA(RF)

VCOGND

RFGND

RFIP

RFIN

IFGND

CCA(CP)

CCA(SYN)

VCCA(RF)

VCCA(IF)

RFOP

RFON

RFGND

Fig.4 Application diagram.

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

17 PACKAGE OUTLINE

0.5

0.2

UNIT

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

4.1
3.9

2.25
1.95

4.1
3.9

2.25
1.95

2.5

0.30
0.18

0.05
0.00

0.05

0.1

DIMENSIONS (mm are the original dimensions)

SOT616-1

MO-220

- - -

0.5
0.3

0.1

0.05

2.5

5 mm

scale

SOT616-1

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm

(1)

max.

detail X

y1 C

01-08-08
02-10-22

terminal 1
index area

1/2

(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

(1)

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

18 SOLDERING

18.1

Introduction to soldering surface mount
packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.

18.2

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 220

C for

thick/large packages, and below 235

C for small/thin

packages.

18.3

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

18.4

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

18.5

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, HBGA, LFBGA, SQFP, TFBGA

not suitable

suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS

not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

2002 Oct 30

Philips Semiconductors

Objective specification

Wideband code division multiple access
frequency division duplex zero IF receiver

UAA3580

19 DATA SHEET STATUS

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

LEVEL

DATA SHEET

STATUS

(1)

PRODUCT

STATUS

(2)(3)

DEFINITION

Objective data

Development

This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Preliminary data Qualification

This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

III

Product data

Production

This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).

20 DEFINITIONS

Short-form specification

The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition

Limiting values given are in

accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information

Applications that are

described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

21 DISCLAIMERS

Life support applications

These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes

Philips Semiconductors

reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status `Production'), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.

SCA74

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Philips Semiconductors a worldwide company

Contact information

For additional information please visit http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

Printed in The Netherlands

403506/02/pp

Date of release:

2002 Oct 30

Document order number:

9397 750 10632

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UAA3580HN

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UAA3580HN