1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

FEATURES

Line interface

Low DC line voltage; operates down to 1.2 V (excluding
polarity guard)

Voltage regulator with adjustable DC voltage

DC mask for voltage or current regulation (CTR21)

Line current limitation for protection

Electronic hook switch control input

Transmit amplifier with:

Symmetrical inputs

Fixed gain

Large signal handling capability.

Receive amplifier with fixed gain

Transmit and receive amplifiers Automatic Gain Control
(AGC) for line loss compensation.

General purpose switches

Two switches with open-collector.

3-wire serial bus interface

Allows control of:

DC mask (voltage or current regulation)

Receive amplifier mute function

AGC:

On/off

Slope

start

line current.

The state of the general purpose switches

Global power-down mode.

Supply

Operates with external supply voltage from 3.0 to 5.5 V.

APPLICATIONS

Cordless base stations

Mains or battery-powered telephone sets.

GENERAL DESCRIPTION

The UBA1706 is a BiCMOS integrated circuit intended for
use in mains-powered telecom terminals. It performs all
speech and line interface functions, DC mask for voltage
or current regulation and electronic hook switch control.
The device also includes general purpose switches.

Most of the characteristics are programmable via a 3-wire
serial bus interface.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

UBA1706TS

SSOP24

plastic shrink small outline package; 24 leads; body width 5.3 mm

SOT340-1

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

QUICK REFERENCE DATA

line

= 15 mA; V

= 3.3 V; R

SLPE

= 10

; AGC pin connected to GND; Z

line

= 600

; Z

SET

= 619

; EHI = HIGH;

f = 1 kHz; T

amb

= 25

C; bit AGC at logic 1, all other configuration bits at logic 0; measured in the test circuit of Fig.14;

unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

supply voltage

3.0

5.5

current consumption from pin V

normal operation; bit PD = 0

2.2

3.2

power-down mode; bit PD = 1

110

150

line

line current operating range

normal operation

140

with reduced performance

DC line voltage

2.7

3.0

3.3

REGC

DC mask slope in current regulation
mode

line

> 35 mA (typical);

LVI

= 1 M

; R

RGL

= 7.15 k

;

bit CRC = 1

1.4

v(trx)

voltage gain

transmit amplifier from TXI to LN

TXI

= 50 mV (RMS)

10.6

11.6

12.6

receive amplifier from RXI to RXO V

RXI

= 2 mV (RMS)

36.9

37.9

38.9

v(trx)

gain control range for transmit and
receive amplifiers with respect to
I

line

= 15 mA

line

= 90 mA

6.5

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

PINNING

SYMBOL

PIN

DESCRIPTION

positive line terminal

REG

line voltage regulator decoupling

LVI

negative line voltage sense input

RGL

reference for current regulation mode

LCC

line current control output

CST

input for stability capacitor

RXO

receive amplifier output

AGC

automatic gain control/line loss
compensation adjustment

RXI

receiver amplifier input

EHI

electronic hook switch control input

DATA

serial bus data input

programming serial bus enable input

CLK

serial bus clock input

TXI

inverted transmit amplifier input

TXI+

non-inverted transmit amplifier input

n.c.

not connected

SWI2

NPN open-collector output 2

SWI1

NPN open-collector output 1

GND

ground reference

n.c.

not connected

supply voltage

n.c.

not connected

n.c.

not connected

SLPE

connection for slope resistor

Fig.2 Pin configuration.

handbook, halfpage

UBA1706

FCA031

REG

LVI

RGL

LCC

CST

RXO

AGC

RXI

EHI

DATA

SLPE

n.c.

VCC

n.c.

GND

SW1

SW2

n.c.

TXI+

TXI-

CLK

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

FUNCTIONAL DESCRIPTION

All data given in this chapter consists of typical values,
except when otherwise specified.

Supply (pins V

and GND; bit PD)

The UBA1706 must be supplied with an external stabilized
voltage source across pins V

and GND.

Without any signal and without any general purpose switch
selected, the internal current consumption is 2.2 mA at
V

= 3.3 V. Each selected switch (pins SWI1 or SWI2)

increases the current consumption by 600

To drastically reduce current consumption, the UBA1706
is provided with a power-down mode controlled by bit PD.
When bit PD is at logic 1, the current consumption from
V

becomes 110

A. In the power-down mode, the serial

interface is the only function which remains active.

Line interface

CHARACTERISTICS

(

PINS

LN, SLPE, REG, CST, LVI,

LCC, RGL

AND

GND;

BIT

CRC)

The IC generates a stabilized reference voltage (V

ref

)

across pins LN and SLPE. This reference voltage is equal
to 2.9 V, is temperature compensated and can be adjusted
by means of an external resistor (R

). The reference

voltage can be increased by connecting the R

resistor

between pins REG and SLPE (see Fig.3).

The voltage at pin REG is used by the internal regulator to
generate the stabilized reference voltage and is decoupled
by a capacitor (C

REG

) which is connected to GND. This

capacitor, converted to an equivalent inductance
(see Section "Set impedance") realizes the set impedance
conversion from its DC value (R

SLPE

) to its AC value

SET

in the audio frequency range). Figure 4 illustrates

the reference voltage supply configuration. As can be seen
from Fig.4, part of the line current flows into the Z

SET

impedance network and is not sensed by the UBA1706.
Therefore, using the R

resistor to change the value of

the reference voltage will also modify all parameters
related to the line current such as:

The AGC

The DC mask management

The low voltage area characteristics.

In the same way, changing the value of Z

SET

also affects

the characteristics. The IC has been optimized for
V

ref

= 2.9 V and Z

SET

= 619

The IC regulates the line voltage at pin LN, which can be
calculated as follows:

Where:

line

= line current

ZSET

= current flowing through Z

SET

I* = current consumed between LN and GND
(approximately 100

A).

The preferred value for R

SLPE

is 10

. Changing R

SLPE

will

affect more than the DC characteristics; it also influences
the transmit gain, the gain control characteristics, the
sidetone level and the maximum output swing on the line.

Nevertheless, for compliance with CTR21, 8.66

is the

optimum value for R

SLPE

Fig.3 Reference voltage adjustment with R

(1) Influence of R

on V

ref

(2) V

ref

without influence of R

handbook, halfpage

8.5

2.5

(1)

(2)

MGK706

3.5

4.5

6.5

5.5

7.5

Vref

(V)

RVA (

)

ref

SLPE

line

ZSET

line

ZSET

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

The DC line current flowing into the set is determined by
the exchange supply voltage (V

exch

), the feeding bridge

resistance (R

exch

), the DC resistors of the telephone line

line

) and the set (R

SET

), the reference voltage (V

ref

) and

the voltage introduced by the transistor (TN

) used as

line interrupter (see Fig.5).

With a line current below I

low

(8 mA with Z

SET

= 619

), the

internal reference voltage (V

ref

) is automatically adjusted

to a lower value. This means that several sets can operate
in parallel with DC line voltages (excluding the polarity
guard) down to 1.2 V. With a line current below I

low

, the

circuit has limited transmit and receive levels. This is called
the low voltage area.

Figure 6 shows in more detail how the UBA1706, in
association with some external components, manages the
line interrupter (TN

external transistor).

In on-hook conditions (voltage at pin EHI is LOW), the
voltage at pin LCC is pulled up to the supply voltage level
(V

) to turn off transistor TP

DARL

. As a result, because of

resistor R

, transistors TN

and TN

ON-HOOK

are

switched off. Transistor TN

ON-HOOK

disconnects resistor

LVI

from the LN

line terminal to guarantee a high

on-hook impedance.

In off-hook conditions (voltage at pin EHI is HIGH), an
operational amplifier drives (at pin LCC) the base of
transistor TP

DARL

, which forms a current amplifier

structure in association with TN

. The line current flows

through transistor TN

. Transistor TN

ON-HOOK

is forced

into deep saturation. A virtual ground is created at pin LVI
because of the operational amplifier. A DC current (I

LVI

) is

sourced from pin LVI into the R

LVI

resistor to generate a

voltage source. Thus, the voltage across pins GND and
LN

becomes:

(TN

) = R

LVI

+ V

(TN

ON-HOOK

)

LVI

The voltage V

line

across line terminals LN+ and LN

can

be calculated as follows:

line

ref

+ R

SLPE

line

ZSET

) + V

(TN

)

Where:

line

= line current

ZSET

= current flowing through Z

SET

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

The UBA1706 offers the possibility to choose two kinds of
regulations for the DC characteristic between line
terminals LN+ and LN

(see Fig.7):

Voltage regulation mode

Current regulation mode.

The regulation mode is selected by bit CRC via the serial
interface.

The DC mask regulation is realised by adjusting the DC
voltage V

(TN

) across pin GND and line terminal LN

as a function of the line current.

Voltage regulation mode

In the voltage regulation mode (bit CRC at logic 0), the
V

(TN

) voltage is fixed by means of a 200 nA DC

constant current I

LVIV

flowing through R

LVI

Fig.7

General form of the DC mask as a function
of the regulation mode.

(1) Low voltage area.

(2) Small slope (determined by R

SLPE

(3) Small slope (dashed line; determined by R

SLPE

) in voltage

regulation mode.

High slope (full line; determined by R

SLPE

, R

LVI

and R

RGL

) in

current regulation mode.

(4) Current limitation.

handbook, halfpage

MGK710

Vline

Iline

Iprot

(4)

Iknee

Ilow

(1)

(2)

(3)

Therefore, V

(TN

)

LVI

LVIV

= 200 mV in a typical

application (see Fig.15).

The slope

line

of the V

line

, I

line

characteristic is

REGV

SLPE.

Current regulation mode

In current regulation mode (bit CRC at logic 1), when the
line current is lower than I

knee

= 35 mA (with

SET

= 619

), V

(TN

) is fixed by means of a 200 nA

DC constant current I

LVIV

flowing through R

LVI

. When the

line current is higher than 35 mA, an additional current
(proportional to the line current) flows through R

LVI

. As a

result, TN

works as a DC voltage source increasing with

the line current. V

(TN

) can be calculated as follows:

Where:

line

= line current

RGL

= resistor connected at pin RGL.

In a typical application (see Fig.15), the slope

line

of the V

line

, I

line

characteristic is determined by the ratio of

the resistors connected at pins SLPE, LVI and RGL, as
follows:

Current limitation

Whatever the selected mode is, the line current is limited
to approximately 145 mA; this current is sensed on SLPE.
For this purpose, the external Zener diode must be
connected between pins LN and SLPE. The speech
function no longer operates in this condition.

LECTRONIC HOOK SWITCH CONTROL

(

EHI)

The electronic hook switch input (EHI) controls the state of
transistor TP

DARL

. When the voltage applied at pin EHI is

LOW, transistor TP

DARL

is turned off. The voltage at

pin LCC is pulled up to supply voltage (V

). Transistors

and TN

ON-HOOK

are also turned off by means of a

pull-down resistor (R

). When the voltage applied at

pin EHI is HIGH, transistor TP

DARL

is driven by the

operational amplifier at pin LCC and the regulation mode
selected is operating. An internal 165 k

pull-up resistor is

connected between pins LCC and V

(

)

LVI

SLPE

RGL

----------------

line

knee

(

)

LVIV

REGC

SLPE

LVI

SLPE

RGL

----------------

1400

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

Input EHI can also be used for pulse dialling or register
recall (timed loop break). During line breaks (the voltage at
pin EHI is LOW or open-circuit), the voltage regulator is
switched off and the capacitor at pin REG is internally
disconnected to prevent its discharge. As a result, the
voltage stabilizer will have negligible switch-on delay after
line interruptions. This minimizes the contribution of the IC
to the current waveform during pulse dialling or register
recall.

When the UBA1706 is in power-down mode (bit PD at
logic 1), transistor TP

DARL

is forced off whatever the

voltage applied at pin EHI.

ET IMPEDANCE

In the audio frequency range, the dynamic impedance
between pins LN and GND (illustrated in Fig.8) is mainly
determined by the Z

SET

impedance. The impedance

introduced by the external TN

transistor connected

between pins GND and LN

is negligible.

RANSMIT AMPLIFIER

(

PINS

TXI+

AND

TXI

)

The UBA1706 has symmetrical transmit inputs TXI+ and
TXI

. The input impedance between pins TXI+ or TXI

and

GND is 21 k

. The voltage gain from pins TXI+ or TXI

pin LN is set at 11.6 dB with 600

line load (Z

line

) and

619

set impedance. The inputs are biased at

1.4 V, with V

representing the diode voltage.

AGC is provided on this amplifier for line loss
compensation.

ECEIVE AMPLIFIER

(

PINS

RXI

AND

RXO;

BIT

RXM)

The receive amplifier (see Fig.9) has one input (RXI) and
one output (RXO). The input impedance between
pins RXI and GND is 21 k

The rail-to-rail output stage is designed to drive a 500

peak current. The output impedance at pin RXO is
approximately 100

The voltage gain from pin RXI to pin RXO is set at 37.9 dB.
This gain value compensates typically the attenuation of
the anti-sidetone network (see Fig.10). The output and the
input are biased at 2

1.4 V.

AGC is provided on this amplifier for line loss
compensation. This amplifier can be muted by activating
the receive mute function (bit RXM at logic 1).

Fig.8

Equivalent impedance between
pins LN and GND.

= C

REG

SLPE

= internal resistance = 35 k

handbook, halfpage

GND

SLPE

RSLPE

CREG

REG

ZSET

4.7

619

Vref

LEQ

MGL215

Fig.9 Receive amplifier.

Bit names are given in italics.

handbook, full pagewidth

FCA035

RXM

2Vd

from AGC

RXI

RXO

UBA1706

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

IDETONE SUPPRESSION

The UBA1706 anti-sidetone network comprising
Z

SET

//Z

line

, R

ast1

, R

ast2

, R

ast3

, R

SLPE

and Z

bal

(see Fig.10)

suppresses the transmitted signal in the received signal.
Maximum compensation is obtained when the following
conditions are fulfilled:

SLPE

ast1

= Z

SET

ast2

+ R

ast3

)

bal

= k

line

The scale factor `k' is chosen to meet the compatibility with
a standard capacitor from the E6 or E12 range for Z

bal

In practice, Z

line

varies considerably with the line type and

the line length.

ast2

ast3

SLPE

(

)

(

)

ast1

SLPE

(

)

--------------------------------------------------------------------

Therefore, the value chosen for Z

bal

should be for an

average line length, which gives satisfactory sidetone
suppression with short and long lines.

The suppression also depends on the accuracy of the
match between Z

bal

and the impedance of the average

line.

The anti-sidetone network for the UBA1706 (see Fig.15)
attenuates the receiving signal from the line by 38 dB
before it enters the receiving amplifier. The attenuation is
almost constant over the whole audio frequency range.
A Wheatstone bridge configuration (see Fig.11) may also
be used.

More information on the balancing of an anti-sidetone
bridge can be obtained in our publication

"Applications

Handbook for Wired Telecom Systems, IC03b".

Fig.10 Equivalent circuit of UBA1706 anti-sidetone bridge.

handbook, full pagewidth

MGL216

ZRXI

RXI

Rast1

Rast3

Rast2

SLPE

RSLPE

GND

Zline

ZSET

Zbal

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

Fig.11 Equivalent circuit of an anti-sidetone network in a Wheatstone bridge configuration.

handbook, full pagewidth

MGL217

ZRXI

RXI

Zbal

Rast1

SLPE

RSLPE

GND

Zline

ZSET

UTOMATIC GAIN CONTROL

(

AGC;

BITS

RAGC1,

RAGC2, SAGC

AND

AGC)

The UBA1706 performs automatic line loss compensation.
The AGC varies the gain of the transmit amplifier and the
gain of the receive amplifier in accordance with the DC line
current. The control range is 6.5 dB (which corresponds
roughly to a line length of 5.5 km for a 0.5 mm diameter
twisted-pair copper cable with a DC resistance of
176

/km and an average attenuation of 1.2 dB/km).

When the line current is greater than I

stop

, the voltage

gains are minimum. When the line current is less than I

start

the voltage gains are maximum.

When the AGC pin is connected to pin GND, the start line
current (I

start

) can be chosen between 22.5 and 29.5 mA

via bits RAGC1 and RAGC2 through the serial interface.
Two values for the I

stop

start

ratio (slope of the AGC) are

possible via bit SAGC through the serial interface. When
bit SAGC is at logic 0 then I

stop

= 2.7

start

(optimized for

voltage regulation mode). When SAGC is at logic 1 then
I

stop

= 1.9

start

(optimized for current regulation mode).

An external resistor R

AGC

(connected between pins GND

and AGC) enables the I

start

and I

stop

line currents to be

increased (the ratio between I

start

and I

stop

is not affected

by this external resistor). Therefore, internal and external
adjustments of the AGC allow optimization of the IC for
many configurations of exchange supply voltage and
feeding bridge resistance.

Part of the line current flows into the Z

SET

impedance

network. The IC has been optimized for Z

SET

= 619

Changing this 619

value slightly modifies I

stop

and I

start

line currents as well as the value of the two AGC slopes.

The AGC function can be disabled by setting the AGC bit
to logic 0 via the serial interface or by leaving pin AGC
open-circuit. In this case, both of the voltage gains are
maximum.

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

General purpose switches (pins SWI1 and SWI2; bits
SWC1 and SWC2)

The UBA1706 is equipped with two general purpose
open-collector switches, which short circuit pins SWI1 and
SWI2 to ground. These switches are controlled by bits
SWC1 and SWC2, respectively, and have an operating
voltage limited to 12 V. The outputs have to be current
biased. For a bias current between 2 and 20 mA, the
AC impedance is 30

maximum.

Serial interface (pins DATA, CLK and EN)

A simple 3-wire unidirectional serial bus is used to program
the circuit. The three wires of the bus are EN, CLK and
DATA. The data sent to the device is loaded in bursts
framed by EN. Programming clock edges (falling edges)
and their appropriate data bits are ignored until EN goes
HIGH. The programmed information is loaded into the
addressed register when EN returns to LOW or left
open-circuit.

During normal operation, EN should be kept LOW. Only
the last seven bits serially clocked into the device are
retained within the programming register.

Additional leading bits are ignored and no check is made
on the number of clock pulses. New programming data can
always be captured during global power-down (bit PD at
logic 1).

Data is entered with the most significant bit first. The
leading six bits make up the data field (bits D0 to D5) while
the trailing two bits are the address field (bits ADO and
AD1). The first bit entered is D5, the last bit AD0. This
organisation allows the transmission of only the number of
bits of the addressed register.

Figure 13 shows the serial timing diagram. Table 1 gives
the list of registers.

When the supply voltage V

drops below 2.5 V, all

register files are set to the initial state (see Table 1)
defined by the power-up reset. At start-up, the circuit is in
power-down mode.

When the IC is used in a noisy environment, it is advised
to periodically refresh the content of registers.

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

Table 1

Notes

1. For full software compatibility, the registers have the same addresses as for the UBA1707.

2. See Section "Automatic gain control (pin AGC; bits RAGC1, RAGC2, SAGC and AGC)".

BIT

NAME

FUNCTION

POLARITY

DATA

ADDRESS

STATE AT

POWER-UP

RESET

Register 0: general purpose switches state and DC mask regulation mode

SWC1

SWI1 output connection

0: SWI1 switched-off

(AD1, AD0) = (0,0)

1: SWI1 switched-on

SWC2

SWI2 output connection

0: SWI2 switched-off

1: SWI2 switched-on

unused

must be set to logic 0

unused

must be set to logic 0

CRC

current regulation mode

0: voltage regulation

1: current regulation

Register 1: automatic gain control

RAGC1

AGC range selection 1

(AD1, AD0) = (0,1)

RAGC2

AGC range selection 2

SAGC

AGC slope selection

0: 2.7 type slope; note 2

1: 1.9 type slope; note 2

AGC

line loss compensation mode

0: AGC inhibited

1: AGC enabled

Register 2

unused, in case of programming register 2 data must be set to: 000100 (D5; D0)

(AD1, AD0) = (1,0)

Register 3: mute functions and power-down

unused

must be set to logic 1

(AD1, AD0) = (1,1)

RXM

receive amplifier mute

0: amplifier enabled

1: amplifier muted

reduced consumption mode

0: normal operating mode

1: power-down mode

unused

must be set to logic 1

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

supply voltage

GND

0.4 5.5

positive continuous line voltage on pin LN

GND

0.4 12.0

repetitive line voltage during switch-on or
line interruption

GND

0.4 13.2

SWIn

voltage on pins SWI1 and SWI2

continuous

GND

0.4 12.0

during switching

GND

0.4 13.2

n(max)

maximum voltage on all other pins

GND

0.4 V

+ 0.4

current sunk by pin LN

see Fig.12

150

SWIn

continuous current sunk by pins SWI1 and
SWI2

bit SWCn = 1

tot

total power dissipation

amb

= 75

C; see Fig.12

454

stg

IC storage temperature

+125

amb

ambient temperature

+75

junction temperature

+125

SYMBOL

PARAMETER

CONDITIONS

VALUE

UNIT

th(j-a)

thermal resistance from junction to ambient in free air

100

K/W

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

CHARACTERISTICS

line

= 15 mA; V

= 3.3 V; R

SLPE

= 10

; AGC pin connected to GND; Z

line

= 600

; Z

SET

= 619

; EHI = HIGH;

f = 1 kHz; T

amb

= 25

C; bit AGC at logic 1, all other configuration bits at logic 0; measured in test circuit of Fig.14;

unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply (pins V

and GND; bit PD)

supply voltage

3.0

5.5

current consumption from
pin V

2.2

3.2

CC(pd)

current consumption from
pin V

in power-down mode

bit PD = 1

110

150

Line interface (pins LN, SLPE and REG)

CHARACTERISTICS

ref

stabilized voltage between
pins LN and SLPE

line

= 11 to 140 mA

2.6

2.9

3.2

DC line voltage between pins
LN and GND

line

= 2 mA

1.2

line

= 4 mA

1.8

line

= 15 mA

2.7

3.0

3.3

line

= 140 mA

4.35

LN(Rext)

DC line voltage between pins
LN and GND with an external
resistor R

VA(SLPE

REG)

= 8 k

4.5

LN(T)

DC line voltage variation with
temperature referenced to
25

amb

25 to +75

8.0

Masks regulation (pins LCC, LVI, CST and RGL; bit CRC)

CHARACTERISTICS

LCC(max)

maximum current sunk by
pin LCC

500

int(LCC)

internal resistance between
pins V

and LCC

165

Voltage regulation mode

LVIV

current sourced from pin LVI

bit CRC = 0

200

Current regulation mode

knee

start line current for current
regulation mode

bit CRC = 1

REGC

DC mask slope in current
regulation mode

line

> I

knee

; R

LVI

= 1 M

;

RGL

= 7.15 k

; bit CRC = 1

1.4

Current limitation

prot

current limitation level

145

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

Electronic hook-switch control (pin EHI)

HIGH-level input voltage

2.3

+ 0.4

LOW-level input voltage

= 3.0 to 5.5 V

GND

0.4

0.3V

bias

input bias current

input level = HIGH

Transmit amplifier (pins TXI+, TXI

and LN)

input impedance

between pins TXI+ and
GND or TXI

and GND

between pins TXI+ and TXI

- -

v(TX)

voltage gain from TXI+/TXI

to LN

TXI

= 50 mV (RMS)

10.6

11.6

12.6

v(TX)(f)

voltage gain variation with
frequency referenced to 1 kHz

f = 300 to 3400 Hz

0.3

v(TX)(T)

voltage gain variation with
temperature referenced to
25

amb

25 to +75

0.3

CMRR

common mode rejection ratio

PSRR

power supply rejection ratio

LN(max)(rms)

maximum sending signal
(RMS value)

line

= 15 mA; THD = 2%

1.2

1.4

line

= 4 mA; THD = 10%

0.26

iTX(max)(rms)

maximum transmit input
voltage (RMS value) for
2% THD on pin LN

line

= 15 mA

0.35

line

= 90 mA

0.75

no(LN)

noise output voltage at pin LN pins TXI+ and TXI

short-circuited through
200

in series with 10

psophometrically weighted
(P53 curve)

dBmp

Receive amplifier (pins RXI and RXO; bit RXM)

input impedance between
pins RXI and GND

v(RX)

voltage gain from RXI to RXO

RXI

= 2 mV (RMS)

36.9

37.9

38.9

v(RX)(f)

voltage gain variation with
frequency referenced to 1 kHz

f = 300 to 3400 Hz

0.2

v(RX)(T)

voltage gain variation with
temperature referenced to
25

amb

25 to +75

0.3

PSRR

power supply rejection ratio

THD

total harmonic distortion

RXI

= 2 mV (RMS)

0.03

RXI

= 12.5 mV (RMS)

RXI

= 19.5 mV (RMS);

line

= 90 mA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

no(RXO)(rms)

noise output voltage at
pin RXO (RMS value)

RXI open-circuit;
psophometrically weighted
(P53 curve)

dBVp

v(RX)(m)

voltage gain reduction from
pin RXI to RXO when muted

RXI

= 10 mV (RMS);

bit RXM = 1

Automatic gain control (pin AGC; bits RAGC1, RAGC2, SAGC and AGC)

v(trx)

gain control range for transmit
and receive amplifiers with
respect to I

line

= 15 mA

line

= 90 mA

6.5

start

highest line current for
maximum gain

bits RAGC1 = 1;
RAGC2 = 1

22.5

bits RAGC1 = 1;
RAGC2 = 0

bits RAGC1 = 0;
RAGC2 = 1

bits RAGC1 = 0;
RAGC2 = 0

29.5

stop

lowest line current for
minimum gain when
I

start

= 23 mA

bits SAGC = 0; RAGC1 = 1;
RAGC2 = 1

bits SAGC = 1; RAGC1 = 1;
RAGC2 = 1

v(trxoff)

gain variation for transmit and
receive amplifiers when AGC
is off

bit AGC = 0;
I

line

= 15 to 140 mA

0.2

Switches (pins SWI1 and SWI2; bits SWC1 and SWC2)

i(off)

AC impedance between pins
SWIn and GND when not
selected

bit SWCn = 0

700

i(on)

AC impedance between pins
SWIn and GND when
selected

2 mA < I

SWIn

< 20 mA;

bit SWCn = 1

Serial interface (pins DATA, CLK and EN)

HIGH-level input voltage

2.3

+ 0.4

LOW-level input voltage

= 3 to 5.5 V

GND

0.4

0.3V

bias

input bias current

input level = HIGH

input capacitance at pins
DATA, CLK and EN

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

1999

Jun

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

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TEST AND APPLICA

TION INFORMA

TION

handbook, full pagewidth

FCA037

GND

SWI1

EHI

SWI2

DATA

CLK

LCC

CST

REG

LVI

AGC

RGL

TXI

VCC

ICC

RXI

RXO

from

microcontroller

UBA1706

CLVI
470 pF

Cline
100

CEMC
10 nF

CREG
4.7

RLVI
1 M

RRGL
7.15 k

SLPE

RSLPE
10

ZSET

619

Zline
600

CRXI

220 nF

CCST

27 pF

VRXI

TNON-HOOK
MPSA42

TPDARL
MPSA92

100 k

RON-HOOK

Dprot

1N4148

RPD
20 k

DSW

1N4148

TNSW

BUX86

VVCC

VLN

Iline

VTXI

CVCC
10

CLCC
6.8 pF

Fig.14 Test circuit.

1999

Jun

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

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handbook, full pagewidth

FCA038

SWI2

SWI1

RXI

RXO

LCC

CST

REG

LVI

AGC

RGL

GND

TXI

VCC

ICC

SLPE

EHI

DATA

CLK

UBA1706

CRXI
100 nF

CLVI

(2)

470 pF

CVCC
10

CEMC

(3)

10 nF

CREG
4.7

CRXO

RSLPE

Rast3
392

RLVI
1 M

RRGL
7.15 k

ZSET
619

Zbal

Rast2

3.92 k

Rast1

260 k

BZX79C8V2

CTXIP

100 nF

CTXIM

100 nF

CCST

27pF

TNON-HOOK
MPSA42

TPDARL
MPSA92

100 k

RON-HOOK

Dprot

1N4148

RPD
20 k

DSW

1N4148

TNSW

BUX86

(MPSA42

(1)

)

VVCC

VLN

BRIDGE

BAS11

a/b

b/a

BOD
BR211-240

CLCC

(4)

6.8 pF

C
R
O
C
O
N

R
O

L
L

E
R

Fig.15 Typical application.

(1) In case of low line current in voltage regulation mode.

(2) Only required in current regulation mode.

(3) To improve EMC performance; necessary for stability.

(4) To improve stability only in current regulation mode.

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

SOLDERING

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"Data Handbook IC26; Integrated Circuit Packages"

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250

C. The top-surface temperature of the

packages should preferable be kept below 230

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

For packages with leads on two sides and a pitch (e):

larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

For packages with leads on four sides, the footprint must
be placed at a 45

angle to the transport direction of the

printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320

1999 Jun 04

Philips Semiconductors

Objective specification

Cordless telephone line interface

UBA1706

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

"Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE

REFLOW

(1)

BGA, SQFP

not suitable

suitable

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO

not recommended

(5)

suitable

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

SCA

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

Philips Semiconductors a worldwide company

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399

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Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

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Tel. +48 22 612 2831, Fax. +48 22 612 2327

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Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

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Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
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Belgium: see The Netherlands

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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
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Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,
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Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
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Ireland: Newstead, Clonskeagh, DUBLIN 14,
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Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557

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Printed in The Netherlands

465008/02/pp28

Date of release: 1999 Jun 04

Document order number:

9397 750 05276

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UBA1706

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UBA1706