DATA SHEET
Preliminary specification
Supersedes data of 1999 Dec 20
File under Integrated Circuits, IC01
2000 Apr 18
INTEGRATED CIRCUITS
UDA1330ATS
Low-cost stereo filter DAC
2000 Apr 18
2
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1330ATS
FEATURES
General
Low power consumption
Power supply voltage from 2.7 to 5.5 V
Selectable control via L3 microcontroller interface or via
static pin control
System clock frequencies of 256f
s
, 384f
s
and 512f
s
selectable via L3 interface or 256f
s
and 384f
s
via static
pin control
Supports sampling frequencies (f
s
) from 16 to 55 kHz
Integrated digital filter plus non inverting
Digital-to-Analog Converter (DAC)
No analog post filtering required for DAC
Slave mode only applications
Easy application
Small package size (SSOP16)
TTL tolerant input pads
Pin and function compatible with the UDA1320ATS.
Multiple format input interface
L3 mode: I
2
S-bus, MSB-justified or LSB-justified
16, 18 and 20 bits format compatible
Static pin mode: I
2
S-bus and LSB-justified
16, 18 and 20 bits format compatible
1f
s
input format data rate.
DAC digital sound processing
Digital logarithmic volume control in L3 mode
Digital de-emphasis for 32, 44.1 and 48 kHz sampling
frequencies in L3 mode or 44.1 kHz sampling frequency
in static pin mode
Soft mute control both in static pin mode and L3 mode.
Advanced audio configuration
Stereo line output (volume control in L3 mode)
High linearity, wide dynamic range and low distortion.
APPLICATIONS
PC audio applications
Car radio applications.
GENERAL DESCRIPTION
The UDA1330ATS is a single-chip stereo DAC employing
bitstream conversion techniques.
The UDA1330ATS supports the I
2
S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits and the LSB-justified
serial data format with word lengths of 16, 18 and 20 bits.
The UDA1330ATS can be used in two modes: L3 mode or
the static pin mode.
In the L3 mode, all digital sound processing features must
be controlled via the L3 interface, including the selection of
the system clock setting.
In the two static modes, the UDA1330ATS can be
operated in the 256f
s
and 384f
s
system clock mode.
Muting, de-emphasis for 44.1 kHz and four digital input
formats (I
2
S-bus or LSB-justified 16, 18, and 20 bits) can
be selected via static pins. The L3 interface cannot be
used in this application mode, so volume control is not
available in this mode.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UDA1330ATS
SSOP16
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
2000 Apr 18
3
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1330ATS
QUICK REFERENCE DATA
Note
1. The output voltage scales linearly with the power supply voltage.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DDA
DAC analog supply voltage
2.7
5.0
5.5
V
V
DDD
digital supply voltage
2.7
5.0
5.5
V
I
DDA
DAC analog supply current
V
DDA
= 5.0 V
operating
-
9.5
-
mA
power-down
-
400
-
A
V
DDA
= 3.3 V
operating
-
7.0
-
mA
power-down
-
250
-
A
I
DDD
digital supply current
V
DDD
= 5.0 V
-
5.5
-
mA
V
DDD
= 3.3 V
-
3.0
-
mA
T
amb
ambient temperature
-
40
-
+85
C
Digital-to-analog converter (V
DDA
= V
DDD
= 5.0 V)
V
o(rms)
output voltage (RMS value)
note 1
-
1.45
-
V
(THD + N)/S
total harmonic distortion-plus-noise to
signal ratio
at 0 dB
-
-
90
-
85
dB
at
-
60 dB; A-weighted
-
-
40
-
35
dB
S/N
signal-to-noise ratio
code = 0; A-weighted
-
+100
-
95
dB
cs
channel separation
-
100
-
dB
Digital-to-analog converter (V
DDA
= V
DDD
= 3.3 V)
V
o(rms)
output voltage (RMS value)
note 1
-
1.0
-
V
(THD + N)/S
total harmonic distortion-plus-noise to
signal ratio
at 0 dB
-
-
85
-
dB
at
-
60 dB; A-weighted
-
-
38
-
dB
S/N
signal-to-noise ratio
code = 0; A-weighted
-
100
-
dB
cs
channel separation
-
100
-
dB
Power dissipation
P
power dissipation
playback mode
V
DDA
= V
DDD
= 5.0 V
-
75
-
mW
V
DDA
= V
DDD
= 3.3 V
-
33
-
mW
2000 Apr 18
4
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1330ATS
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MGL401
DAC
UDA1330ATS
NOISE SHAPER
INTERPOLATION FILTER
VOLUME/MUTE/DE-EMPHASIS
CONTROL
INTERFACE
14
15
DAC
6
DIGITAL INTERFACE
8
16
9
10
3
2
1
4
5
11
7
13
12
VOUTR
BCK
VSSA
WS
VOUTL
DATAI
VDDA
VDDD
Vref(DAC)
VSSD
APPL0
SYSCLK
APPL1
APPSEL
APPL2
APPL3
Fig.1 Block diagram.
PINNING
SYMBOL
PIN
DESCRIPTION
BCK
1
bit clock input
WS
2
word select input
DATAI
3
data input
V
DDD
4
digital supply voltage
V
SSD
5
digital ground
SYSCLK
6
system clock input: 256f
s
, 384f
s
and 512f
s
APPSEL
7
application mode select input
APPL3
8
application input 3
APPL2
9
application input 2
APPL1
10
application input 1
APPL0
11
application input 0
V
ref(DAC)
12
DAC reference voltage
V
DDA
13
analog supply voltage for DAC
VOUTL
14
left channel output
V
SSA
15
analog ground
VOUTR
16
right channel output
Fig.2 Pin configuration.
handbook, halfpage
UDA1330ATS
MGL402
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VOUTR
BCK
VSSA
WS
VOUTL
DATAI
VDDA
VDDD
Vref(DAC)
VSSD
APPL0
SYSCLK
APPL1
APPSEL
APPL2
APPL3
2000 Apr 18
5
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1330ATS
FUNCTIONAL DESCRIPTION
System clock
The UDA1330ATS operates in slave mode only.
Therefore, in all applications the system devices must
provide the system clock. The system frequency (f
sys
) is
selectable and depends on the application mode. The
options are: 256f
s
, 384f
s
and 512f
s
for the L3 mode and
256f
s
or 384f
s
for the static pin mode. The system clock
must be locked in frequency to the digital interface input
signals.
The UDA1330ATS supports sampling frequencies from
16 to 55 kHz.
Application modes
The application mode can be set with the three-level
pin APPSEL (see Table 1):
L3 mode
Static pin mode with f
sys
= 384f
s
Static pin mode with f
sys
= 256f
s
.
Table 1
Selecting application mode and system clock
frequency via pin APPSEL
The function of an application input pin (active HIGH)
depends on the application mode (see Table 2).
Table 2
Functions of application input pins
For example, in the static pin mode the output signal can
be soft muted by setting pin APPL0 to HIGH.
De-emphasis can be switched on for 44.1 kHz by setting
pin APPL1 to HIGH; setting pin APPL1 to LOW will disable
de-emphasis.
In the L3 mode, pin APPL0 must be set to LOW. It should
be noted that when the L3 mode is used, an initialization
must be performed when the IC is powered-up.
Multiple format input interface
D
ATA FORMATS
The digital interface of the UDA1330ATS supports multiple
format inputs (see Fig.3).
Left and right data-channel words are time multiplexed.
The WS signal must have a 50% duty factor for all
LSB-justified formats.
The BCK clock can be up to 64f
s
, or in other words the
BCK frequency is 64 times the Word Select (WS)
frequency or less: f
BCK
64
f
WS
.
Important: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digital
interface.
The UDA1330ATS also accepts double speed data for
double speed data monitoring purposes
L3
MODE
This mode supports the following input formats:
I
2
S-bus format with data word length of up to 20 bits
MSB-justified format with data word length up to 20 bits
LSB-justified format with data word length of
16, 18 or 20 bits.
S
TATIC PIN MODE
This mode supports the following input formats:
I
2
S-bus format with data word length of up to 20 bits
LSB-justified format with data word length of
16, 18 or 20 bits.
These four formats are selectable via the static pin codes
SF0 and SF1 (see Table 3).
Table 3
Input format selection using SF0 and SF1
VOLTAGE ON
PIN APPSEL
MODE
f
sys
V
SSD
L3 mode
256f
s
, 384f
s
or 512f
s
0.5V
DDD
static pin mode
384f
s
V
DDD
256f
s
PIN
FUNCTION
L3 MODE
STATIC PIN MODE
APPL0
TEST
MUTE
APPL1
L3CLOCK
DEEM
APPL2
L3MODE
SF0
APPL3
L3DATA
SF1
FORMAT
SF0
SF1
I
2
S-bus
0
0
LSB-justified 16 bits
0
1
LSB-justified 18 bits
1
0
LSB-justified 20 bits
1
1
PDF 
ZIP