1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

FEATURES

General

Low power consumption

3.0 V power supply

256, 384 and 512f

system clock

Small package size (SSOP28)

ADC plus integrated high pass filter to cancel DC offset

Overload detector for easy record level control

Separate power control for ADC and DAC

Integrated digital filter plus DAC

No analog post filter required for DAC

Easy application

Functions controllable by microcontroller interface.

Multiple format input interface

S-bus, MSB-justified and LSB-justified format

compatible

input and output format data rate.

DAC digital sound processing

Digital volume control

Digital tone control, bass boost and treble

dB-linear volume and tone control (low microcontroller
load)

Digital de-emphasis for 32, 44.1 and 48 kHz f

Soft mute.

Advanced audio configuration

Stereo single-ended input configuration

Stereo line output (under microcontroller volume
control)

Power-down click prevention circuitry

High linearity, dynamic range, low distortion.

GENERAL DESCRIPTION

The UDA1340 is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. The low power consumption and
low voltage requirements make the device eminently
suitable for use in low-voltage low-power portable digital
audio equipment which incorporates recording and
playback functions.

The UDA1340 supports the I

S-bus data format with word

lengths of up to 20 bits, the MSB-justified data format with
word lengths of up to 20 bits and the LSB justified serial
data format with word lengths of 16, 18 and 20 bits.

The UDA1340 has special sound processing features in
playback mode, de-emphasis, volume, bass boost, treble,
and soft mute, which can be controlled via the
microcontroller interface.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

UDA1340M

SSOP28

plastic shrink small outline package; 28 leads; body width 5.3 mm

SOT341-1

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

DDA(ADC)

ADC analog supply voltage

2.7

3.0

3.6

DDA(DAC)

DAC analog supply voltage

2.7

3.0

3.6

DDO

operational amplifiers supply voltage

2.7

3.0

3.6

DDD

digital supply voltage

2.7

3.0

3.6

DDA(ADC)

ADC supply current

4.5

DDA(DAC)

DAC supply current

3.5

DDO

operational amplifier supply current

DDD

digital supply current

PD(ADC)

digital ADC power-down supply current

PD(DAC)

digital DAC power-down supply current

amb

operating ambient temperature

+85

Analog-to-digital converter

I(rms)

input voltage (RMS value)

0.8

(THD + N)/S

total harmonic distortion plus
noise-to-signal ratio

at 0 dB

60 dB; A-weighted

dBA

S/N

signal-to-noise ratio

= 0 V; A-weighted

dBA

channel separation

100

Digital-to-analog converter

o(rms)

output voltage (RMS value)

0.8

(THD + N)/S

total harmonic distortion plus
noise-to-signal ratio

at 0 dB

60 dB; A-weighted

dBA

S/N

signal-to-noise ratio

code = 0; A weighted

100

dBA

channel separation

100

Power performance

ADDA

power consumption in record and
playback mode

power consumption in playback only
mode

power consumption in record only
mode

power consumption in power-down
mode

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

PINNING

SYMBOL

PIN

Description

SSA(ADC)

ADC analog ground

DDA(ADC)

ADC analog supply voltage

VINL

ADC input left

ref(A)

ADC reference voltage

VINR

ADC input right

ADCN

ADC negative reference voltage

ADCP

ADC positive reference voltage

TEST1

test control 1 (pull-down)

OVERFL

overload flag output

DDD

digital supply voltage

SSD

digital ground

SYSCLK

system clock 256, 384 or 512f

L3MODE

L3-bus mode input

L3CLOCK

L3-bus clock input

L3DATA

L3-bus data input

BCK

bit clock input

word selection input

DATAO

data output

DATAI

data input

TEST3

test output

TEST2

test control 2 (pull-down)

SSA(DAC)

DAC analog ground

DDA(DAC)

DAC analog supply voltage

VOUTR

DAC output right

DDO

operational amplifier supply voltage

VOUTL

DAC output left

SSO

operational amplifier ground

ref(D)

DAC reference voltage

Fig.2 Pin configuration.

handbook, halfpage

VSSA(ADC)

VDDA(ADC)

VINL

Vref(A)

VINR

VADCN

VADCP

TEST1

OVERFL

VDDD

VSSD

SYSCLK

L3MODE

L3CLOCK

Vref(D)

VSSO

VOUTL

VDDO

VDDA(DAC)

VSSA(DAC)

VOUTR

TEST2

TEST3

DATAI

DATAO

BCK

L3DATA

UDA1340

MGG838

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

FUNCTIONAL DESCRIPTION

System clock

The UDA1340 accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable. The options are 256f

, 384f

and 512f

The system clock must be locked in frequency to the digital
interface input signals.

Multiple format input/output interface

The UDA1340 supports the following data input/output
formats:

S-bus with data word length of up to 20 bits

MSB justified serial format with data word length of up to
20 bits

LSB justified serial format with data word lengths of
16, 18 or 20 bits.

The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1340 consists of two
third-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.

Decimation filter (ADC)

The decimation from 128f

is performed in two stages.

The first stage realizes 3rd-order

characteristic. This

filter decreases the sample rate by 16. The second stage,
an FIR filter, consists of 3 half-band filters, each
decimating by a factor of 2.

Table 1

Decimation filter characteristics

ITEM

CONDITION

VALUE (dB)

Passband Ripple

0.45f

0.05

Stop band

>0.55f

Dynamic range

0.45f

108

Gain

overall

1.16

sin x

------------

DC cancellation filter (ADC)

An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 2.

Table 2

DC cancellation filter characteristics

Mute (ADC)

On recovery from power-down or switching on of the
system clock, the serial data output DATAO is held LOW
until valid data is available from the decimation filter. This
time depends on whether the DC cancellation filter is
selected:

DC cancel off: time =

, t = 23.2 ms when

= 44.1 kHz

DC cancel on: time =

, t = 279 ms when

= 44.1 kHz

Overload detection (ADC)

In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than

1 dB (actual figure is

1.16 dB) of the maximum

possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512f

cycles

(11.6 ms at f

= 44.1 kHz). This time-out is reset for each

infringement.

ITEM

CONDITION

VALUE (dB)

Passband ripple

none

Passband gain

Droop

at 0.00045f

0.031

Attenuation at DC

at 0.00000036f

>40

Dynamic range

0.45f

>110

1024

-------------

12288

----------------

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

Interpolation filter (DAC)

The digital filter interpolates from 1f

to 128f

by means of

a cascade of a recursive filter and an FIR filter.

Table 3

Interpolation filter characteristics

Noise shaper (DAC)

The 3rd-order noise shaper operates at 128f

. It shifts

in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.

ITEM

CONDITION

VALUE (dB)

Passband ripple

0.45f

0.03

Stop band

>0.55f

Dynamic range

0.45f

108

Gain

3.5

The Filter Stream DAC (FSDAC)

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

L3-Interface

The UDA1340 has a microcontroller input mode. In the
microcontroller mode, all the digital sound processing
features and the system controlling features can be
controlled by the microcontroller. The controllable features
are:

System clock frequency

Data input format

Power control

DC-filtering

De-emphasis

Volume

Flat/min/max switch

Bass boost

Treble

Mute.

The exchange of data and control information between the
microcontroller and the UDA1340 is accomplished through
a serial hardware interface comprising the following pins:

L3DATA: microcontroller interface data line

L3MODE: microcontroller interface mode line

L3CLOCK: microcontroller interface clock line.

Information transfer via the microcontroller bus is
organized in accordance with the so called `L3' format, in
which two different modes of operation can be
distinguished; address mode and data transfer mode
(see Figs 4 and 5).

The address mode is required to select a device
communicating via the L3-bus and to define the
destination registers for the data transfer mode. Data
transfer for the UDA1340 can only be in one direction,
input to the UDA1340 to program its sound processing and
other functional features.

Address mode

The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits. The fundamental timing is
shown in Fig.4. Data bits 0 to 1 indicate the type of
subsequent data transfer as given in Table 4.

Table 4

Selection of data transfer

Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1340 is 000101 (bit 7 to bit 2). In the event that the
UDA1340 receives a different address, it will deselect its
microcontroller interface logic.

Data transfer mode

The selection preformed in the address mode remains
active during subsequent data transfers, until the
UDA1340 receives a new address command.
The fundamental timing of data transfers is essentially the
same as in the address mode, shown in Fig.4.
The maximum input clock and data rate is 64f

All transfers are byte wise, i.e. they are based on groups
of 8 bits. Data will be stored in the UDA1340 after the
eighth bit of a byte has been received. A multibyte transfer
is illustrated in Fig.6.

ROGRAMMING THE SOUND PROCESSING AND OTHER

FEATURES

The sound processing and other feature values are stored
in independent registers. The first selection of the registers
is achieved by the choice of data type that is transferred.
This is performed in the address mode, BIT 1 and BIT 0
(see Table 4). The second selection is performed by the
2 MSBs of the data byte (BIT 7 and BIT 6). The other bits
in the data byte (BIT 5 to BIT 0) is the value that is placed
in the selected registers.

When the data transfer of type `data' is selected, the
features VOLUME, BASS BOOST, TREBLE,
DE-EMPHASIS, MUTE, MODE and POWER CONTROL
can be controlled. When the data transfer of type `status'
is selected, the features SYSTEM CLOCK FREQUENCY,
DATA INPUT FORMAT and DC-FILTER can be
controlled.

BIT 1

BIT 0

TRANSFER

DATA (volume, bass boost, treble,
de-emphasis, mute, mode and power
control)

not used

STATUS (system clock frequency, data
input format and DC-filter)

not used

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

YSTEM CLOCK FREQUENCY

A 2-bit value (SC1 and SC0) to select the used external
clock frequency (see Table 7).

Table 7

System clock frequency settings

ATA INPUT FORMAT

A 3-bit value (IF2 to IF0) to select the used data format
(see Table 8).

Table 8

Data input format settings

SC1

SC0

FUNCTION

512f

384f

256f

not used

IF2

IF1

IF0

FUNCTION

S-bus

LSB justified, 16 bits

LSB justified, 18 bits

LSB justified, 20 bits

MSB justified

not used

DC-

FILTER

A 1-bit value to enable the digital DC-filter (see Table 9).

Table 9

DC-filtering

OLUME CONTROL

A 6-bit value to program the left and right channel volume
attenuation (VC5 to VC0). The range is 0 dB to

dB in

steps of 1 dB (see Table 10).

Table 10 Volume settings

FUNCTION

no DC-filtering

DC-filtering

VC5

VC4

VC3

VC2

VC1

VC0

VOLUME

(dB)

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

EMPHASIS

A 2-bit value to enable the digital de-emphasis filter.

Table 13 De-emphasis settings

UTE

A 1-bit value to enable the digital mute.

Table 14 Mute

ODE

A 2-bit value to program the mode of the sound processing
filters of Bass Boost and Treble. There are three modes:
flat, min. and max.

DE1

DE0

FUNCTION

no de-emphasis

de-emphasis, 32 kHz

de-emphasis, 44.1 kHz

de-emphasis, 48 kHz

FUNCTION

no muting

muting

Table 15 The flat/min./max. switch

OWER

ONTROL

A 2-bit value to disable the ADC and/or DAC to reduce
power consumption.

Table 16 Power control settings

FUNCTION

flat

min.

max.

PC1

PC0

FUNCTION

ADC

DAC

off

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground,
V

DDD

= V

DDA

= V

DDO

= 3 V; T

amb

= 25

C; unless otherwise specified.

Notes

1. All V

and V

connections must be made to the same power supply.

2. Equivalent to discharging a 100 pF capacitor via a 1.5 k

series resistor, except pins 24, 26 and 28 which can

withstand ESD pulses of

1500 V to +1500 V.

3. Equivalent to discharging a 200 pF capacitor via a 2.5

H series inductor.

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DDD

supply voltage

note 1

5.0

xtal(max)

maximum crystal temperature

150

stg

storage temperature

+125

amb

operating ambient temperature

+85

electrostatic handling

note 2

3000

+3000

note 3

300

+300

SYMBOL

PARAMETER

VALUE

UNIT

th j-a

thermal resistance from junction to ambient in free air

K/W

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

DC CHARACTERISTICS

DDD

= V

DDA

= V

DDO

= 3 V; T

amb

= 25

C; R

= 5 k

; note 1; all voltages referenced to ground (pins 1, 11, 22 and 27);

unless otherwise specified.

Notes

1. All power supply pins (V

and V

) must be connected to the same external power supply unit.

2. When higher capacitive loads must be driven then a 100

resistor must be connected in series with the DAC output

in order to prevent oscillations in the output operational amplifier.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supply

DDA(ADC)

ADC analog supply voltage

2.7

3.0

3.6

DDA(DAC)

DAC analog supply voltage

2.7

3.0

3.6

DDO

operational amplifiers supply voltage

2.7

3.0

3.6

DDD

digital supply voltage

2.7

3.0

3.6

DDA(ADC)

ADC supply current

operation mode

4.5

ADC power-down

200

DDA(DAC)

DAC supply current

operation mode

3.5

DAC power-down

DDO

operational amplifier supply current

operation mode

DAC power-down

DDD

digital supply current

operation mode

DAC power-down

ADC power-down

Digital input pins

HIGH level input voltage

0.8V

DDD

+ 0.5 V

LOW level input voltage

0.5

+0.2V

DDD

input leakage current

input capacitance

Digital output pins

HIGH level output voltage

2 mA

0.85V

DDD

LOW level output voltage

= 2 mA

0.4

Analog-to-digital converter

ref

reference voltage

with respect to V

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

o(ref)

refA

reference output resistance

pin 4

input resistance

1 kHz

9.8

input capacitance

Digital-to-analog converter

ref

reference voltage

with respect to V

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

o(ref)

refD

reference output resistance

pin 28

DAC output resistance

0.13

3.0

o(max)

maximum output current

(THD + N)/S < 0.1%
R

= 5 k

0.22

load resistance

load capacitance

note 2

200

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

AC CHARACTERISTICS (ANALOG)
V

DDD

= V

DDA

= V

DDO

= 3 V; f

= 1 kHz; T

amb

= 25

C; R

= 5 k

all voltages referenced to ground

(pins 1, 11, 22 and 27); unless otherwise specified

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Analog-to-digital converter

i(rms)

input voltage (RMS value)

0.8

unbalance between channels

0.1

(THD + N)/S

total harmonic distortion plus
noise-to-signal ratio

at 0 dB

60 dB; A-weighted

dBA

S/N

signal-to-noise ratio

= 0 V; A-weighted

dBA

channel separation

100

PSRR

power supply rejection ratio

ripple

= 1 kHz;

ripple(p-p)

= 30 mV

Digital-to-analog converter

o(rms)

output voltage (RMS value)

0.8

unbalance between channels

0.1

(THD + N)/S

total harmonic distortion plus
noise-to-signal ratio

at 0 dB

60 dB; A-weighted

dBA

S/N

signal-to-noise ratio

code = 0; A-weighted

100

dBA

channel separation

PSRR

power supply rejection ratio

ripple

= 1 kHz;

ripple(p-p)

= 100 mV

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

AC CHARACTERISTICS (DIGITAL)

DDD

= V

DDA

= V

DDO

= 2.7 to 3.6 V; T

amb

20 to +85

C; R

= 5 k

; all voltages referenced to ground

(pins 1, 11, 22 and 27); unless otherwise specified.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

clock cycle

sys

= 256f

131

sys

= 384f

sys

= 512f

CWL

sys

LOW level pulse width

sys

< 19.2 MHz

sys

19.2 MHz

sys

CWH

sys

HIGH level pulse width

sys

< 19.2 MHz

sys

19.2 MHz

sys

Serial input/output data timing; see Fig.7

BCK

bit clock period

BCK(H)

bit clock HIGH time

100

BCK(L)

bit clock LOW time

100

rise time

fall time

s;DATI

data input set-up time

h;DATI

data input hold time

d(DATO)(BCK)

data output delay time (from BCK falling edge)

d(DATO)(WS)

data output delay time (from WS edge)

MSB-justified format

h;DATO

data output hold time

s;WS

word selection set-up time

h;WS

word selection hold time

Address and data transfer mode timing; see Figs 4 and 5

L3CLK cycle time

500

L3CLK HIGH period

250

L3CLK LOW period

250

s;MA

L3MODE set-up time

address mode

190

h;MA

L3MODE hold time

address mode

190

s;MT

L3MODE set-up time

data transfer mode

190

h;MT

L3MODE hold time

data transfer mode

190

s;DAT

L3DATA set-up time

data transfer mode
and address mode

190

h;DAT

L3DATA hold time

data transfer mode
and address mode

halt

L3MODE halt time

190

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

APPLICATION INFORMATION

Fig.8 Application diagram.

handbook, full pagewidth

MGK582

R30

C11

100

(16 V)

C12

100

(16 V)

VDDA

VDDD

8LM32A07

3 V

ground

VSSA(ADC)

UDA1340

SYSCLK

Vref(A)

VDDD

VDDA(ADC) VADCN VADCP

VSSD

system

clock

DATAO

BCK

overload

flag

OVERFL

R32
1 M

C31
1 nF
(63 V)

(16 V)

VINL

VOUTL

R23

100

R22
10 k

VOUTR

R26

100

R27
10 k

R33
680 k

C32
1 nF
(63 V)

(16 V)

VINR

DATAI

L3MODE

L3CLOCK

L3DATA

100 nF

(63 V)

R21
1

R24

100

(16 V)

C25

100

(63 V)

C21

VDDA

C3
47

(16 V)

C22
100

(63 V)

Vref(D)

C4
47

(16 V)

C23
100

(63 V)

100 nF

(63 V)

R28
1

100

(16 V)

C29

VDDD

VSSO

VDDO

R25
1

100

(16 V)

C26

100 nF

(63 V)

VDDO

VDDA(DAC)

VSSA(DAC)

R29
1

C10

100

(16 V)

C27

100 nF

(63 V)

VDDA

left

output

right

output

left

input

right

input

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

SOLDERING

Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

"IC Package Databook" (order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45

Wave soldering

Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.

The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260

C, and

maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150

C within

6 seconds. Typical dwell time is 4 seconds at 250

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300

C. When

using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320

1997 Jul 09

Philips Semiconductors

Preliminary specification

Low-voltage low-power stereo audio
CODEC with DSP features

UDA1340

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

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Philips Semiconductors a worldwide company

SCA55

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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
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Argentina: see South America

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Hungary: see Austria

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Indonesia: see Singapore

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Printed in The Netherlands

547027/1200/02/pp24

Date of release: 1997 Jul 09

Document order number:

9397 750 02548

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