2003 Dec 08
2
Philips Semiconductors
Product specification
16-bit transceiver with direction pin; 30
series
termination resistors; 5 V tolerant input/output; 3-state
74LVC162245A;
74LVCH162245A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTE
TM
flow-through standard pin-out
architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Integrated 30
termination resistors
High-impedance when V
CC
= 0 V
All data inputs have bushold (74LVCH162245A only)
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
-
40 to +85
C and
-
40 to +125
C.
DESCRIPTION
The 74LVC(H)162245A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. In
3-state operation, outputs can handle 5 V. These features
allow the use of these devices as translators in a mixed
3.3 and 5 V environment.
The 74LVC(H)162245A is a 16-bit transceiver featuring
non-inverting 3-state bus compatible outputs in both send
and receive directions.
The 74LVC(H)162245A features two output enable (nOE)
inputs for easy cascading and two send/receive (nDIR)
inputs for direction control. nOE controls the outputs so
that the buses are effectively isolated. This device can be
used as two 8-bit transceivers or one 16-bit transceiver.
The 74LVCH162245A bushold data inputs eliminates the
need for external pull-up resistors to hold unused inputs.
The 74LVC(H)162245A is designed with 30
series
termination resistors in both HIGH and LOW output stages
to reduce line noise.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Note
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nAn to nBn; nBn to nAn
C
L
= 50 pF; V
CC
= 3.3 V
3.3
ns
C
I
input capacitance
5.0
pF
C
I/O
input/output capacitance
10
pF
C
PD
power dissipation capacitance
V
CC
= 3.3 V; notes 1 and 2
28
pF
2003 Dec 08
4
Philips Semiconductors
Product specification
16-bit transceiver with direction pin; 30
series
termination resistors; 5 V tolerant input/output; 3-state
74LVC162245A;
74LVCH162245A
PINNING
SYMBOL
PIN
DESCRIPTION
1DIR
1
direction control input
n.c.
-
not connected
1B0
2
data input/output
1B1
3
data input/output
GND
4, 10, 15, 21, 28,
34, 39, 45
ground (0 V)
1B2
5
data input/output
1B3
6
data input/output
V
CC
7, 18, 31, 42
supply voltage
1B4
8
data input/output
1B5
9
data input/output
1B6
11
data input/output
1B7
12
data input/output
2B0
13
data input/output
2B1
14
data input/output
2B2
16
data input/output
2B3
17
data input/output
2B4
19
data input/output
2B5
20
data input/output
2B6
22
data input/output
2B7
23
data input/output
2DIR
24
direction control input
2OE
25
output enable input
(active LOW)
2A7
26
data input/output
2A6
27
data input/output
2A5
29
data input/output
2A4
30
data input/output
2A3
32
data input/output
2A2
33
data input/output
2A1
35
data input/output
2A0
36
data input/output
1A7
37
data input/output
1A6
38
data input/output
1A5
40
data input/output
1A4
41
data input/output
1A3
43
data input/output
1A2
44
data input/output
1A1
46
data input/output
1A0
47
data input/output
1OE
48
output enable input
(active LOW)
SYMBOL
PIN
DESCRIPTION
162245
001aaa156
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1B0
1B1
GND
1A0
1A1
GND
1DIR
1OE
1B2
1B3
V
CC
1B4
1B5
GND
1B6
1B7
2B0
2B1
GND
2B2
2B3
V
CC
2B4
2B5
GND
2B6
2B7
2DIR
1A2
1A3
V
CC
1A4
1A5
GND
1A6
1A7
2A0
2A1
GND
2A2
2A3
V
CC
2A4
2A5
GND
2A6
2A7
2OE
Fig.1 Pin configuration SSOP48 and TSSOP48.
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