2003 Dec 08
2
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
MULTIBYTE
TM
flow-through standard pin-out
architecture
Low inductance multiple power and ground pins for
minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bushold (74LVCH16244A only).
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
-
40 to +85
C and
-
40 to +125
C.
DESCRIPTION
The 74LVC(H)16244A is a high-performance, low power,
low voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families. Inputs can be
driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 Volt. These features allow the use of
these devices as a mixed 3.3 and 5 V environment.
The 74LVC(H)16244A is a 16-bit non-inverting buffer/line
driver with 3-state outputs. The device can be used as four
4-bit buffers, two 8-bit buffers or one 16-bit buffer. The
device features four Output Enables (1OE, 2OE, 3OE and
4OE), each controlling four of the 3-state outputs. A HIGH
on nOE causes the outputs to assume a high-impedance
OFF-state.
The 74LVC(H)16244A is identical to the 74LVC16240A
but has non-inverting outputs.
The 74LVCH16244A bushold data inputs eliminates the
need for external pull-up resistors to hold unused inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
C; t
r
= t
f
2.5 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC
2
f
i
N +
(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
(C
L
V
CC
2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay nAn to nYn
C
L
= 50 pF; V
CC
= 3.3 V
3.0
ns
t
PZH
/t
PZL
3-state output enable time nOE to nYn
C
L
= 50 pF; V
CC
= 3.3 V
3.5
ns
t
PHZ
/t
PLZ
3-state output disable time nOE to nYn
C
L
= 50 pF; V
CC
= 3.3 V
3.7
ns
C
I
input capacitance
5.0
pF
C
PD
power dissipation capacitance per gate
V
CC
= 3.3 V; notes 1 and 2
outputs enabled
12
pF
outputs disabled
4.0
pF
2003 Dec 08
4
Philips Semiconductors
Product specification
16-bit buffer/line driver; 5 V input/output
tolerant; 3-state
74LVC16244A;
74LVCH16244A
PINNING
SYMBOL
PIN
BALL
DESCRIPTION
1OE
1
A1
output enable input (active LOW)
n.c.
-
A2, A3, A4, A5, K2, K3, K4, K5
not connected
1Y0
2
B2
data output
1Y1
3
B1
data output
GND
4, 10, 15, 21, 28, 34, 39, 45
B3, B4, D3, D4, G3, G4, J3, J4
ground (0 V)
1Y2
5
C2
data output
1Y3
6
C1
data output
V
CC
7, 18, 31, 42
C3, H3, C4, H4
supply voltage
2Y0
8
D2
data output
2Y1
9
D1
data output
2Y2
11
E2
data output
2Y3
12
E1
data output
3Y0
13
F1
data output
3Y1
14
F2
data output
3Y2
16
G1
data output
3Y3
17
G2
data output
4Y0
19
H1
data output
4Y1
20
H2
data output
4Y2
22
J1
data output
4Y3
23
J2
data output
4OE
24
K1
output enable input (active LOW)
3OE
25
K6
output enable input (active LOW)
4A3
26
J5
data input
4A2
27
J6
data input
4A1
29
H5
data input
4A0
30
H6
data input
3A3
32
G5
data input
3A2
33
G6
data input
3A1
35
F5
data input
3A0
36
F6
data input
2A3
37
E6
data input
2A2
38
E5
data input
2A1
40
D6
data input
2A0
41
D5
data input
1A3
43
C6
data input
1A2
44
C5
data input
1A1
46
B6
data input
1A0
47
B5
data input
2OE
48
A6
output enable input (active LOW)
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