ViSTA VES1820
D i g i t a l E n t e r t a i n m e n t
B l o c k D i a g r a m
O V E R V I E W
The ViSTA VES1820 integrates all fea-
t u res of its predecessor Vi S TA VES1520
(DVB-C compliant Digital Cable Receiver)
combined with a direct IF interface and
9-bit ADC (Analog to Digital Converter)
on a single chip. The Vi S TA VES1820 i s
a fully contained digital cable channel
receiver for digitally transmitted D V B - C
compatible signal format. The VES1820
is based on VLSI's industry leading
Integrated Set-Top Arc h i t e c t u re (Vi S TA)
The VES1820 is a single chip channel
receiver for 16, 32, 64, 128, and 256-
QAM modulated signals. The device
interfaces directly to the IF output of a
tuner, and provides on-chip analog to
digital conversion plus digital demo-
dulation and error correction. Demo-
dulation symbol rates are variable from
0.87-8.7 MBaud and a re achieved
using an external fixed cry s t a l
frequency. The digital loop filters for
both clock and carrier recovery are
programmable in order to optimize
their characteristics according to the
specific application.
Equalization filters can be configured
as either T-spaced transversal
equalizer or DFE type, so that the
system performance can be optimized
according to the network
characteristics.
A proprietary equalization algorithm
is provided to achieve carrier recovery
independent of carrier offset. Next, a
decision directed algorithm takes place
to achieve final equalization converg e n c e .
The VES1820 implements a FORNEY
convoluted deinterleaver of depth 12
and a Reed-Solomon decoder w h i c h
c o rrects up to 8 erroneous bytes. The
deinterleaver and the RS decoder are
automatically synchronized to the frame
synchronization algorithm that uses the
MPEG2 sync byte. Finally, descrambling
a c c o rding to the DVB-C s t a n d a rd is
achieved at the Reed-Solomon o u t p u t .
This device is controlled via an I
2
C bus.
Single-Chip DVB-C
Continuously Variable Cable Channel Receiver
T y p i c a l A p p l i c a t i o n
F E A T U R E S
16/32/64/128/256 QAM
demodulator
9-bit ADC
Digital 9-bit bandpass input signal
Digital down conversion
(direct IF sampling)
Half-Nyquist filters (roll off = 15%)
Automatic gain control (AGC)
Post Width Modulation output
DC offset compensation
Symbol timing recovery, with pro-
grammable second order loop filter
Variable rate capability: SACLK/64 to
SACLK/4 (SACLK max = 36 MHz)
Full digital carrier recovery loop
Carrier acquisition range up to
7% of symbol rate
Integrated adaptive equalizer
(Transversal or DFE equalizer)
On-chip FEC decoder (Deinterleaver
& RS decoder), full DVB-C compliant
DVB compatible differential coding
and mapping
I
2
C bus interface, for easy control
100 MQFP package
0.35 m CMOS technology
VLSI Technology, Inc.
1109 McKay Drive
San Jose, CA 95131
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LIFE SUPPORT APPLICATIONS:
V L S I 's products are not intended for use as critical
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1997 VLSI Technology, Inc. Printed in USA
Document Control: PB-V/iSTA-1820 V1.2 December 97
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