PJ1062A
Low Voltage Transmission Circuits With Dialler Interface
1-12
2003/10.REV.A
he
PJ1062A are integrated circuits that perform all
speech and line interface functions required in fully
electronic telephone sets. They perform electronic
switching between dialling and speech. The ICs operate at
line voltage down to 1.6V
DC
(with reduced performance) to
facilitate the use of more telephone sets connected in parallel.
Low DC line voltage; operates down to 1.6V(excluding
polarity guard)
Voltage regulator with adjustable static resistance
Provides a supply for external circuits
Symmetrical high-impedance inputs(64K) for
dynamic, magnetic or piezoelectric microphones.
Asymmetrical high-impedance inputs(32K) for
electret microphones
DTMF signal input with confidence tone
Mute input for pulse or DTMF dialing
PJ1062A:active LOW (MUTE)
Receiving amplifier for dynamic, magnetic or
piezoelectronic earpieces amplifiers
Large gain setting ranges on microphone and earpiece
amplifiers
Line loss compensation (line current dependent) for
microphone and earpiece amplifiers
DC line voltage adjustment facililty
J
T
Device Operating
Temperature
Package
PJ1062ACD DIP-16
PJ1062ACS
-20+85
SOP-16
DIP-16
SOP-16
Pin 1.Ln
9.V
EE
2.GAS
1
10.Ir
3.GAS
2
11.Dtmf
4.Qr 12.MUTE(PJ1062A)
5.Gar 13.Vcc
6.Mic 14.Reg
7.Mic+ 15.Agc
8.Stab 16.Slpe
FEATURES
ORDERING INFORMATION
PJ1062A
Low Voltage Transmission Circuits With Dialler Interface
2-12
2003/10.REV.A
Supplies Vcc,LN, SLPE,REG and STAB
Power for the IC and its peripheral circuit is usually obtained
from the telephone line. The supply voltage is derived from
the line via a dropping resistor and regulated by the IC. The
supply voltage Vcc may also be used to supply external
circuits e.g. dialling and control circuits.
Decoupling of the supply voltage is performed by a capacutor
between Vcc and V
EE
. The internal voltage regulator is
decoupled by a capacitor between REG and V
EE
.
The DC current flowing into the set is determined by the
exchange supply voltage Vexch, the feeding bridge resistane
Rexch and the DC resistance of the telephone line Rline.
The circuit has an internal current stabilizer operating at a
level determined by a 3.6KW resistor connected between
STAB and V
EE
(see Fig.9). When the line current (I
line
) is
more than 0.5mA greater than the sum of the IC supply
current (Icc) and the current drawn by the peripheral circuitry
connected to Vcc (Ip) the excess current is shunted to V
EE
via
LN.
The regulated voltage on the line termainal(V
LN
) can by
calculated as:
V
LN
=V
ref
+I
SLPE
R9
V
LN
=V
ref
+{(I
line
-Icc-0.510
-3
A)-Ip}R9
V
ref
is an internally generated termperature compensated
reference voltage of 3.7V and R9 is an external resistor
connected between SLPE and V
EE
.
In normal is the value of R9 would be 20W.
Changing the value of R9 will also affect microphone gain,
DTMF gain, gain control characteristics, sidetone level,
maximum output swing on LN and the DC characteristics
(espercially at the lower voltages).
Under normal conditions , when I
SLPE
>>Icc+0.5mA+Ip the
static behaviour of the circuit is that of a 3.7V regulator diode
with an internal resistance equal to that of R9. In the audio
frequency range the dynamic impedance is largely determined
by R1 Fig.3 shows the equivalent impedance of the circuit.
At line currents below 9mA the internal reference voltage is
automatically adjusted to a lower value (typically 1.6V at
1mA). This means that more sets can be operated in parallel
with DC line voltages (excluding the polarity guard) down to
an absolute minimum voltage of 1.6V. At line currents below
9mA the circuit has limited sending and receiving levers. The
internal reference voltage can be adjusted by means of an
external resistor (R
VA
).
This resistor when connected between LN and REG will
decrease the internal reference voltage and when connected
between REG and SLPE will increase the internal reference
voltage.
Current (Ip) available from Vcc for peripheral circuits
depends on the external components used. Fig 10 shows this
current for Vcc>2.2V. If MUTE is LOW (PJ1062) or MUTE
is HIGH (PJ1062A) when the receiving amplifier is driven,
the available current is further reduced. Current availability
can be increased by connecting the supply IC (PJ1081)in
parallel with R1 as shown in Fig.19 and Fig.20, or by
increasing the DC line voltage by means of an external
resistor (R
VA
) connected between REG and SLPE (Fig.18).
Microphone inputs MIC+ and MIC- and gain pins GAS1 and
GAS2.
The circuit has symmetrical microphone inputs. Its input
impedance is 64KW (2 32KW)and its voltage gain is
typically 52dB (when R7=68KW, see Figures14 and
15).Dynamic, magnetic, piezoelectric or electret (with built-in
FET source followers) can be used. Microphone arrangements
are illustrated in Fig.11.
The gain of the microphone amplifier can be adjusted between
44dB and 52dB to suit the sensitivity of the transuder in use.
The gain is proportional to the value of R7 which is connected
between GAS1 and GAS2.
Stability is ensured by two external capacitors, C6 connected
between GAS1 and SLPE and C8 connected between GAS1
and V
EE
. The value of C6 is 100pF but this may be increased
to obtain a first-order low-pass filter. The value of C8 is 10
PJ1062A
Low Voltage Transmission Circuits With Dialler Interface
3-12
2003/10.REV.A
times the value of C6. The cut-off frequency corresponds to
the time constant R7C6.
When MUTE is LOW or open-circuit the DTMF input is
enabled and the microphone and receiving amplifier inputs
are inhibited. The reveres is true when MUTE is LOW or
open-circuit. MUTE switching causes only negligible clicking
on the line and earpiece output. If the number of parallel sets
in use cause a drop in line current to below 6mA the speech
amplifiers remain in active independent to the DC level
applied to the MUTE input.
Input MUTE(PJ1062A)
When MUTE is HIGH the DTMF input is enabled and the
microphone and receiving amplifier inputs are inhibited. The
reveres is true when MUTE is LOW or open-circuit. MUTE
switching causes only negligible clicking on the line and
earpiece output. If the number of parallel sets in use causes a
drop in line current to below 6mA the DTMF amplifier
becomes active independent to the DC level applied to the
MUTE input.
Dual-tone multi-frequency input DTMF
When the DTMF input is enabled dialing tones may be sent
on to the line. The voltage gain from DTMF to LN is typically
25.5dB(When R7=68KW)and varies with R7 in the same way
as the microphone gain. The signaling tones can be heard in
the earpiece at a low level(confidence tone). Receiving
amplifier IR, QR and GAR.
The receiving amplifier has one input(IR) and a non-inverting
output(QR). Earpiece arrangements are illus. trated in Fig.12.
The IR to GR gain is typically 31 dB (when R4=100KW). It
can be adjusted between 20 and 31dB to match the sensitivity
of the transducer in use. The gain is set with the value of R4
which is connected between GAR and QR. The overall
receive gain, between LN and QR, is calculated by subtracting
the anti-sidetone network attenuation(32dB) from the
amplifier gain. Two external capacitors, C4 and C7, ensure
stability. C4 is normally 100pF and C7 is 10 times the value
of C4. The value of C4 may be increased to obtain a first-
order low-pass filter. The cut-off frequency will depend on
the time constant R4C4.
The output voltage of the receiving amplifier is specified for
continuous-wave drive. The maximum output voltage will be
higher under speech conditions where the peak to RMS ratio
is higher.Automatic Gain Control input AGC.
Automatic line loss compensation is achieved by connecting a
resistor(R6) between AGC and V
EE.
The automatic gain control varies the gain of the microphone
amplifier and the receiving amplifier in accordance with the
DC line current . The control range is 5.8dB which
corresponds to line length of 5Km for a 0.5mm diameter
twisted-pair copper cable with a DC resistance of 176W/Km
and average attenuation of 1.2dB/Km.Resistor R6 should be
chosen in accordance with the exchange supply voltage and
its feeding bridge resistance (see Fig.13 and Table 1). The
ratio of startand stop currents of the AGC curve is
independent of the value of R6. If no automatic line-loss
compensation is required the AGC pin may be left open-
circuit. The amplifiers, in this condition, will give their
maximum specified gain.
Sidetone suppression
The anti-sidetone network, R1//Z
line
, R2, R3, R8, R9 and Z
bal
(see Fig.4) suppresses the transmitted signal in the earpiece.
Maximum compensation is obtained when the following
conditions are fulfilled:
R9R2 = R1R3+
bal
bal
Z
R8
Z
R8
+
(1)
R8
Z
Z
bal
bal
+
+
R1
Z
Z
line
line
+
(2)
If fixed values are chosen for R1, R2, R3 and R9, then
condition(1) will always be fulfilled when |R8//Z
bal
|<<R3. To
obtain optimum sidetone suppression, condition(2) has to be
fulfilled which results in:
Z
bal
=
R1
R8
Z
line
=KZ
line
Where K is a scale factor, K=
R1
R8
The scale factor K dependent on the value of R8, is chosen to
meet the following criteria:
PJ1062A
Low Voltage Transmission Circuits With Dialler Interface
4-12
2003/10.REV.A
Compatibility with a standard capacitor from the E6 or E12
range for Z
bal
Z
bal
//R8<<R3 fulfilling condition(a) and thus ensuring correct
anti-sidetone bridge operation
Z
bal
+R8>>R9 to avoid influencing the trainsmit gain. In
practise Z
line
varies considerably with the line type and
length. The value chosen for Z
bal
should therefore be for an
average line length thus giving optimum setting for short or
long lines.
EXAMPLE
The balance impedance Z
bal
at which the optimum
suppression is present can be calculated by:
Suppose Z
line
= 210W + (1265W//140nF) representing a 5Km
line 0.5mm diameter, copper, twisted-pair cable matched to
600W(176W/Km, 38nF/Km).
When K=0.64 then R8=390W;
Z
bal
=130W+(820W//220nF)
The anti-sidetone network for the PJ1060 family shown in
Fig.4 attenuares the signal received from the line by 32dB
before it enters the receiving amplifier. The attenuation is
almost constant over the whole audio-frequency range.
Figure 5 shows a conventional wheatstone bridge anti-
sidetone circuit that can be used as an alternative. Both bridge
types can be used with either resistive or complex set
impedances.
Leq=C3R9Rp
Rp=16.2KW
FIGURE3. EQUIVALENT IMPEDANCE CIRCUIT
FIGURE4. EQUIVALENT OF PJ1062 ANTI-SIDETONE
BRIDGE
FIGURE5. EQUIVALENT CIRCUIT OF AN ANTI-
SIDETONE NETWORK IN AN WHEATSTONE
BRIDGE CONFIGURATION
PJ1062A
Low Voltage Transmission Circuits With Dialler Interface
5-12
2003/10.REV.A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System.
PARMETER CONDITIONS
SYMBOL
MIN.
MAX.
UNIT
Positive continuous line voltage
V
LN
- 12 V
Repetitive line voltage during
switch-on or line interruption
V
LN(R)
- 13.2 V
Repetitive peak line voltage for
1ms pulse per 5s
R9=20W;R10=13W;
See Fig.18
V
LN(RM)
- 28 V
Line current
R9=20W;note 1
I
line
- 140
mA
Positive input voltage
-
Vcc+0.7
V
Input voltage on all other pins
Negative input voltage
V
I
- -0.7 V
Total power dissipation
PJ1062ACD
/PJ1062ACS
R9=20W;note 2
Ptot
-
617
454
mW
mW
Operating ambient temperature
Tamb
-25
+75
Storage temperature
Tstg
-40
+125
Junction temperature
Tj
-
125
Notes
1.Mostly dependent on the maximum requird Tamb and on the voltage between LN and SLPE(see Fig6,7 and 8).
2.Calculated for the maximum ambient temperature specified (Tamb=75) and a maximum junction temperature of 125.
HANDING
This device meets class 2 ESD test requirements [Human Body Model (HMB)].
THERMAL CHARACTERISTICS
PARAMETER SYMBOL
VALUE
UNIT
Thermal resistance from junction to ambient in free air
PJ1062ACD
PJ1062ACS
Rth j-a
81
110
K/W
K/W
Note
1. Mounted on glass epoxy board 28.519.11.5mm.
FIGURE 6./PJ1062ACD safe operating area.
FIGURE 7. PJ1062ACS safe operating area.
(1).Tamb=45; Ptot=988mW
(1).Tamb=45; Ptot=727mW
(2).Tamb=55; Ptot=864mW
(2).Tamb=55; Ptot=636mW
(3).Tamb=65; Ptot=741mW
(3).Tamb=65; Ptot=545mW
(4).TAMB=75 ; PTOT=6
17MW (4).TAMB=75 ;
PTOT=4
54MW
PDF 
ZIP