PLL103-01
Low Skew Buffers
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 1
FEATURES
Generate 18 copies of High-speed clock inputs.
Supports up to four SDRAM DIMMS synchronous
clocks.
Supports 2-wire I2C serial bus interface with
readback.
50% duty cycle with low jitter.
Less than 5ns delay.
Skew between any outputs is less than 250 ps.
Tri-state pin for testing.
Frequency up to 133 MHZ.
3.0V-3.7V Supply range.
48-pin SSOP package.
BLOCK DIAGRAM
PIN CONFIGURATION
Note: ^: pull up
POWER GROUP
VDD: SDRAM( 0:17 )
VDD1: I2C Circuitry
GROUND GROUP
GND: SDRAM( 0:17 )
GND1: I2C Circuitry
KEY SPECIFICATIONS
BUFIN to SDRAM outputs Delay: 1 ~ 5 ns.
Output Slew:
1.5 V/ns.
Output Skew:
250 ps.
Output Duty Cycle: 50%
5%.
PLL103-01
GND
VDD
GND
SDRAM7
SDRAM6
VDD
GND
SDRAM5
VDD
BUF_IN
SDRAM3
SDRAM2
VDD
SDRAM1
SDRAM0
VDD
N/C
N/C
SDATA
VDD1
SDRAM16
GND
VDD
SDRAM13
SDRAM12
GND
OE^
VDD
SDRAM11
SDRAM10
GND
VDD
SDRAM9
N/C
N/C
VDD
SDRAM15
SDRAM14
GND
SDRAM8
SDRAM17
GND
VDD
GND1
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
41
42
44
43
45
46
47
48
SDRAM4
GND
GND
BUF_IN
SDATA
SCLK
I2C
Control
OE
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10
SDRAM11
SDRAM12
SDRAM13
SDRAM14
SDRAM15
SDRAM16
SDRAM17
PLL103-01
Low Skew Buffers
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 2
PIN DESCRIPTIONS
Name
Number
Type
Description
SDRAM (0:3)
4,5,8,9
O
SDRAM Byte0 Clock outputs.
SDRAM (4:7)
13,14,17,18
O
SDRAM Byte1 Clock outputs.
SDRAM (8:11)
31,32,35,36
O
SDRAM Byte2 Clock outputs.
SDRAM (12:15)
40,41,44,45
O
SDRAM Byte3 Clock outputs.
SDRAM (16:17)
21,28
O
SDRAM Byte4 Clock outputs.
OE
38
I
Tristates all outputs, active low. Has internal pull-up.
BUF_IN
11
I
Input for fanout buffers SDRAM (0:17).
SDATA
24
B
SCLK
25
I
Serial data inputs for serial interface port.
VDD
3,7,12,16,20,2
9,33,37,42,46
P
3.3V Power supply for SDRAM buffer.
VDD1
23
P
3.3V Power supply for I2C circuitry.
GND
6,10,15,19,22,
27,30,34,39,43
P
Ground for SDRAM buffer.
GND1
26
P
Power supply for I2C circuitry.
N/C
1,2,47,48
-
Pins are internally disconnected.
PLL103-01
Low Skew Buffers
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 3
I2C BUS CONFIGURATION SETTING
Address Assignment
A6 A5 A4 A3 A2 A1 A0 R/W
1 1 0 1 0 0 1 _
Slave
Receiver/Transmitter
Provides both slave write and readback functionality
Data Transfer Rate
Standard mode at 100kbits/s
Data Protocol
This serial protocol is designed to allow both blocks write and read from the controller. The
bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred
must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will
terminate the transfer. The write or read block both begins with the master sending a slave
address and a write condition (0xD2) or a read condition (0xD3).
Following the acknowledge of this address byte, in
Write Mode: the Command Byte and Byte
Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte
Count Byte will be read by the master then all other Data Byte. Byte Count Byte default at
power-up is = (0x09).
I2C CONTROL REGISTERS
1. BYTE 0: SDRAM(0:7) Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
18
1
SDRAM7 (Active/Inactive)
Bit 6
17
1
SDRAM6 (Active/Inactive)
Bit 5
14
1
SDRAM5 (Active/Inactive)
Bit 4
13
1
SDRAM4 (Active/Inactive)
Bit 3
9
1
SDRAM3 (Active/Inactive)
Bit 2
8
1
SDRAM2 (Active/Inactive)
Bit 1
5
1
SDRAM1 (Active/Inactive)
Bit 0
4
1
SDRAM0 (Active/Inactive)
PLL103-01
Low Skew Buffers
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 4
2. BYTE 1: SDRAM(8:15) Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
45
1
SDRAM15 (Active/Inactive)
Bit 6
44
1
SDRAM14 (Active/Inactive)
Bit 5
41
1
SDRAM13 (Active/Inactive)
Bit 4
40
1
SDRAM12 (Active/Inactive)
Bit 3
36
1
SDRAM11 (Active/Inactive)
Bit 2
35
1
SDRAM10 (Active/Inactive)
Bit 1
32
1
SDRAM9 (Active/Inactive)
Bit 0
31
1
SDRAM8 (Active/Inactive)
3. BYTE 2: SDRAM(16:17) Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default
Description
Bit 7
28
1
SDRAM17 (Active/Inactive)
Bit 6
21
1
SDRAM16 (Active/Inactive)
Bit 5
-
1
Reserved
Bit 4
-
1
Reserved
Bit 3
-
1
Reserved
Bit 2
-
1
Reserved
Bit 1
-
1
Reserved
Bit 0
-
1
Reserved
PLL103-01
Low Skew Buffers
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 03/08/00 Page 5
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
V
DD
V
SS
-
0.5
7.0
V
Input Voltage, dc
V
I
V
SS
-
0.5
V
DD
+
0.5
V
Output Voltage, dc
V
O
V
SS
-
0.5
V
DD
+
0.5
V
Storage Temperature
T
S
-65
150
C
Ambient Operating Temperature
T
A
0
70
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. AC/DC Electrical Specifications
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Input High Current
I
IH
V
IN
= V
DD
5
uA
I
IL
V
IN
=0V; with no pull-up resistors
uA
Input Low Current
I
IL
V
IN
=0V; with 100k pull-up resistors
uA
Input High Voltage
V
IH
2
V
DD
+
0.3
V
Input Low Voltage
V
IL
V
SS
-
0.3
0.8
V
Input Frequency
F
IN
V
DD
=3.3V; All outputs loaded
10
150
Mhz
Input Capacitance
C
IN
Logic Inputs
5
PF
I
DD1
C
L
= 0pf @ 66MHz
80
120
mA
I
DD2
C
L
= 0pf @ 100MHz
120
180
mA
I
DD3
C
L
= 30pf; RS= 33
@ 66MHz
180
260
mA
I
DD4
C
L
= 30pf; RS= 33
@ 100MHz
240
360
mA
Operating Supply
Current
I
DD5
Stopped, input at 0 or VDD
500
uA
PDF 
ZIP