N
et
C
hip
Technology, Inc.
335 Pioneer Way
Mountain View, California 94041
Tel (650) 526-1490
Fax (650) 526-1494
e-mail: sales@netchip.com
Internet: www.netchip.com
NET2280 PCI USB 2.0 High Speed
Peripheral Controller
Rev 1A Device
Doc #:
605-0177-0120
Revision: 1.2
Date:
March 17, 2003
Specification
NET2280 PCI/USB 2.0 Controller
____________________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
March 17, 2003
2
This document contains material that is confidential to NetChip. Reproduction without the express written consent
of NetChip is prohibited. All reasonable attempts were made to ensure the contents of this document are accurate,
however no liability, expressed or implied is guaranteed. NetChip reserves the right to modify this document,
without notification, at any time.
Revision History
Revision
Issue Date
Comments
1.0
May 5, 2002
Initial Release
1.1
November 11, 2002
Update power consumption values
1.2
March 17, 2003
Rev 1A release
Specification
NET2280 PCI/USB 2.0 Controller
____________________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
March 17, 2003
3
NET2280 PCI/USB 2.0 Controller
1
INTRODUCTION ...............................................................................................................................10
1.1
F
EATURES
.......................................................................................................................................10
1.2
F
EATURE
O
VERVIEW
......................................................................................................................10
1.3
O
PERATION
O
VERVIEW
..................................................................................................................13
1.3.1
Applications ...........................................................................................................................13
1.3.2
Initialization...........................................................................................................................13
1.3.3
PCI Interface .........................................................................................................................13
1.3.4
USB Interface ........................................................................................................................13
1.3.5
Interrupts ...............................................................................................................................14
1.4
NET2280 B
LOCK
D
IAGRAM
...........................................................................................................14
1.5
NET2280 T
YPICAL
A
DAPTER
M
ODE
B
LOCK
D
IAGRAM
.................................................................15
1.6
NET2280 T
YPICAL
H
OST
M
ODE
B
LOCK
D
IAGRAM
.......................................................................15
1.7
E
XAMPLE CONNECTIONS TO
NET2280 ...........................................................................................16
1.7.1
Example Part Numbers..........................................................................................................17
1.7.2
General PCB Layout Guidelines ...........................................................................................17
1.7.2.1
USB Differential Signals ..................................................................................................................17
1.7.2.2
Analog VDD (power)........................................................................................................................17
1.7.2.3
Analog VSS (ground)........................................................................................................................18
1.7.2.4
Decoupling Capacitors......................................................................................................................18
1.7.2.5
EMI Noise Suppression ....................................................................................................................18
1.8
T
ERMINOLOGY
...............................................................................................................................19
2
PIN DESCRIPTION............................................................................................................................20
2.1
D
IGITAL
P
OWER AND
G
ROUND
(26
PINS
) .......................................................................................20
2.2
USB T
RANSCEIVER
(15
PINS
).........................................................................................................21
2.3
C
LOCKS
, R
ESET
, M
ISC
(27
PINS
) ....................................................................................................22
2.4
PCI B
US
(52
PINS
)..........................................................................................................................24
2.5
P
HYSICAL
P
IN
A
SSIGNMENT
...........................................................................................................27
3
RESET AND INITIALIZATION ......................................................................................................28
3.1
O
VERVIEW
......................................................................................................................................28
3.2
RESET# P
IN
..................................................................................................................................28
3.3
PCI RST# P
IN
................................................................................................................................28
3.4
R
OOT
P
ORT
R
ESET
..........................................................................................................................28
3.5
S
OFT
R
ESETS
..................................................................................................................................28
3.6
R
ESET
S
UMMARY
...........................................................................................................................29
3.7
I
NITIALIZATION
S
UMMARY
.............................................................................................................29
4
EEPROM..............................................................................................................................................30
4.1
O
VERVIEW
......................................................................................................................................30
4.2
EEPROM D
ATA
F
ORMAT
..............................................................................................................30
4.3
I
NITIALIZATION
..............................................................................................................................31
4.4
EEPROM R
ANDOM
R
EAD
/W
RITE
A
CCESS
....................................................................................31
4.4.1
EEPROM Opcodes ................................................................................................................31
4.4.2
EEPROM Low-Level Access Routines...................................................................................32
4.4.3
EEPROM Read Status Routine..............................................................................................33
4.4.4
EEPROM Write Data Routine ...............................................................................................33
4.4.5
EEPROM Read Data Routine................................................................................................33
5
8051 CPU..............................................................................................................................................34
Specification
NET2280 PCI/USB 2.0 Controller
____________________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
March 17, 2003
4
5.1
O
VERVIEW
......................................................................................................................................34
5.2
8051 M
EMORY
M
AP
.......................................................................................................................34
5.2.1
Program Space (64 Kbytes)...................................................................................................34
5.2.2
External Data Space (64 Kbytes)...........................................................................................34
5.2.3
Internal Data Space (256 bytes) ............................................................................................34
5.2.3.1
Internal RAM (256 Bytes) ................................................................................................................34
5.2.3.2
Special Function Registers................................................................................................................35
5.2.4
PCI Master Cycles.................................................................................................................36
5.3
8051 I
NTERRUPTS
...........................................................................................................................37
6
PCI INTERFACE................................................................................................................................38
6.1
O
VERVIEW
......................................................................................................................................38
6.2
C
ONFIGURATION
T
RANSACTIONS
...................................................................................................38
6.3
I
NITIATOR
T
RANSACTIONS
.............................................................................................................39
6.4
T
ARGET
T
RANSACTIONS
.................................................................................................................39
6.5
B
US
A
RBITRATION
..........................................................................................................................40
6.5.1
Overview................................................................................................................................40
6.5.2
External Arbiter Mode...........................................................................................................40
6.5.3
Internal Arbiter Mode............................................................................................................40
6.5.4
Arbitration Parking ...............................................................................................................40
7
USB FUNCTIONAL DESCRIPTION...............................................................................................41
7.1
USB I
NTERFACE
.............................................................................................................................41
7.2
USB P
ROTOCOL
.............................................................................................................................41
7.2.1
Tokens....................................................................................................................................41
7.2.2
Packets...................................................................................................................................41
7.2.3
Transaction............................................................................................................................42
7.2.4
Transfer .................................................................................................................................42
7.3
A
UTOMATIC
R
ETRIES
.....................................................................................................................42
7.3.1
Out Transactions ...................................................................................................................42
7.3.2
In Transactions ......................................................................................................................42
7.4
P
ING
F
LOW
C
ONTROL
.....................................................................................................................42
7.5
P
ACKET
S
IZES
.................................................................................................................................42
7.6
USB E
NDPOINTS
............................................................................................................................43
7.6.1
Control Endpoint - Endpoint 0 ..............................................................................................43
7.6.1.1
Control Write Transfer......................................................................................................................43
7.6.1.2
Control Write Transfer Details..........................................................................................................44
7.6.1.3
Control Read Transfer.......................................................................................................................45
7.6.1.4
Control Read Transfer Details ..........................................................................................................45
7.6.1.5
Auto-Enumerate................................................................................................................................47
7.6.2
Isochronous Endpoints ..........................................................................................................47
7.6.2.1
Isochronous Out Transactions...........................................................................................................48
7.6.2.2
High Bandwidth Isochronous OUT Transactions .............................................................................48
7.6.2.3
Isochronous In Transactions .............................................................................................................49
7.6.2.4
High Bandwidth Isochronous IN Transactions .................................................................................49
7.6.3
Bulk Endpoints.......................................................................................................................50
7.6.3.1
Bulk Out Transactions ......................................................................................................................50
7.6.3.2
Bulk In Endpoints .............................................................................................................................51
7.6.4
Interrupt Endpoints................................................................................................................52
7.6.4.1
Interrupt Out Transactions ................................................................................................................52
7.6.4.2
Interrupt In Endpoints .......................................................................................................................52
7.6.4.3
High Bandwidth INTERRUPT Endpoints ........................................................................................52
7.6.5
Dedicated Endpoints..............................................................................................................53
7.6.5.1
CFGOUT Endpoint ...........................................................................................................................53
7.6.5.2
CFGIN Endpoint...............................................................................................................................54
Specification
NET2280 PCI/USB 2.0 Controller
____________________________________________________________________________________
NetChip Technology, Inc., 2003
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
http://www.netchip.com
March 17, 2003
5
7.6.5.3
PCIOUT Endpoint ............................................................................................................................55
7.6.5.4
PCIIN Endpoint ................................................................................................................................56
7.6.5.5
STATIN Endpoint.............................................................................................................................56
7.7
FIFO
S
.............................................................................................................................................57
7.7.1
IN Endpoint FIFOs................................................................................................................57
7.7.2
OUT Endpoint FIFOs............................................................................................................58
7.8
USB T
EST
M
ODES
..........................................................................................................................59
8
DMA CONTROLLER ........................................................................................................................60
8.1
O
VERVIEW
......................................................................................................................................60
8.2
S
INGLE
T
RANSFER
M
ODE
...............................................................................................................60
8.2.1
OUT Endpoints ......................................................................................................................60
8.2.2
IN Endpoints ..........................................................................................................................60
8.3
S
CATTER
/G
ATHER
M
ODE
...............................................................................................................61
8.3.1
Valid Bit.................................................................................................................................61
8.3.2
Clear Count Enable ...............................................................................................................61
8.3.3
Direction................................................................................................................................61
8.3.4
Done Interrupt Enable...........................................................................................................62
8.3.5
End of Chain..........................................................................................................................62
8.4
OUT T
RANSFER
DMA C
OMPLETION
.............................................................................................62
8.5
DMA A
BORT
.................................................................................................................................63
8.6
DMA P
AUSE
..................................................................................................................................63
8.7
PCI U
NALIGNED
W
RITE
T
RANSFERS
..............................................................................................63
8.7.1
Restrictions ............................................................................................................................63
8.8
PCI U
NALIGNED
R
EAD
T
RANSFERS
...............................................................................................64
8.8.1
Restrictions ............................................................................................................................64
9
INTERRUPT AND STATUS REGISTER OPERATION...............................................................65
9.1
O
VERVIEW
......................................................................................................................................65
9.2
I
NTERRUPT
S
TATUS
R
EGISTERS
(IRQSTAT0
AND
IRQSTAT1) ....................................................65
9.3
E
NDPOINT
R
ESPONSE
R
EGISTERS
(EP_RSP) ..................................................................................65
9.4
E
NDPOINT
S
TATUS
R
EGISTER
(EP_STAT) .....................................................................................65
10
POWER MANAGEMENT.............................................................................................................66
10.1
O
VERVIEW
......................................................................................................................................66
10.2
USB P
OWER
C
ONFIGURATIONS
......................................................................................................66
10.2.1
Self-Powered Device..............................................................................................................66
10.3
USB S
USPEND
M
ODE
.....................................................................................................................66
10.4
PCI P
OWER
M
ANAGEMENT
............................................................................................................67
10.4.1
Power States ..........................................................................................................................67
10.5
USB S
USPEND
/R
ESUME FOR
PCI H
OST
M
ODE
...............................................................................67
10.5.1
Suspend Sequence..................................................................................................................67
10.5.2
Host Initiated Wake-Up .........................................................................................................68
10.5.3
Device-Remote Wake-Up.......................................................................................................68
10.5.4
Resume Interrupt ...................................................................................................................68
10.6
USB S
USPEND
/R
ESUME FOR
PCI A
DAPTER
M
ODE
........................................................................68
10.6.1
Suspend Sequence with 8051 held in reset ............................................................................68
10.6.2
Host Initiated Wake-Up with 8051 held in reset....................................................................68
10.6.3
Suspend Sequence with 8051 operating ................................................................................68
10.6.4
Host Initiated Wake-Up with 8051 operating........................................................................69
10.6.5
PME Isolation........................................................................................................................69
10.7
NET2280 L
OW
-P
OWER
M
ODES
.....................................................................................................70
10.7.1
USB Suspend (Unplugged from USB) ...................................................................................70
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