PCI 9060SD Data Sheet
Version 1.0
April 17, 1997
Website: http://www.plxtech.com
Email: apps@plxtech.com
Phone: 408-774-9060
FAX: 408-774-2169
PCI 9060SD
TABLE OF CONTENTS
PLX Technology, Inc., 1997
Page iii
Version 1.0
TABLE OF CONTENTS
1. GENERAL DESCRIPTION ..................................................................................................................................................1
1.1 MAJOR FEATURES.......................................................................................................................................................1
1.2 COMPARISON OF PCI 9060 AND PCI 9060SD ...........................................................................................................2
2. BUS OPERATION ...............................................................................................................................................................3
2.1 PCI BUS CYCLES..........................................................................................................................................................3
2.1.1 PCI Target Command Codes ..................................................................................................................................3
2.1.2 PCI Master Command Codes..................................................................................................................................3
2.1.2.1 DMA Master Command Codes........................................................................................................................................... 3
2.2 LOCAL BUS CYCLES ....................................................................................................................................................3
2.2.1 Local Bus Slave .......................................................................................................................................................3
2.2.2 Local Bus Master .....................................................................................................................................................3
2.2.2.1 Ready/Wait State Control................................................................................................................................................... 3
2.2.2.2 Burst Mode and Continuous Burst Mode (BTERM "Burst Terminate" Mode) ..................................................................... 4
2.2.2.3 Recovery States ................................................................................................................................................................. 4
2.2.2.4 Local Bus Read Accesses.................................................................................................................................................. 4
2.2.2.5 Local Bus Write Accesses............................................................................................... ................................................... 5
2.2.2.6 Direct Slave Write Access to 8- and 16-bit bus ......................................................................... ......................................... 5
2.2.2.7 Local Bus Data Parity ......................................................................................................................................................... 5
2.2.2.8 Local Bus Little/Big Endian................................................................................................................................................. 5
3. FUNCTIONAL DESCRIPTION ............................................................................................................................................7
3.1 RESET ...........................................................................................................................................................................7
3.1.1 PCI Bus Input RST# ................................................................................................................................................7
3.1.2 Local Bus Input LRESETi# ......................................................................................................................................7
3.1.3 Local Bus Output LRESETo# ..................................................................................................................................7
3.1.4 Software Reset ........................................................................................................................................................7
3.2 PCI 9060SD INITIALIZATION ........................................................................................................................................7
3.3 EEPROM ........................................................................................................................................................................7
3.3.1 Short EEPROM Load...............................................................................................................................................7
3.3.2 Long EEPROM Load ...............................................................................................................................................8
3.3.3 Extra Long EEPROM Load ....................................................................................................................................10
3.3.4 Internal Register Access........................................................................................................................................10
3.3.5 PCI Bus Access to Internal Registers....................................................................................................................11
3.3.6 Local Bus Access to Internal Registers .................................................................................................................11
3.4 DIRECT DATA TRANSFER MODES...........................................................................................................................12
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3.4.1 Direct Bus Master Operation .................................................................................................................................12
3.4.2 Direct Slave Operation (PCI Master to Local Bus Access)....................................................................................12
3.4.2.1 PCI to Local Address Mapping ......................................................................................................................................... 13
3.4.2.1.1 Local Bus Initialization Software................................................................................................................................ 13
3.4.2.1.2 PCI Initialization Software.......................................................................................................................................... 13
3.4.2.2 Direct Slave Lock ............................................................................................................................................................. 15
3.4.3 Direct Slave Priority ...............................................................................................................................................15
3.5 DMA OPERATION .......................................................................................................................................................15
3.5.1 Non-Chaining Mode DMA ......................................................................................................................................16
3.5.2 Chaining Mode DMA..............................................................................................................................................17
3.5.3 DMA Data Transfers ..............................................................................................................................................18
3.5.3.1 Local to PCI Bus DMA Transfer ....................................................................................................................................... 18
3.5.3.2 PCI to Local Bus DMA Transfer ....................................................................................................................................... 19
3.5.4 Unaligned Transfers ..............................................................................................................................................19
3.5.5 Demand Mode DMA ..............................................................................................................................................19
3.5.6 DMA Priority...........................................................................................................................................................19
3.5.7 DMA Arbitration......................................................................................................................................................20
3.5.7.1 End Of Transfer (EOT1#) Input ........................................................................................................................................ 20
3.5.7.2 Local Latency and Pause Timers ..................................................................................................................................... 20
3.6 BREQ INPUT ...............................................................................................................................................................20
3.7 DOORBELL REGISTERS ............................................................................................................................................20
3.8 MAILBOX REGISTERS................................................................................................................................................20
3.9 INTERRUPTS ..............................................................................................................................................................20
3.9.1 PCI Interrupts (INTA#) ...........................................................................................................................................20
3.9.1.1 Local to PCI Doorbell Interrupt ......................................................................................................................................... 20
3.9.1.2 Local Interrupt Input ......................................................................................................................................................... 21
3.9.1.3 Master/Target Abort Interrupt ........................................................................................................................................... 21
3.9.2 Local Interrupts (LINTo#).......................................................................................................................................21
3.9.2.1 PCI to Local Doorbell Interrupt ......................................................................................................................................... 21
3.9.2.2 Built-In Self Test Interrupt (BIST) ..................................................................................................................................... 21
3.9.2.3 DMA Channel 1 Interrupt.................................................................................................................................................. 21
3.9.3 PCI SERR# (PCI NMI) ...........................................................................................................................................22
3.9.4 Local LSERR# (Local NMI)....................................................................................................................................22
4. REGISTERS ......................................................................................................................................................................23
4.1 REGISTER ADDRESS MAPPING ...............................................................................................................................23
4.2 PCI CONFIGURATION REGISTERS ..........................................................................................................................25
4.2.1 PCI Configuration ID Register (Offset 00h) ...........................................................................................................25
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4.2.2 PCI Command Register (Offset 04h).....................................................................................................................25
4.2.3 PCI Status Register (Offset 06h) ...........................................................................................................................26
4.2.4 PCI Revision ID Register (Offset 08h) ...................................................................................................................26
4.2.5 PCI Class Code Register (Offset 09 - 0Bh) ...........................................................................................................27
4.2.6 PCI Cache Line Size Register (Offset 0Ch)...........................................................................................................27
4.2.7 PCI Latency Timer Register (Offset 0Dh) ..............................................................................................................27
4.2.8 PCI Header Type Register (Offset 0Eh) ................................................................................................................27
4.2.9 PCI Built-In Self Test (BIST) Register (PCI Offset 0Fh) ........................................................................................28
4.2.10 PCI Base Address Register for Memory Access to Runtime Registers (Offset 10h) ..........................................28
4.2.11 PCI Base Address Register for I/O Access to Runtime Registers (Offset 14h) ..................................................29
4.2.12 PCI Base Address Register for Memory Access to Local Address Space 0 (Offset 18h) ...................................29
4.2.13 PCI Base Address Register for Memory Access to Local Address Space 1 (Offset 1Ch) ..................................30
4.2.14 PCI Configuration ID Register (PCI 2Ch) (LOC 2Ch) ..........................................................................................30
4.2.15 PCI Expansion ROM Base Register (Offset 30h) ................................................................................................30
4.2.16 PCI Interrupt Line Register (Offset 3Ch)..............................................................................................................31
4.2.17 PCI Interrupt Pin Register (Offset 3Dh) ...............................................................................................................31
4.2.18 PCI Min_Gnt Register (Offset 3Eh) .....................................................................................................................31
4.2.19 PCI Max_Lat Register (Offset 3Fh) .....................................................................................................................31
4.3 LOCAL CONFIGURATION REGISTERS ....................................................................................................................32
4.3.1 Local Address Space 0 Range Register for PCI to Local Bus (PCI 00h) (LOC 80h) ............................................32
4.3.2 Local Address Space 0 Local Base Address (Remap) Register for PCI to Local Bus (PCI 04h) (LOC 84h) ........32
4.3.3 Local Arbitration Register (PCI 08h) (LOC 88h) ....................................................................................................33
4.3.4 Big/Little Endian Descriptor Register (PCI 0Ch) (LOC 8Ch)..................................................................................34
4.3.5 Local Expansion ROM Range Register for PCI to Local Bus (PCI 10h) (LOC 90h)..............................................34
4.3.6 Local Expansion ROM Base Address (Remap) Register for PCI to Local Bus (PCI 14h) (LOC 94h)...................34
4.3.7 Local Bus Region Descriptor for PCI to Local Accesses Register (PCI 18h) (LOC 98h) ......................................35
4.3.8 Local Address Space 1 Range Register for PCI to Local Bus (PCI 30h) (LOC B0h) ............................................36
4.3.9 Local Address Space 1 Local Base Address (Remap) Register for PCI to Local Bus (PCI 34h) (LOC B4h) .......36
4.3.10 Local Bus Region Descriptor for (Space 1) PCI to Local Accesses Register (PCI 38h) (LOC B8h) ...................37
4.4 SHARED RUNTIME REGISTERS ...............................................................................................................................38
4.4.1 Mailbox Register 0 (PCI 40h) (LOC C0h) ..............................................................................................................38
4.4.2 Mailbox Register 1 (PCI 44h) (LOC C4h) ..............................................................................................................38
4.4.3 Mailbox Register 2 (PCI 48h) (LOC C8h) ..............................................................................................................38
4.4.4 Mailbox Register 3 (PCI 4Ch) (LOC CCh) .............................................................................................................38
4.4.5 PCI to Local Doorbell Register (PCI 60h) (LOC E0h)............................................................................................39
4.4.6 Local to PCI Doorbell Register (PCI 64h) (LOC E4h)............................................................................................39
4.4.7 Interrupt Control/Status Register (PCI 68h) (LOC E8h) ........................................................................................40
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Version 1.0
4.4.8 EEPROM Control, PCI Command Codes, User I/O Control, Init Control Register (PCI 6Ch) (LOC ECh)............41
4.4.9 PCI Configuration ID Register (PCI 70h) (LOC F0h) .............................................................................................41
4.5 LOCAL DMA REGISTERS...........................................................................................................................................42
4.5.1 DMA Channel 1 Mode Register (LOC 114h) (PCI 94h).........................................................................................42
4.5.2 DMA Channel 1 PCI Data Address Register (LOC 118h) (PCI 98h) .....................................................................43
4.5.3 DMA Channel 1 Local Data Address Register (LOC 11Ch) (PCI 9Ch) .................................................................43
4.5.4 DMA Channel 1 Transfer Size (Bytes) Register (LOC 120h) (PCI A0h)................................................................43
4.5.5 DMA Channel 1 Descriptor Pointer Register (LOC 124h) (PCI A4h).....................................................................43
4.5.6 DMA Command/Status Register (LOC 128h) (PCI A8h) .......................................................................................44
4.5.7 DMA Arbitration Register 0 (LOC 12Ch) (PCI ACh) ..............................................................................................44
4.5.8 DMA Arbitration Register 1 (LOC 130h) (PCI B0h) ...............................................................................................45
5. PIN SUMMARY .................................................................................................................................................................46
6. ELECTRICAL AND TIMING SPECIFICATIONS...............................................................................................................58
7. PACKAGE SPECIFICATIONS ..........................................................................................................................................61
7.1 PACKAGE MECHANICAL DIMENSIONS....................................................................................................................61
7.2 TYPICAL PCI BUS MASTER ADAPTER .....................................................................................................................62
7.3 PCI 9060SD PIN OUT..................................................................................................................................................63
8. TIMING DIAGRAMS ..........................................................................................................................................................64
8.1 LIST OF TIMING DIAGRAMS ......................................................................................................................................64
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