PCI 9080 Data Book
Version 1.06
January 2000
Website: http://www.plxtech.com
Email: apps@plxtech.com
Phone: 408 774-9060
800 759-3735
Fax: 408 774-2169
2000 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have
minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc. Other brands and names are
property of their respective owners.
Order Number: 9080-SIL-DB-P1-1.06
Printed in the USA, January 2000
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved
v
CONTENTS
FIGURES
XI
TABLES
XIII
TIMING DIAGRAMS .......................................................................................................................................................... XVII
PREFACE
XXI
REVISION HISTORY ........................................................................................................................................................ XXIII
FEATURES 1
1.
GENERAL DESCRIPTION .............................................................................................................................................. 3
1.1
C
OMPANY AND
P
RODUCT
B
ACKGROUND
...................................................................................................................... 3
1.2
PCI 9080 A
PPLICATIONS
............................................................................................................................................ 3
1.2.1
PCI Adapter Cards ............................................................................................................................................. 3
1.2.2
Embedded Systems ........................................................................................................................................... 3
1.3
M
AJOR
F
EATURES
....................................................................................................................................................... 3
1.4
C
OMPATIBILITY WITH
PCI 9060, PCI 9060ES,
AND
PCI 9060SD................................................................................. 4
1.4.1
Pin Compatibility................................................................................................................................................. 4
1.4.2
Register Compatibility ........................................................................................................................................ 4
1.5
C
OMPARISON OF
PCI 9060, PCI 9060ES, PCI 9060SD,
AND
PCI 9080 ..................................................................... 5
2.
BUS OPERATION ........................................................................................................................................................... 7
2.1
PCI B
US
C
YCLES
........................................................................................................................................................ 7
2.1.1
PCI Target Command Codes ............................................................................................................................. 7
2.1.2
PCI Master Command Codes ............................................................................................................................ 7
2.1.2.1
DMA Master Command Codes .......................................................................................................................................7
2.1.2.2
Direct Local-to-PCI Command Codes .............................................................................................................................7
2.1.3
PCI Arbitration .................................................................................................................................................... 7
2.2
L
OCAL
B
US
C
YCLES
.................................................................................................................................................... 8
2.2.1
Local Bus Arbitration .......................................................................................................................................... 8
2.2.2
Local Bus Direct Master ..................................................................................................................................... 8
2.2.3
Local Bus Direct Slave ....................................................................................................................................... 8
2.2.3.1
Ready/Wait State Control................................................................................................................................................8
2.2.3.1.1
Wait State--Local Bus ..............................................................................................................................................9
2.2.3.1.2
Wait State--PCI Bus.................................................................................................................................................9
2.2.3.2
Burst Mode and Continuous Burst Mode (Bterm "Burst Terminate" Mode).....................................................................9
2.2.3.2.1
Burst Mode................................................................................................................................................................9
2.2.3.2.2
Continuous Burst Mode (Bterm "Burst Terminate" Mode) .......................................................................................10
2.2.3.2.3
Partial Lword Accesses...........................................................................................................................................10
Contents
PCI 9080 Data Book v1.06
vi
PLX Technology, Inc. All rights reserved
2.2.3.3
Recovery States............................................................................................................................................................10
2.2.3.4
Local Bus Read Accesses ............................................................................................................................................10
2.2.3.5
Local Bus Write Accesses.............................................................................................................................................10
2.2.3.6
Direct Slave Write Accesses--8- and 16-Bit Buses ......................................................................................................10
2.2.3.7
Local Bus Data Parity....................................................................................................................................................10
2.2.3.8
Local Bus Big/Little Endian ...........................................................................................................................................11
2.2.3.8.1
32
-Bit Local Bus--Big Endian Mode .......................................................................................................................11
2.2.3.8.2
16-Bit Local Bus--Big Endian Mode .......................................................................................................................11
2.2.3.8.3
8-Bit Local Bus--Big Endian Mode .........................................................................................................................12
3.
FUNCTIONAL DESCRIPTION ...................................................................................................................................... 13
3.1
R
ESET
...................................................................................................................................................................... 13
3.1.1
PCI Bus Input RST# ......................................................................................................................................... 13
3.1.2
Software Reset LRESETo#.............................................................................................................................. 13
3.1.3
Local Bus Input LRESETi#............................................................................................................................... 13
3.1.4
Local Bus Output LRESETo#........................................................................................................................... 13
3.1.5
Software Reset ................................................................................................................................................. 13
3.2
PCI 9080 I
NITIALIZATION
........................................................................................................................................... 13
3.2.1
Serial EEPROM Initialization............................................................................................................................ 14
3.2.2
Local Initialization ............................................................................................................................................. 14
3.3
S
ERIAL
EEPROM ..................................................................................................................................................... 14
3.3.1
Short Serial EEPROM Load ............................................................................................................................. 15
3.3.2
Long Serial EEPROM Load.............................................................................................................................. 15
3.3.3
Extra Long Serial EEPROM Load .................................................................................................................... 17
3.3.4
Recommended Serial EEPROMs .................................................................................................................... 17
3.3.5
Programming the Serial EEPROM ................................................................................................................... 17
3.4
I
NTERNAL
R
EGISTER
A
CCESS
.................................................................................................................................... 17
3.4.1
PCI Bus Access to Internal Registers .............................................................................................................. 18
3.4.2
Local Bus Access to Internal Registers............................................................................................................ 18
3.5
R
ESPONSE TO
F
ULL AND
E
MPTY
FIFO
S
..................................................................................................................... 19
3.6
D
IRECT
D
ATA
T
RANSFER
M
ODES
............................................................................................................................... 19
3.6.1
Direct Master Operation (Local Master to PCI Target) .................................................................................... 20
3.6.1.1
Decode..........................................................................................................................................................................20
3.6.1.2
FIFOs ............................................................................................................................................................................20
3.6.1.3
Memory Access ............................................................................................................................................................21
3.6.1.4
IO/CFG Access .............................................................................................................................................................21
3.6.1.5
I/O .................................................................................................................................................................................21
Contents
PCI 9080 Data Book v1.06
PLX Technology, Inc. All rights reserved
vii
3.6.1.6
CFG (PCI Configuration Type 0 or Type 1 Cycles) .......................................................................................................21
3.6.1.7
Direct Bus Master Lock .................................................................................................................................................22
3.6.1.8
Master/Target Abort ......................................................................................................................................................22
3.6.1.9
Write and Invalidate ......................................................................................................................................................22
3.6.1.9.1
DMA Write and Invalidate .......................................................................................................................................23
3.6.1.9.2
Direct Master Write and Invalidate ..........................................................................................................................23
3.6.2
Direct Slave Operation (PCI Master to Local Bus Access) .............................................................................. 25
3.6.2.1
PCI 2.1 Mode ................................................................................................................................................................25
3.6.2.2
PCI-to-Local Address Mapping .....................................................................................................................................27
3.6.2.2.1
Byte Enables...........................................................................................................................................................27
3.6.2.2.2
Local Bus Initialization Software .............................................................................................................................27
3.6.2.2.3
PCI Initialization Software .......................................................................................................................................27
3.6.2.3
Deadlock and BREQo ...................................................................................................................................................29
3.6.2.3.1
Backoff ....................................................................................................................................................................30
3.6.2.3.2
Software/Hardware Solution for Systems without Backoff Capability......................................................................30
3.6.2.3.3
Software Solutions to Deadlock ..............................................................................................................................30
3.6.2.4
Direct Slave Lock ..........................................................................................................................................................30
3.6.3
Direct Slave Priority.......................................................................................................................................... 31
3.7
DMA O
PERATION
..................................................................................................................................................... 31
3.7.1
Non-Chaining Mode DMA ................................................................................................................................ 31
3.7.2
Chaining Mode DMA ........................................................................................................................................ 33
3.7.3
DMA Data Transfers......................................................................................................................................... 34
3.7.3.1
Local-to-PCI Bus DMA Transfer....................................................................................................................................35
3.7.3.2
PCI-to-Local Bus DMA Transfer....................................................................................................................................35
3.7.3.3
Unaligned Transfers......................................................................................................................................................36
3.7.4
Demand Mode DMA......................................................................................................................................... 36
3.7.5
DMA Priority ..................................................................................................................................................... 36
3.7.6
DMA Arbitration ................................................................................................................................................ 36
3.7.6.1
End of Transfer (EOT0# or EOT1#) Input .....................................................................................................................36
3.7.6.2
DMA Abort ....................................................................................................................................................................37
3.7.6.3
Local Latency and Pause Timers ..................................................................................................................................37
3.8
V
ENDOR AND
D
EVICE
ID R
EGISTERS
.......................................................................................................................... 37
3.9
D
OORBELL
R
EGISTERS
.............................................................................................................................................. 37
3.10
M
AILBOX
R
EGISTERS
................................................................................................................................................. 37
3.11
U
SER
I
NPUT AND
O
UTPUT
.......................................................................................................................................... 37
3.12
I
NTERRUPTS
............................................................................................................................................................. 38
3.12.1
PCI Interrupts (INTA#)...................................................................................................................................... 38
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