MSP8510
PMC-2031171, Issue 4
Copyright PMC-Sierra, Inc. 200
6
All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers' internal use.
Multi-Service Processor
PRODUCT OVERVIEW
PMC-Sierra's MSP8500 Series multi-service processor products are
designed to meet the needs of networking, storage, office automation,
industrial control and high-end consumer applications.
The MSP8510 Multi-Service processor is a highly-integrated, feature-
rich product that incorporates PMC-Sierra's high performance E9000
microprocessor core. The MSP8510 uses the Fast Device Bus (FDB) as
the system bus to interconnect all the on-chip devices to each other
and to the E9000 microprocessor using the Generic Device Interface
(GDI). All MSP8500 Series products provide a variety of interfaces
including PCI, Ethernet, and ROM, Flash, Compact Flash, SRAM, and
other low-speed peripheral interfaces.
PRODUCT HIGHLIGHTS
E9000 microprocessor core:
600 MHz to 1 GHz operation
Dual-issue superscalar 7-stage pipeline
16 Kbyte L1 Instruction and Data caches with parity and a 256-
Kbyte L2 cache with ECC support
8K entry branch prediction table
Multiple reads with out-of-order return
MMU with 128 total TLB entries, page size range: 4 Kbytes to
256 Mbytes.
High-performance Floating Point Unit (IEEE 754)
Fixed-point DSP instructions
400 MHz Fast Device Bus (FDB) system interconnect:
Multiple master, shared, on-chip bus
Bus performance monitoring
Connects the E9000 CPU and other peripherals to memory and
I/O interfaces
167 200 MHz DDR1/DDR2 SDRAM memory controller with 64-bit
data interface:
Supports Class I and Class II SSTL drive strengths
Supports maximum addressing up to 4 Gbytes
Provides DDR2 single-ended DQS signaling so that DDR2 RAMs
may be supported and operated in DDR1 mode
DDR1 supports device densities of 64, 128, 256, 512 Mbits and
1 Gbit. DDR2 supports densities of 256 Mbits, 512 Mbits and
1 Gbit
DDR2 supports device widths of 8 and 16 bits. DDR1 additionally
supports 32-bit widths
Supports unbuffered and registered DIMMs
2 PCI ports, 32 bits each:
Compliant with PCI 2.3 standard
Supports 0 to 66 MHz frequencies
Supports on-line insertion and removal
Local Bus controller providing glueless ROM, Flash, Compact Flash,
SRAM, external USB 2.0 devices, and Variable-Latency I/O (VLIO)
support:
6 independent chip selects
BLOCK DIAGRAM
On-chip
Memory
GDI Port
PCI
Controller
PCI
Controller
GDI Port
DDR1/
DDR2
Controller
Gigabit Ethernet (GE)
Subsystem
E9000
CPU
Core
GE
Port 1
GE
Port 0
GDI Port
GDI Port
GDI Port
GDI Port
Channelized
DMA
Controller
Central
Processing
Interface
Central
Interrupt
Controller
Local Bus
Controller
GDI Port
Packet
FIFO
Dual
UART
(DUART)
TWI/
MDIO/
MDC
GDI Port
DMA
Controller
Fast Device Bus (FDB)
Central
Arbiter
Released
Product Brief
MSP8510 Multi-Service Processor
Corporate Head Office:
PMC-Sierra, Inc.
Mission Towers One
3975 Freedom Circle
Santa Clara, CA, 95054, U.S.A.
Tel: 1.408.239.8000
Fax: 1.408. 492.1157
PMC-2031171 (R4) Copyright PMC-Sierra, Inc. 200
6. All rights
reserved. For a complete list of PMC-Sierra's trademarks , visit
www.pmc-sierra.com/legal/. Other product and company names
mentioned herein may be the trademarks of their respective owners.
For corporate information, send email to: info@pmc-sierra.com.
All product documentation is available on our web site at:
www.pmc-sierra.com.
Operations Head Office:
PMC-Sierra, Inc.
100-2700 Production Way
Burnaby, BC V5A 4X1 Canada
Tel: 1.604.415.6000
Fax: 1.604.415.6200
2 Ethernet MAC or Generic Packet Interfaces (GE Subsystem +
Generic Device Interface XDMA Controller):
Ethernet MAC interfaces support industry-standard TBI
(1000 Mbit/s), GMII (1000 Mbit/s), and MII (10/100 Mbit/s, full
and half duplex) interface modes
Integrated DMA support for GE subsystem:
Up to 16 logical channels for each receive and transmit direction
Receive and transmit are independent
32-Kbyte scalable packet FIFO:
24 Kbytes for the receive direction. Configurable sizing
Support for Ethernet pause flow control
2 integrated 16550 UART ports
32 Kbytes of on-chip memory (ECC)
64 general-purpose I/O pins with integrated de-bounce on 8 pins
Integrated watchdog timer and 4 general-purpose timers
Up to 4 ports of Two-Wire interface (TWI) with support for Small Form
Factor Plug-able (SFP) or up to 4 ports of MDIO/MDC interface
protocol through the general-purpose I/O pins
Integrated DMA engine, which supports 4 independently configured
and controlled channels
Support for 256 vectored interrupts:
In-band interrupt sources from all on-chip GDI devices
Flexible mapping of interrupt vectors to E9000 CPU interrupt lines
Integrated on-chip EJTAG debug circuitry:
A dedicated debug module on the E9000 core
Watch exceptions, interrupt and exception debuggers,
performance counters, and 64-entry trace buffers
896-pin FCBGA package, 31 mm x 31 mm
Pin compatible with the MSP8520 Multi-service Security
Processor
APPLICATIONS
Low-end/Mid-range Enterprise Switches & Routers
Storage Networking
Office-in-a-box Gateway
Control Plane Processing
SMB Network Attached Storage (NAS)
Imaging systems: Color Laser Printers/MFPs
Embedded Computing
Industrial and General Purpose Control
Media Networked Server
SUPPORT
OPERATING SYSTEMS
Open Source Linux versions 2.4 and 2.6
VxWorks 5.5 from Wind River
Neutrino from QNX Software Systems
EJTAG EMULATORS
Wind River
Corelis
EVALUATION BOARDS
PMC-Sierra PM2330-KIT reference kit
ATX form-factor evaluation board
COMPANION CHIPS
Wide range of companion chips available to interface with the PCI
bus
Control Bus
FE
Line Card
FE
FE
PCI
User
MSP8510
Processor
Line Card
FE
FE
PCI
User
MSP8510
Processor
ASIC
ASIC
SERDES
SERDES
System Control/Processor Card
PCI
Switch
MSP8500 Series
Processor
PHY
PHY
DISTRIBUTED ROUTER AND MULTI-SERVICE SWITCH
FURTHER RESOURCES
MSP8520 MULTI-SERVICE SECURITY PROCESSOR
www.pmc-sierra.com/products/details/msp8520/
VOIP NETWORK PROCESSOR CHIP FAMILY
www.pmc-sierra.com/voip-network-processor/
TECHNICAL DOCUMENTATION
www.pmc-sierra.com/documentation/
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