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Электронный компонент: PM25LV512-25SC

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512 Kbit / 1 Mbit 3.0 Volt-only, Serial Flash Memory
With 25 MHz SPI Bus Interface
PMC
FEATURES
Single Power Supply Operation
- Low voltage range: 2.7 V - 3.6 V
Memory Organization
- Pm25LV512: 64K x 8 (512 Kbit)
- Pm25LV010: 128K x 8 (1 Mbit)
Cost Effective Sector/Block Architecture
- Uniform 4 Kbyte sectors
- Uniform 32 Kbyte blocks (8 sectors per block)
- Two blocks with 32 Kbytes each (512 Kbit)
-
Four blocks with 32 Kbytes each (1 Mbit)
- 128 pages per block
Serial Peripheral Interface (SPI) Compatible
- Supports SPI Modes 0 (0,0) and 3 (1,1)
High Performance Read
- 25 MHz clock rate (maximum)
Page Mode for Program Operations
- 256 bytes per page
Block Write Protection
- The Block Protect (BP1, BP0) bits allow part or entire
of the memory to be configured as read-only.
Hardware Data Protection
- Write Protect (WP#) pin will inhibit write operations
to the status register
Page Program (up to 256 Bytes)
- Typical 2 ms per page program time
Sector, Block and Chip Erase
- Typical 40 ms sector/block/chip erase time
Single Cycle Reprogramming for Status Register
- Build-in erase before programming
High Product Endurance
- Guarantee 100,000 program/erase cycles per single
sector (preliminary)
- Minimum 20 years data retention
Industrial Standard Pin-out and Package
- 8-pin JEDEC SOIC
- 8-contact WSON
- Optional lead-free (Pb-free) packages
GENERAL DESCRIPTION
The Pm25LV512/010 are 512 Kbit/1 Mbits 3.0 Volt-only serial Flash memories. These devices are designed to use
a single low voltage, range from 2.7 Volt to 3.6 Volt, power supply to perform read, erase and program operations.
The devices can be programmed in standard EPROM programmers as well.
The device is optimized for use in many commercial applications where low-power and low-voltage operation are
essential. The Pm25LV512/010 is enabled through the Chip Enable pin (CE#) and accessed via a 3-wire interface
consisting of Serial Data Input (Sl), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are com-
pletely self-timed.
Block Write protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled
by programming the status register. Separate write enable and write disable instructions are provided for additional
data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts
to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial
sequence.
Programmable Microelectronics Corp.
1
Issue Date: December, 2003, Rev: 1.3
Pm25LV512 / Pm25LV010
The Pm25LV512/010 are manufactured on PMC's advanced nonvolatile CMOS technology, P-FLASHTM. The de-
vices are offered in 8-pin JEDEC SOIC and 8-contact WSON packages with operation frequency up to 25 MHz.
2
Programmable Microelectronics Corp.
Issue Date: December, 2003, Rev: 1.3
PMC
Pm25LV512/010
PIN DESCRIPTIONS
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CONNECTION DIAGRAMS
8-Pin SOIC
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T o p V i e w
3
Programmable Microelectronics Corp.
Issue Date: December, 2003, Rev: 1.3
PMC
Pm25LV512/010
PRODUCT ORDERING INFORMATION
Pm25LVxxx -25 S C E
Temperature Range
C = Commercial (0C to +70C)
Package Type
S = 8-pin SOIC (8S)
Q = 8-contact WSON (8Q)
Operating Speed
25 MHz
PMC Device Number
Pm25LV512 (512 Kbit)
Pm25LV010 (1 Mbit)
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Environmental Attribute
E = Lead-free (Pb-free) Package
Blank = Standard Package
4
Programmable Microelectronics Corp.
Issue Date: December, 2003, Rev: 1.3
PMC
Pm25LV512/010
BLOCK DIAGRAM
High Voltage
G e n e r a t o r
Control Logic
Serial /Parallel convert Logic
A d d r e s s L a t c h
& C o u n t e r
2KBit Page Buffer
Status
Register
Memory Array
Y-DECODER
X - D E C O D E R
Instruction Decoder
SPI Chip Block Diagram
5
Programmable Microelectronics Corp.
Issue Date: December, 2003, Rev: 1.3
PMC
Pm25LV512/010
Pm25LV512/010 can be driven by a microcontroller on the SPI bus as shown in Figure 1. The serial communication
term definitions are in the following section.
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the Pm25LV512/010 always operates as a slave.
TRANSMITTER/RECEIVER: The Pm25LV512/010 has separate pins designated for data transmission (SO) and
reception (Sl).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CE# going low, the first byte will be received. This byte
contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the Pm25LV512/010, and the serial
output pin (SO) will remain in a high impedance state until the falling edge of CE# is detected again. This will
reinitialize the serial communication.
SERIAL INTERFACE DESCRIPTION
SPI Interface with
(0, 0) or (1, 1)
S D O
SDI
S C K
S C K
S O
SI
Bus Master
C S 3
C S 2 C S 1
C E #
W P # H O L D #
H O L D #
H O L D #
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven, High or Low as appropriate.
S C K S O
SI
S C K
S O
SI
C E #
W P #
C E #
W P #
Figure 1. Bus Master and SPI Memory Devices