RELEASED
PM3386
DATASHEET
PMC-1991129
ISSUE 7
DUAL GIGABIT ETHERNET CONTROLLER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM3386
S/UNI-2xGE
DUAL GIGABIT ETHERNET
CONTROLLER
DATASHEET
PROPRIETARY AND CONFIDENTIAL
RELEASED
ISSUE 7: JULY 2001
RELEASED
PM3386
DATASHEET
PMC-1991129
ISSUE 7
DUAL GIGABIT ETHERNET CONTROLLER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
REVISION HISTORY
Issue
No.
Issue Date Originator
Details of Change
7
July 2001
Karen
Leandro
Release to Production Datasheet
Updated DC Characteristics with qualified
values
Added SERDES Mode
Added GMII/TBI Mode
Modified timing contained within SERDES
Transmit Data Timing
Modified timing contained within SERDES
Received Data Timing
6
Feb 2001
Karen
Leandro
Added to register descriptions.
5
Dec 2000
Karen
Leandro
Updated register defaults
4
June 2000
Stuart
Robinson
Added pinout and register section.
3
May 2000
Stuart
Robinson
Included Timing Diagrams
2
Nov 1999
Stuart
Robinson
Preliminary release
1
Sept 1999
Stuart
Robinson
Created Document.
RELEASED
PM3386
DATASHEET
PMC-1991129
ISSUE 7
DUAL GIGABIT ETHERNET CONTROLLER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
CONTENTS
1
DEFINITIONS .......................................................................................... 1
2
FEATURES .............................................................................................. 3
2.1
GENERAL ..................................................................................... 3
2.2
LINE SIDE INTERFACE................................................................ 3
2.3
GIGABIT ETHERNET MAC........................................................... 4
2.4
FLOW CONTROL ......................................................................... 4
2.5
STATISTICS .................................................................................. 4
3
APPLICATIONS ....................................................................................... 5
4
REFERENCES......................................................................................... 6
5
APPLICATION EXAMPLES ..................................................................... 7
6
BLOCK DIAGRAM ................................................................................. 10
7
DESCRIPTION ...................................................................................... 12
8
PIN DIAGRAM ....................................................................................... 15
9
PIN DESCRIPTION................................................................................ 16
10
FUNCTIONAL DESCRIPTION............................................................... 43
10.1 SERIALIZER-DESERIALIZER (SERDES) .................................. 43
10.2 ENHANCED GIGABIT MEDIA ACCESS CONTROL (EGMAC) .. 44
10.2.1 EGMAC GENERAL .......................................................... 44
10.2.2 EGMAC EGRESS DIRECTION........................................ 44
10.2.3 EGMAC INGRESS DIRECTION....................................... 45
10.2.4 EGMAC FLOW CONTROL - MAC CONTROL
SUBLAYER....................................................................... 46
10.2.5 EGMAC AUTO-NEGOTIATION ........................................ 48
RELEASED
PM3386
DATASHEET
PMC-1991129
ISSUE 7
DUAL GIGABIT ETHERNET CONTROLLER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
10.2.6 EGMAC ADDRESS FILTER LOGIC ................................. 48
10.3 MANAGEMENT STATISTICS (MSTAT) ...................................... 48
10.4 POS-PHY LEVEL 3 PHYSICAL LAYER INTERFACE ................. 49
10.4.1 POS-PHY LEVEL 3 GENERAL ........................................ 49
10.4.2 POS-PHY LEVEL 3 INGRESS PHYSICAL LAYER
INTERFACE (PL3IP) ........................................................ 49
10.4.3 POS-PHY LEVEL 3 EGRESS PHYSICAL LAYER
INTERFACE (PL3EP)....................................................... 50
10.5 MICROPROCESSOR INTERFACE ............................................ 51
10.6 JTAG TEST ACCESS PORT INTERFACE.................................. 51
11
NORMAL MODE REGISTER DESCRIPTION ....................................... 52
12
TEST FEATURES DESCRIPTION ...................................................... 234
12.1 JTAG TEST PORT .................................................................... 235
13
OPERATION ........................................................................................ 236
13.1 POWER ON SEQUENCE ......................................................... 236
13.2 SYSTEM RESET....................................................................... 236
13.3 GMII VS. SERDES CONFIGURATION ..................................... 237
13.4 SYSTEM CLOCKING................................................................ 237
13.4.1 PHY-LINK FREQUENCY SELECTION........................... 237
13.4.2 GMII MODE CLOCKING ................................................ 237
13.4.3 SERDES MODE CLOCKING ......................................... 238
13.5 INTERFACING TO ODL ............................................................ 238
13.6 GMII INTERFACING ................................................................. 239
13.7 TBI INTERFACING.................................................................... 240
13.8 ENABLING AND DISABLING DATA FLOWS ............................ 241
RELEASED
PM3386
DATASHEET
PMC-1991129
ISSUE 7
DUAL GIGABIT ETHERNET CONTROLLER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
13.8.1 ENABLING AND DISABLING INGRESS DATA FLOW... 241
13.8.2 ENABLING AND DISABLING EGRESS DATA FLOW.... 241
13.9 REGISTER ACCESS PROCEDURES ...................................... 241
13.9.1 PL3IP REGISTER ACCESS PROCEDURE ................... 242
13.9.2 PL3EP REGISTER ACCESS PROCEDURE.................. 242
13.9.3 EGMAC REGISTER ACCESS PROCEDURE................ 242
13.10 FRAME DATA AND BYTE FORMAT ......................................... 243
13.11 SERDES LOOPBACK............................................................... 244
13.12 GMII LOOPBACK...................................................................... 244
13.13 IFG MANIPULATION................................................................. 245
13.14 FRAME LENGTH SUPPORT .................................................... 245
13.15 TRANSMIT PADDING AND CRC GENERATION ..................... 246
13.16 MII OPERATIONS ..................................................................... 248
13.16.1 MII READ ACCESS ................................................... 248
13.16.2 MII WRITE ACCESS ................................................. 248
13.17 AUTO-NEGOTIATION............................................................... 248
13.17.1 MONITORING AUTO-NEGOTIATION ....................... 250
13.17.2 MODIFYING AUTO-NEGOTIATION .......................... 250
13.17.3 CONTROL OF AUTO-NEGOTIATION ....................... 250
13.18 TX_ER ASSERTION CRITERIA................................................ 250
13.19 FRAME FILTERING .................................................................. 251
13.19.1 GROUP MULTICAST ADDRESS FILTERING ........... 251
13.19.2 EXACT MATCH FILTER PROGRAM OPTIONS........ 252
13.19.3 EXACT MATCH FILTER OPERATION ...................... 253
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