PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PM4318
OCTLIU
OCTAL E1/T1/J1 LINE INTERFACE
DEVICE
DATASHEET
PROPRIETARY AND CONFIDENTIAL
PRELIMINARY
ISSUE 3: APRIL 2001
PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
i
CONTENTS
1
FEATURES........................................................................................................................ 1
1.1
EACH RECEIVER SECTION: .............................................................................. 2
1.2
EACH TRANSMITTER SECTION:....................................................................... 2
2
APPLICATIONS................................................................................................................. 4
3
REFERENCES .................................................................................................................. 5
4
APPLICATION EXAMPLES............................................................................................... 7
5
BLOCK DIAGRAM............................................................................................................. 9
6
DESCRIPTION ................................................................................................................ 11
7
PIN DIAGRAM................................................................................................................. 12
8
PIN DESCRIPTION......................................................................................................... 13
9
FUNCTIONAL DESCRIPTION........................................................................................ 35
9.1
OCTANTS........................................................................................................... 35
9.2
RECEIVE INTERFACE ...................................................................................... 35
1.3
CLOCK AND DATA RECOVERY (CDRC).......................................................... 36
1.4
RECEIVE JITTER ATTENUATOR (RJAT) ......................................................... 38
1.5
T1 INBAND LOOPBACK CODE DETECTOR (IBCD) ....................................... 38
1.6
T1 PULSE DENSITY VIOLATION DETECTOR (PDVD) ................................... 39
1.7
PERFORMANCE MONITOR COUNTERS (PMON).......................................... 39
1.8
PSEUDO RANDOM BINARY SEQUENCE GENERATION AND DETECTION
(PRBS) ............................................................................................................... 39
1.9
T1 INBAND LOOPBACK CODE GENERATOR (XIBC)..................................... 39
1.10
PULSE DENSITY ENFORCER (XPDE)............................................................. 39
1.11
TRANSMIT JITTER ATTENUATOR (TJAT) ....................................................... 40
1.12
LINE TRANSMITTER......................................................................................... 44
1.13
TIMING OPTIONS (TOPS) ................................................................................ 44
PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
ii
1.14
SCALEABLE BANDWIDTH INTERCONNECT (SBI) INTERFACE ................... 44
1.14.1 INTERFACING OCTLIUS TO A HIGH DENSITY FRAMER.................. 45
1.15
SBI EXTRACTER AND PISO............................................................................. 46
1.16
SBI INSERTER AND SIPO ................................................................................ 46
1.17
SBI TO CLK/DATA CONVERTER ...................................................................... 46
1.18
SERIAL PROM INTERFACE.............................................................................. 46
1.19
JTAG TEST ACCESS PORT.............................................................................. 48
1.20
MICROPROCESSOR INTERFACE ................................................................... 48
2
NORMAL MODE REGISTER DESCRIPTION ................................................................ 49
2.1
NORMAL MODE REGISTER MEMORY MAP................................................... 50
3
TEST FEATURES DESCRIPTION................................................................................ 169
3.1
JTAG TEST PORT............................................................................................ 169
4
OPERATION.................................................................................................................. 172
4.1
CONFIGURING THE OCTLIU FROM RESET................................................. 172
4.2
SERVICING INTERRUPTS.............................................................................. 172
4.3
USING THE PERFORMANCE MONITORING FEATURES ............................ 173
4.4
USING THE TRANSMIT LINE PULSE GENERATOR ..................................... 173
4.5
USING THE LINE RECEIVER ......................................................................... 194
4.6
USING THE PRBS GENERATOR AND DETECTOR ...................................... 201
4.7
LOOPBACK MODES ....................................................................................... 201
4.7.1
LINE LOOPBACK................................................................................ 201
4.7.2
DIAGNOSTIC DIGITAL LOOPBACK .................................................. 202
4.8
JTAG SUPPORT .............................................................................................. 202
4.8.1
TAP CONTROLLER ............................................................................ 204
5
FUNCTIONAL TIMING .................................................................................................. 210
5.1
SBI BUS INTERFACE TIMING ........................................................................ 210
PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iii
5.2
LINE CODE VIOLATION INSERTION ............................................................. 211
5.3
ALARM INTERFACE........................................................................................ 213
6
ABSOLUTE MAXIMUM RATINGS ................................................................................ 214
7
D.C. CHARACTERISTICS ............................................................................................ 215
8
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ............................. 217
9
OCTLIU TIMING CHARACTERISTICS......................................................................... 221
9.1
RSTB TIMING (FIGURE 33) ............................................................................ 221
9.2
XCLK INPUT TIMING (FIGURE 34)................................................................. 221
9.3
TRANSMIT SERIAL INTERFACE (FIGURE 35) .............................................. 222
9.4
RECEIVE SERIAL INTERFACE (FIGURE 36)................................................. 223
9.5
SBI INTERFACE (FIGURE 37 TO FIGURE 39)............................................... 224
9.6
SERIAL PROM (SPI) INTERFACE (FIGURE 40) ............................................ 227
9.7
ALARM INTERFACE (FIGURE 41).................................................................. 228
9.8
INGRESS CLK/DATA INTERFACE (FIGURE 42)............................................ 228
9.9
EGRESS CLK/DATA INTERFACE (FIGURE 43) ............................................. 229
9.10
JTAG PORT INTERFACE (FIGURE 44) .......................................................... 230
10
ORDERING AND THERMAL INFORMATION .............................................................. 232
11
MECHANICAL INFORMATION ..................................................................................... 233
PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iv
LIST OF FIGURES
FIGURE 1
T1/E1 FRAMER/TRANSCEIVER APPLICATION................................................. 7
FIGURE 2
HIGH DENSITY T1/E1 FRAMER/TRANSCEIVER APPLICATION...................... 7
FIGURE 3
HIGH DENSITY LEASED LINE CIRCUIT EMULATION APPLICATION.............. 7
FIGURE 4
METRO OPTICAL ACCESS EQUIPMENT .......................................................... 8
FIGURE 5
OCTLIU BLOCK DIAGRAM LIUS ENABLED ................................................... 9
FIGURE 6
OCTLIU BLOCK DIAGRAM SBI TO CLK/DATA CONVERTER, LIUS
DISABLED .......................................................................................................... 10
FIGURE 7
PIN DIAGRAM.................................................................................................... 12
FIGURE 8
EXTERNAL ANALOGUE INTERFACE CIRCUITS ............................................ 35
FIGURE 9
T1 JITTER TOLERANCE ................................................................................... 37
FIGURE 10
COMPLIANCE WITH ITU-T SPECIFICATION G.823 FOR E1 INPUT JITTER . 38
FIGURE 11
TJAT JITTER TOLERANCE ............................................................................... 41
FIGURE 12
TJAT MINIMUM JITTER TOLERANCE VS. XCLK ACCURACY........................ 42
FIGURE 13
TJAT JITTER TRANSFER.................................................................................. 43
FIGURE 14
SBI TO FRAMER LINE SIDE INTERFACE........................................................ 45
FIGURE 15
SERIAL PROM CASCADE INTERFACE ........................................................... 46
FIGURE 16
SERIAL PROM COMMAND FORMAT ............................................................... 47
FIGURE 17
TRANSMIT TIMING OPTIONS........................................................................... 75
FIGURE 18
LINE LOOPBACK............................................................................................. 202
FIGURE 19
DIAGNOSTIC DIGITAL LOOPBACK................................................................ 202
FIGURE 20
BOUNDARY SCAN ARCHITECTURE ............................................................. 203
FIGURE 21
TAP CONTROLLER FINITE STATE MACHINE ............................................... 205
FIGURE 22
INPUT OBSERVATION CELL (IN_CELL) ........................................................ 208
FIGURE 23
OUTPUT CELL (OUT_CELL) OR ENABLE CELL (ENABLE).......................... 208
FIGURE 24
BIDIRECTIONAL CELL (IO_CELL) .................................................................. 209
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