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Электронный компонент: PM4328-PI

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STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PM4328
TECT3
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED M13 MULTIPLEXER
DATASHEET
PROPRIETARY AND CONFIDENTIAL
ISSUE 1: AUGUST 2001
STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL
i
CONTENTS
1
FEATURES...............................................................................................1
2
APPLICATIONS...................................................................................... 11
3
REFERENCES .......................................................................................12
4
APPLICATION EXAMPLES ....................................................................15
5
BLOCK DIAGRAM..................................................................................16
5.1
TOP LEVEL BLOCK DIAGRAM...................................................16
5.2
M13 MULTIPLEXER MODE BLOCK DIAGRAM..........................18
5.3
DS3 FRAMER ONLY BLOCK DIAGRAM.....................................18
6
DESCRIPTION .......................................................................................20
7
PIN DIAGRAM ........................................................................................25
8
PIN DESCRIPTION ................................................................................26
9
FUNCTIONAL DESCRIPTION ...............................................................55
9.1
T1 FRAMER (T1-FRMR)..............................................................55
9.2
E1 FRAMER (E1-FRMR) .............................................................55
9.3
PERFORMANCE MONITOR COUNTERS (T1/E1-PMON) .........62
9.4
BIT ORIENTED CODE DETECTOR (RBOC) ..............................63
9.5
HDLC RECEIVER (RDLC)...........................................................63
9.6
T1 ALARM INTEGRATOR (ALMI)................................................64
9.7
ELASTIC STORE (ELST) ............................................................65
9.8
SIGNALING ELASTIC STORES (RX-SIG-ELST AND TX_SIG-
ELST)...........................................................................................65
9.9
SIGNALING EXTRACTOR (SIGX)...............................................66
STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL
ii
9.10 RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC) ......67
9.11 BASIC TRANSMITTER (XBAS)...................................................67
9.12 E1 TRANSMITTER (E1-TRAN) ...................................................68
9.13 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC) ....68
9.14 SIGNALING ALIGNER (SIGA) .....................................................68
9.15 BIT ORIENTED CODE GENERATOR (XBOC)............................69
9.16 HDLC TRANSMITTERS (TDPR) .................................................69
9.17 T1 AUTOMATIC PERFORMANCE REPORT GENERATION
(APRM) ........................................................................................70
9.18 RECEIVE AND TRANSMIT DIGITAL JITTER ATTENUATOR (RJAT,
TJAT) ...........................................................................................71
9.19 TIMING OPTIONS (TOPS) ..........................................................77
9.20 PSEUDO RANDOM BINARY SEQUENCE GENERATION AND
DETECTION (PRBS) ...................................................................77
9.21 PSEUDO RANDOM PATTERN GENERATION AND DETECTION
(PRGD) ........................................................................................77
9.22 DS3 FRAMER (DS3-FRMR) ........................................................78
9.23 PERFORMANCE MONITOR ACCUMULATOR (DS3-PMON) .....80
9.24 DS3 TRANSMITTER (DS3-TRAN) ..............................................81
9.25 M23 MULTIPLEXER (MX23)........................................................82
9.26 DS2 FRAMER (DS2-FRMR) ........................................................82
9.27 M12 MULTIPLEXER (MX12)........................................................84
9.28 EGRESS SYSTEM INTERFACE (ESIF)......................................85
9.29 INGRESS SYSTEM INTERFACE (ISIF) ......................................91
9.30 EXTRACT SCALEABLE BANDWIDTH INTERCONNECT (EXSBI)
.....................................................................................................96
STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL
iii
9.31 INSERT SCALEABLE BANDWIDTH INTERCONNECT (INSBI) .97
9.32 SCALEABLE BANDWIDTH INTERCONNECT PISO (SBIPISO).98
9.33 SCALEABLE BANDWIDTH INTERCONNECT SIPO (SBISIPO).98
9.34 JTAG TEST ACCESS PORT........................................................98
9.35 MICROPROCESSOR INTERFACE .............................................98
10
NORMAL MODE REGISTER DESCRIPTION ...................................... 118
11
TEST FEATURES DESCRIPTION ....................................................... 119
11.1 JTAG TEST PORT .....................................................................121
12
OPERATION.........................................................................................134
12.1 DS3 FRAME FORMAT...............................................................134
12.2 SERVICING INTERRUPTS .......................................................136
12.3 USING THE PERFORMANCE MONITORING FEATURES.......136
12.4 USING THE INTERNAL FDL TRANSMITTER...........................140
12.5 USING THE INTERNAL DATA LINK RECEIVER.......................144
12.6 T1 AUTOMATIC PERFORMANCE REPORT FORMAT.............148
12.7 USING THE PER-CHANNEL SERIAL CONTROLLERS............150
12.8 T1/E1 FRAMER LOOPBACK MODES ......................................151
12.9 DS3 LOOPBACK MODES .........................................................154
12.10 SBI BUS DATA FORMATS.........................................................157
12.11 H-MVIP DATA FORMAT.............................................................166
12.12 SERIAL CLOCK AND DATA FORMAT .......................................170
12.13 PRGD PATTERN GENERATION ...............................................170
12.14 JTAG SUPPORT........................................................................175
13
FUNCTIONAL TIMING .........................................................................183
STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
PROPRIETARY AND CONFIDENTIAL
iv
13.1 DS3 LINE SIDE INTERFACE TIMING .......................................183
13.2 DS3 SYSTEM SIDE INTERFACE TIMING ................................185
13.3 SBI DROP BUS INTERFACE TIMING .......................................187
13.4 SBI ADD BUS INTERFACE TIMING ..........................................188
13.5 EGRESS H-MVIP LINK TIMING ................................................188
13.6 INGRESS H-MVIP LINK TIMING ...............................................189
13.7 EGRESS SERIAL CLOCK AND DATA INTERFACE TIMING ....190
13.8 INGRESS SERIAL CLOCK AND DATA INTERFACE TIMING ...195
14
ABSOLUTE MAXIMUM RATINGS........................................................199
15
D.C. CHARACTERISTICS....................................................................200
16
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS......202
17
TECT3 TIMING CHARACTERISTICS ..................................................206
18
ORDERING AND THERMAL INFORMATION ......................................234
19
MECHANICAL INFORMATION.............................................................235
LIST OF FIGURES
FIGURE 1: CHANNELIZED DS3 CIRCUIT EMULATION APPLICATION .........15
FIGURE 2: HIGH DENSITY FRAME RELAY APPLICATION ............................15
FIGURE 3: TECT3 BLOCK DIAGRAM..............................................................17
FIGURE 4: M13 MULTIPLEXER BLOCK DIAGRAM ........................................18
FIGURE 5: DS3 FRAMER ONLY MODE BLOCK DIAGRAM............................19
FIGURE 6: PIN DIAGRAM ................................................................................25
FIGURE 7: CRC MULTIFRAME ALIGNMENT ALGORITHM ............................59