MSP7130
PMC-2052574, Issue 2
Copyright PMC-Sierra, Inc. 2006
All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers' internal use.
Multi-Service Processor
PRODUCT OVERVIEW
The MSP7130, a member of PMC-Sierra's MSP7100 Series of multi-
service processors, is a Residential Gateway SoC designed to meet the
performance, QoS, remote management, and security needs of multi-
service residential gateways.
Turning the Telco and ISP visions of the digital home into reality and
meeting IP service revenue goals requires a new, higher-performing
class of residential gateway that provides home network QoS,
manageability, and security. This new breed of residential gateway
ensures simultaneous functionality and quality of voice, video, and
data services delivered using the home network. The MSP7130
provides the packet processing performance and advanced remote
management and diagnostic functionalities needed to reach and
surpass these immediate goals. The MSP7130 has sufficient
processing headroom to support evolving IP service definitions while
servicing video data rates.
The MSP7100 Series is supported by a powerful software development
kit (SDK) and comes with production-ready software components
including the PMC Fast Data-Path high-performance networking stack,
PMC VPM VoIP firmware suite, and a management framework that
allows for easy integration of management agents. The SDK enables
customers to quickly and easily design high-performance, feature-
rich VoIP-enabled communication equipment for use within the
customer premise.
A key element of the SDK is the PMC Fast Data-Path. This software is
designed specifically for the QoS requirements of triple-play RGs and
supports complete TR-098 data models required for comprehensive
TR-069 remote manageability. For more detail on the software devel-
opment environment, refer to the MSP7100 Series SDK Product Brief.
PRODUCT HIGHLIGHTS
PMC-Sierra's residential gateway solution is able to perform complex
traffic management, routing, bridging and firewalling tasks on a large
amount of simultaneous traffic transiting both the LAN and WAN
networks. The MSP7100 gateway solution provides:
A 300 percent packet throughput improvement compared to single-
threaded processors of similar frequency;
Guaranteed data path performance through Dynamic Multi-
Processing Core technology, featuring an advanced QoS feature set
and enhanced control and visibility for remote management;
Hardware IPSec acceleration for enhanced security features;
Robust VoIP terminal adaptor functionality, which is field-hardened
and production-deployed worldwide; and
An Open Source programming model that leverages standard tools
and a large software ecosystem.
BLOCK DIAGRAM
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32 b
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1
66 M
H
z
BIU
Memory
Interface
10/100 Ethernet MAC
System Logic and Peripherals
EJTAG
Trace/debug
10/100 Ethernet MAC
USB
PHY
USB
Modem
CPU Shim
+ CIC
Denali
DDR
Con-
troller
Security
Engine
DDR DRAM
16 bits 166 MHz
USB 2.0
host/device
(R)MII
(R)MII
EJTAG
SMPI IF
Timer x 2
TWI
GPIO
UART x 2
Local Bus
TDM IF
MIPS32
400 MHz
I Cache
D Cache
Ext IRQ
PCI Interface
CUL2
Converter
UL2
SAR
CUL2
Preliminary
Product Brief
MSP7130 Multi-Service Processor
Corporate Head Office:
PMC-Sierra, Inc.
Mission Towers One
3975 Freedom Circle
Santa Clara, CA, 95054, U.S.A.
Tel: 1.408.239.8000
Fax: 1.408. 492.1157
PMC-2052574 (
P2) Copyright PMC-Sierra, Inc. 2006. All rights
reserved. For a complete list of PMC-Sierra's trademarks , visit
www.pmc-sierra.com/legal/. Other product and company names
mentioned herein may be the trademarks of their respective owners.
For corporate information, send email to: info@pmc-sierra.com.
All product documentation is available on our web site at:
www.pmc-sierra.com.
Operations Head Office:
PMC-Sierra, Inc.
100-2700 Production Way
Burnaby, BC V5A 4X1 Canada
Tel: 1.604.415.6000
Fax: 1.604.415.6200
PRODUCT DETAILS
PROCESSOR
400-MHz Multi-Threaded, MIPS32 core with DSP extensions
Enhanced inter-thread communications support
EJTAG interface
Internal and external processor trace support
TDM INTERFACE
Glue-less interface to SLIC/SLACs and DAAs.
32-channel cross-connect with TDM-TDM and TDM to VoIP channel
switching
PERIPHERALS
DDR1 or DDR2 interface
Dual 10/100 MACs with MII/RMII Interfaces
PCI version 2.3 host interface
Low-, full-, and high-speed USB 2.0 (host or device mode)
External Local Bus interface (for flash connections, etc)
IPSec HW acceleration
Integrated DMA engines for Ethernet MAC, Security Engine, USB, TDM
interface, and block copy engine
Two external timer outputs
Two UARTs
SPI/MPI serial interface
Two-wire serial interface
20 GPIO pins
Eight dedicated external interrupt inputs
WAN
Ethernet uplink
Support for DSL uplink via CUL2 interface
HW SAR with ATM TM 4.1, 16 PVCs supported
BUS ARCHITECTURE
32-bit, 166-MHz Multi-Service Bus
Multi-master access
5.3 Gbit/s throughput
Four-way bus-switch to enable simultaneous transactions between
bus sub-systems
Support for three transaction priority levels
ELECTRICAL & PACKAGE
416-pin package
3.3 V I/O, 1.0 V core, 2.5 V (DDR1) or 1.8 V (DDR2)
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