S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239
ISSUE 6
SATURN USER NETWORK INTERFACE (155-QUAD)
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PM5349
S/UNI-QUAD
SATURN
USER NETWORK INTERFACE
(155-QUAD)
DATASHEET
ISSUE 6: JULY 1999
155- QUAD
S/
UNI-
S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239
ISSUE 6
SATURN USER NETWORK INTERFACE (155-QUAD)
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
REVISION HISTORY
Issue
No.
Issue Date
Details of Change
6
July, 1999
General Update:
Section 4: Augmented the DEFINITIONS table
Section 9.6: Changed TDO output drive from 2mA to 1mA, changed
other DC currents from 16mA to 4mA and 4mA to 2mA
Section 11: Added RPOP PAISCONV and LOPCONV status bits in
Register 0x30
Section 11: Clarified EPRDIEN register bit description in Register
0x40
Section 11: Added H4INSB register bit to Register 0x82
Section 11: Fixed logic level specification in Register 0x91
Section 11: Changed Z1/S1_CAP bit description in Register 0xE2
Section 13.8: Enhanced Power Supply Sequencing information
Section 13.9: Analog Power Supply Filtering new recommendations
Section 16: DC Characteristics updated into include IDDOP values
Section 19: Maximum temperature changed from TC = +85C to TA
= +85C. Added Airflow versus Theta JA chart.
5
January, 1999
General update
4
September, 1998
General Update
S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239
ISSUE 6
SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-SIERRA, Inc., and for its Customers' Internal Use
I
CONTENTS
1
FEATURES ........................................................................................................................1
1.1
GENERAL.............................................................................................................1
1.2
THE SONET RECEIVER......................................................................................1
1.3
THE RECEIVE ATM PROCESSOR......................................................................2
1.4
THE SONET TRANSMITTER...............................................................................2
1.5
THE TRANSMIT ATM PROCESSOR ...................................................................3
2
APPLICATIONS .................................................................................................................4
3
REFERENCES ..................................................................................................................5
4
DEFINITIONS ....................................................................................................................6
5
APPLICATION EXAMPLES ...............................................................................................7
6
BLOCK DIAGRAM .............................................................................................................8
7
DESCRIPTION ..................................................................................................................9
8
PIN DIAGRAM .................................................................................................................11
9
PIN DESCRIPTION .........................................................................................................12
9.1
LINE SIDE INTERFACE SIGNALS ....................................................................12
9.2
UTOPIA LEVEL 2 SYSTEM INTERFACE ..........................................................15
9.3
MICROPROCESSOR INTERFACE SIGNALS ...................................................23
9.4
JTAG TEST ACCESS PORT (TAP) SIGNALS ....................................................25
9.5
ANALOG SIGNALS ............................................................................................26
9.6
POWER AND GROUND.....................................................................................26
10
FUNCTIONAL DESCRIPTION ........................................................................................32
10.1
RECEIVE LINE INTERFACE (CRSI) ..................................................................32
10.1.1
CLOCK RECOVERY.......................................................................32
10.1.2
SERIAL TO PARALLEL CONVERTER ...........................................33
10.2
RECEIVE SECTION OVERHEAD PROCESSOR (RSOP) ................................33
10.2.1
FRAMER .........................................................................................33
10.2.2
DESCRAMBLE................................................................................34
10.2.3
ERROR MONITOR..........................................................................34
10.2.4
LOSS OF SIGNAL ..........................................................................34
10.2.5
LOSS OF FRAME ...........................................................................35
S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239
ISSUE 6
SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-SIERRA, Inc., and for its Customers' Internal Use
II
10.3
RECEIVE LINE OVERHEAD PROCESSOR (RLOP).........................................35
10.3.1
LINE RDI DETECT..........................................................................35
10.3.2
LINE AIS DETECT ..........................................................................35
10.3.3
ERROR MONITOR BLOCK ............................................................35
10.4
THE RECEIVE APS, SYNCHRONIZATION EXTRACTOR AND BIT ERROR
MONITOR (RASE)..............................................................................................36
10.4.1
AUTOMATIC PROTECTION SWITCH CONTROL..........................36
10.4.2
BIT ERROR RATE MONITOR.........................................................37
10.4.3
SYNCHRONIZATION STATUS EXTRACTION................................37
10.5
RECEIVE PATH OVERHEAD PROCESSOR (RPOP)........................................38
10.5.1
POINTER INTERPRETER..............................................................38
10.5.2
SPE TIMING....................................................................................42
10.5.3
ERROR MONITOR..........................................................................42
10.6
RECEIVE ATM CELL PROCESSOR (RXCP) ....................................................43
10.6.1
CELL DELINEATION.......................................................................43
10.6.2
DESCRAMBLER .............................................................................44
10.6.3
CELL FILTER AND HCS VERIFICATION .......................................44
10.6.4
PERFORMANCE MONITOR ..........................................................46
10.7
TRANSMIT LINE INTERFACE (CSPI) ...............................................................46
10.7.1
CLOCK SYNTHESIS ......................................................................46
10.7.2
PARALLEL TO SERIAL CONVERTER ...........................................47
10.8
TRANSMIT SECTION OVERHEAD PROCESSOR (TSOP) ..............................47
10.8.1
LINE AIS INSERT ...........................................................................47
10.8.2
BIP-8 INSERT .................................................................................47
10.8.3
FRAMING AND IDENTITY INSERT ...............................................48
10.8.4
SCRAMBLER ..................................................................................48
10.9
TRANSMIT LINE OVERHEAD PROCESSOR (TLOP) ......................................48
10.9.1
APS INSERT ...................................................................................48
10.9.2
LINE BIP CALCULATE....................................................................48
10.9.3
LINE RDI INSERT ...........................................................................48
10.9.4
LINE FEBE INSERT........................................................................49
10.10
TRANSMIT PATH OVERHEAD PROCESSOR (TPOP) .....................................49
S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239
ISSUE 6
SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-SIERRA, Inc., and for its Customers' Internal Use
III
10.10.1
POINTER GENERATOR .................................................................49
10.10.2
BIP-8 CALCULATE..........................................................................50
10.10.3
FEBE CALCULATE.........................................................................50
10.11
TRANSMIT ATM CELL PROCESSOR (TXCP) ..................................................50
10.11.1
IDLE/UNASSIGNED CELL GENERATOR ......................................50
10.11.2
SCRAMBLER ..................................................................................50
10.11.3
HCS GENERATOR..........................................................................51
10.12
UTOPIA LEVEL 2 SYSTEM INTERFACE ..........................................................51
10.12.1
RECEIVE ATM INTERFACE ...........................................................51
10.12.2
TRANSMIT ATM INTERFACE.........................................................51
10.13
JTAG TEST ACCESS PORT...............................................................................52
10.14
MICROPROCESSOR INTERFACE ....................................................................52
11
NORMAL MODE REGISTER DESCRIPTION ................................................................59
12
TEST FEATURES DESCRIPTION ................................................................................193
12.1
MASTER TEST REGISTER .............................................................................193
12.2
TEST MODE 0 DETAILS..................................................................................195
12.3
JTAG TEST PORT ............................................................................................196
12.3.1
BOUNDARY SCAN CELLS...........................................................198
13
OPERATION ..................................................................................................................201
13.1
SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE .............201
13.1.1
ATM MAPPING..............................................................................201
13.1.2
TRANSPORT AND PATH OVERHEAD BYTES ............................202
13.2
ATM CELL DATA STRUCTURE ........................................................................204
13.3
BIT ERROR RATE MONITOR ..........................................................................205
13.4
CLOCKING OPTIONS......................................................................................206
13.5
LOOPBACK OPERATION ................................................................................208
13.6
JTAG SUPPORT ...............................................................................................212
13.6.1
TAP CONTROLLER ......................................................................213
13.6.1.1
STATES ............................................................................215
13.6.1.2
INSTRUCTIONS ..............................................................216
13.7
BOARD DESIGN RECOMMENDATIONS ........................................................217
13.8
POWER SUPPLY SEQUENCING ....................................................................218
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