PM5351
PMC-Sierra,Inc.
Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device
S/UNI-155-TETRA
PMC-1980862 (R3)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
2001 PMC-Sierra, Inc.
FEATURES
Quad channel ATM and Packet over
SONET OC-3c (155 Mbit/s) PHY.
Provides on-chip clock and data
recovery and clock synthesis.
Exceeds Bellcore-GR-253 jitter
requirements.
Inserts and extracts ATM cells or POS
packets into/from SONET SPE.
Filters and captures Automatic
Protection Switch byes (K1 and K2)
and detects APS byte failure.
Detects signal degrade and signal
failure thresholds crossing alarms.
Captures and debounces
synchronization status byte (S1).
Extracts and inserts the 16- or 64-byte
section trace (J0) and path trace (J1)
messages.
Extracts and inserts section/line data
communication channels (DCC).
Provides circuitry to meet holdover,
wander and long term stability.
Provides a generic 8-bit
microprocessor interface for device
control and register access.
Provides standard IEEE 1149.1 JTAG
test port for boundary scan.
ATM
Implements the ATM Forum User
Network Interface Specification.
Performs cell payload scrambling and
descrambling.
Provides a UTOPIA Level 2-compliant
system interface.
Provides synchronous 4-cell transmit
and receive FIFO buffers.
PACKET OVER SONET
Generic design that supports packet
based protocols like PPP, HDLC and
Frame Relay.
Implements the PPP over SONET/
SDH specification according to RFC
1619 and 1662 of the IETF.
Performs flag sequence detection and
insertion.
Performs CRC-CCITT and CRC-32
FCS generation and validation.
Performs byte stuffing and destuffing.
Checks for minimum and maximum
packet lengths.
PACKAGING
Low power, 3.3 V CMOS technology.
Packaged in a 304-pin Ball Grid Array
(BGA) package.
Industrial temp. range (-40 to +85C).
APPLICATIONS
WAN and Edge ATM Switches
Multiprotocol Switches
Layer 3 Switches
Routers, Packet Switches, and Hubs
DRCA[4:1]/DRP[4:1]
TXC[4:1]+
Microprocessor Interface
UT
OP
IA
L
e
vel
2 /
PO
S-
P
H
Y L
e
v
e
l 2
Sy
s
t
e
m
I
n
t
e
r
f
a
c
e
Transmit POS
Frame Processor
Receive ATM
Cell Processor
RDAT[15:0]
REOP
RERR
RMOD
RPRTY
RSOC/RSOP
RCA/RVAL
RADR[4:0]
RENB
RFCLK
PHY_OEN
TFCLK
TENB
TADR[4:0]
TCA
TSOC/TSOP
TPRTY
TDAT[15:0]
DTCA[4:1]/DTPA[4:1]
TEOP
TERR
TMOD
Path Trace
Buffer
Transmit Line
O/H Processor
Section
Trace Buffer
Receive Line
O/H Processor
WAN
S
y
n
c
hron
i
z
ati
o
n
Receive
APS,
Sync,
BERM
R
A
LR
M[4
:
1]
RF
P
O[4
:1]
RCL
K
[
4
:
1
]
RS
D[4
:
1
]
RS
DCL
K
[
4
:
1
]
RL
D[4
:
1
]
RL
DCL
K
[
4
:
1
]
TXC[4:1]-
TXD[4:1]+
TXD[4:1]-
ATB[3:0]
REFCLK
CP[4:1]
CN[4:1]
RXD[4:1]+
RXD[4:1]-
SD[4:1]
TD
O
TD
I
TM
S
TC
K
TR
S
T
B
D[7
:
0
]
A
[
1
0
:
0
]
A
L
E
CS
B
WR
B
RDB
RST
B
INT
B
Receive Section
O/H Processor
Section
DCC
Extract
Line
DCC
Extract
TS
D
[
4:
1
]
T
S
DCL
K[4
:
1
]
T
L
D
[
4:1]
T
L
D
C
L
K
[
4:1]
Section
DCC
Insert
Line
DCC
Insert
JTAG Test Access Port
Transmit Section
O/H Processor
TF
PI
TF
PO
TC
L
K
Transmit
Line
Interface
Receive
Line
Interface
Transmit ATM
Cell Processor
Receive POS
Frame Processor
Transmit Path
O/H Processor
Receive Path
O/H Processor
BLOCK DIAGRAM
Head Office:
PMC-Sierra, Inc.
8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
Preliminary PM5351 S/UNI-TETRA
Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
All product documentation is
available on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
PMC-1980862 (R3)
2001 PMC-Sierra, Inc. SATURN and
S/UNI-155-TETRA are trademarks of
PMC-Sierra, Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
TYPICAL APPLICATIONS
STS-3c (STM-1) ATM SWITCH PORT APPLICATION
SD4
Optical
Transceiver
Optical
Transceiver
UTOPIA Level 2
Interface
TxClk
ATM Layer Device
TxEnb
TxAddr[4:0]
TxClav
TxSOC
TxPrty
TxData[15:0]
RxClk
RxEnb
RxAddr[4:0]
RxClav
RxSOC
RxPrty
RxData[15:0]
RXD4+/-
TXD4+/-
Optical
Transceiver
Optical
Transceiver
TFCLK
PM5351
S/UNI
-155-TETRA
Quad 155 Mb/s ATM
and Packet Over
SONET/SDH Physical
Layer Device
TENB
TADR[4:0]
TCA
TSOC
TPRTY
TDAT[15:0]
RFCLK
RENB
RADR[4:0]
RCA
RSOC
RPRTY
RDAT[15:0]
SD3
RX3+/-
TXD3+/-
SD2
RX2+/-
TXD2+/-
SD1
RX1+/-
TXD1+/-
STS-3c (STM-1) PACKET OVER SONET APPLICATION
TFCLK
TENB
TADR[4:0]
STPA
DTPA[4:1]
TSOP
TPRTY
TDAT[15:0]
TMOD
TEOP
TERR
RFCLK
RENB
RADR[4:0]
DRPA[4:1]
RDAT[15:0]
RMOD
REOP
RVAL
RSOP
RPRTY
RERR
TFCLK
Link Layer Device
TENB
TADR[4:0]
STPA
DTPA[4:1]
TSOP
TPRTY
TDAT[15:0]
TMOD
TEOP
TERR
RFCLK
RADR[4:0]
DRPA[4:1]
RDAT[15:0]
RMOD
REOP
RVAL
RSOP
RPRTY
RERR
SD4
Optical
Transceiver
Optical
Transceiver
RXD4+/-
TXD4+/-
Optical
Transceiver
Optical
Transceiver
SD3
RX3+/-
TXD3+/-
SD2
RX2+/-
TXD2+/-
SD1
RX1+/-
TXD1+/-
PM5351
S/UNI
-155-TETRA
Quad 155 Mb/s ATM
and Packet Over
SONET/SDH Physical
Layer Device
RENB
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