TUPP+622
PM5363 TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM5363
TUPP+622
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR
FOR 622 MBIT/S INTERFACES
DATASHEET
RELEASED
ISSUE 4: JULY 2000
TUPP+622
PM5363 TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
REVISION HISTORY
Issue
No.
Issue Date
Details of Change
Issue 4
July 2000
Update for revision B device.
De-document TU3 Inband
Error feature. Added changes
to timing and operating
conditions. All Input Hold
Times for SCLK (19.44MHz)
are changed from 1ns to
1.5ns. All Output Max Prop
Delays for HSCLK
(77.76MHz) changed from
8ns to 9ns. All Output Min
Prop Delay for SCLK
(19.44MHz) changed from
2ns to 3.5ns. Operating
Condition for V
DD3.3
changed
from 3.3V
10% to 3.3V
0.3V and operating condition
for V
DD2.5
changed from 2.5V
10% to 2.5V 0.2V.
TUGEN Bit and TUGBYP Bit
description changed. Device
ID Revision Number, SOS Bit
description and Boundary
Scan ID changed.
Issue 3
Nov 1999
Update Data-sheet portion to
preliminary.
Issue 2
May 1999
Update pin and register
description.
Issue 1
December
1998
Document created.
TUPP+622
PM5363 TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
i
CONTENTS
1
FEATURES ............................................................................................1
2
APPLICATIONS .....................................................................................5
3
REFERENCES.......................................................................................6
4
DEFINITIONS ........................................................................................8
5
APPLICATION EXAMPLES ...................................................................9
5.1
STS-12 (STM-4) AGGREGATE INTERFACE..............................9
5.2
QUAD STS-3 (STM-1) AGGREGATE INTERFACE ..................10
5.3
STS-48 (STM-16) AGGREGATE INTERFACE.......................... 11
5.4
TUPP-PLUS COMPATIBILITY AND TUPP+622
FEATURE ENHANCEMENTS...................................................12
6
DESCRIPTION.....................................................................................13
7
PIN DIAGRAM .....................................................................................15
8
BLOCK DIAGRAM ...............................................................................16
9
PIN DESCRIPTION (304) ....................................................................17
10
FUNCTIONAL DESCRIPTION.............................................................88
10.1 INPUT BUS DEMULTIPLEXER ................................................89
10.2 OUTPUT BUS MULTIPLEXER..................................................90
10.3 TRIBUTARY PAYLOAD PROCESSOR (VTPP).........................91
10.3.1 CLOCK GENERATOR....................................................91
10.3.2 INCOMING TIMING GENERATOR.................................91
TUPP+622
PM5363 TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
ii
10.3.3 INCOMING MULTIFRAME DETECTOR.........................92
10.3.4 POINTER INTERPRETER .............................................92
10.3.5 PAYLOAD BUFFER........................................................96
10.3.6 OUTGOING TIMING GENERATOR ...............................96
10.3.7 POINTER GENERATOR ................................................97
10.4 TRIBUTARY PATH OVERHEAD PROCESSOR
(RTOP) ....................................................................................100
10.4.1 CLOCK GENERATOR..................................................101
10.4.2 TIMING GENERATOR .................................................101
10.4.3 ERROR MONITOR.......................................................101
10.4.4 IN-BAND ERROR REPORT .........................................103
10.4.5 EXTRACT.....................................................................104
10.5 TRIBUTARY TRACE BUFFER (RTTB) ...................................104
10.5.1 CLOCK GENERATOR..................................................104
10.5.2 TIMING GENERATOR .................................................105
10.5.3 EXTRACT.....................................................................105
10.5.4 ALARM MONITOR .......................................................105
10.5.5 BUFFER .......................................................................106
10.6 JTAG TEST ACCESS PORT ...................................................106
10.7 MICROPROCESSOR INTERFACE ........................................107
11
NORMAL MODE REGISTER DESCRIPTION ................................... 117
11.1
TOP LEVEL CONFIGURATION REGISTERS......................... 118
TUPP+622
PM5363 TUPP+622
DATASHEET
PMC-1981421
ISSUE 4
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR FOR 622 MBIT/S
INTERFACES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
iii
11.2
VTPP #1, VTPP #2 AND VTPP #3 REGISTERS ....................169
11.3
RTOP #1, RTOP #2 AND RTOP #3 REGISTERS ...................205
11.4
RTTB #1, RTTB #2 AND RTTB #3 REGISTERS.....................298
12
TEST FEATURES DESCRIPTION.....................................................325
12.1 I/O TEST MODE......................................................................332
12.2 JTAG TEST PORT ..................................................................364
13
OPERATION ......................................................................................376
13.1 CONFIGURATION OPTIONS .................................................376
13.2 STS-1 MODE ..........................................................................378
13.3 AU3 MODE..............................................................................378
13.4 AU4 MODE..............................................................................379
13.5 BYPASS OPTIONS .................................................................381
13.6 POWER SEQUENCING..........................................................382
13.7 JTAG SUPPORT .....................................................................382
13.7.1 TAP CONTROLLER .....................................................384
13.7.2 BOUNDARY SCAN INSTRUCTIONS...........................387
14
FUNCTIONAL TIMING.......................................................................389
15
ABSOLUTE MAXIMUM RATINGS .....................................................408
16
D.C. CHARACTERISTICS .................................................................409
17
MICROPROCESSOR INTERFACE TIMING
CHARACTERISTICS .........................................................................412
18
TUPP+622 TIMING CHARACTERISTICS .........................................420
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