TANDARD

RODUCT

PMC-Sierra, Inc.

PM5945 SAPI

PMC-940106 ISSUE 3, May 16, 1994

SAPI DAUGHTERBOARD

______________________________________________________________________________________________

C O N T E N T S

OVERVIEW........................................................................................................................

FUNCTIONAL DESCRIPTION.......................................................................................

DAUGHTERBOARD REGISTERS ................................................................................

INTERFACE DESCRIPTION..........................................................................................

SUNI REGISTER ADDRESS MAP...............................................................................

RECEIVE DROP SIDE TIMING......................................................................................

TRANSMIT DROP SIDE TIMING...................................................................................

CHARACTERISTICS.......................................................................................................

MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS.........................

APPENDIX A: PAL EQUATIONS ..................................................................................

APPENDIX B: MECHANICAL DRAWINGS .................................................................

APPENDIX C: MATERIAL LIST.....................................................................................

APPENDIX D: COMPONENT PLACEMENT...............................................................

APPENDIX E: SCHEMATICS........................................................................................

APPENDIX F: LAYOUT NOTES....................................................................................

APPENDIX G: LAYOUT ..................................................................................................

TANDARD

RODUCT

PMC-Sierra, Inc.

PM5945 SAPI

PMC-940106 ISSUE 3, May 16, 1994

SAPI DAUGHTERBOARD

______________________________________________________________________________________________

OVERVIEW

The PM5945 SAPI daughter board contains the PMC PM5345 SUNI-155 (SATURN
User Network Interface), the Cypress CY7B951 SONET/SDH Serial Transceiver (a
clock and data recovery and clock synthesis unit), and optical PMD in a complete
optical ATM (Asynchronous Transfer Mode) physical interface. The SUNI is an ATM
physical layer processor for a SONET STS-3C transmission system. This daughter
board has been designed to mate with National Semiconductor Corporation's
Vicksburg EISA adapter motherboard to form a complete evaluation system. The
SAPI daughter board is configured, monitored, and powered through a 100 pin
edge connector that mates with the Vicksburg motherboard. The motherboard
provides all of the software and decoding logic necessary to directly access all of the
registers on the SAPI board.

The SAPI line side interface uses any 9-pin duplex SC receptacle. The optical
Transceiver PMD device runs at 155.52 MHz. On the receive side, the receive
optical PMD connects to the clock and data recovery section of the Cypress
SONET/SDH Serial Transceiver (CY7B951). The output of the CY7B951 is ac-
coupled to the SUNI's bit serial input. On the transmit side, the SUNI's PECL data
outputs connect directly to the Cypress CY7B951 serial input which buffers the data
and outputs the data directly to the transmit optics. The CY7B951 can mux the
output data to the input of the PLL and transfer back the recovered clock and data to
the input of the SUNI for diagnostic purposes.

The SAPI drop side interface uses a 100 pin edge connector. The 22V10 PLDs
transform the SUNI drop side signals to comply with the UTOPIA like signals of the
Vicksburg motherboard. The receive drop side also incorporates an additional
FIFO, as the internal 4 cell FIFO of the SUNI device is insufficient to handle the
latency time between burst cell reads by the R-FRED device on the Vicksburg
motherboard.

TANDARD

RODUCT

PMC-Sierra, Inc.

PM5945 SAPI

PMC-940106 ISSUE 3, May 16, 1994

SAPI DAUGHTERBOARD

______________________________________________________________________________________________

FUNCTIONAL DESCRIPTION

Block Diagram

SUNI

UTOPIA Edge Connector Interface

tx line

bit serial

rx line

bit serial

Dropside FIFO interface

RXD+/-

CY7B951

TXD+

TXD-

UTOPIA

Interface

RXC+
RXC-

RXD+

RXD-

TXCI+

TXCI-

Optics

Tx+

Tx-

Rx+

Rx-

Rin+

Rin-

RClk+

RClk-

RSer+

Rser-

POCLK

PICLK

RSER

LOS Generate

PIN[7:0]

GPIN

/LFI

TXD+/-

FIFO

ID ROM

Tout+
Tout-

TClk+

TClk-

TSer+

TSer-

PAL

CLK

I/O

/Loop

RefClk+

RefClk-

19.44 MHz

Osc

S U N I

The SUNI is a monolithic integrated circuit that implements the SONET/SDH
processing and ATM mapping functions of a 155 Mbit/s SONET STS-3c User
Network Interface. It is the heart of the SAPI board; all traffic goes through the SUNI.
On the line side, the SUNI transmits SONET frames through the line interface and
receives frames from the line interface. On the drop side, the SUNI sinks cells
provided by the buffer interface and sources cells to the buffer interface. Below, the
SUNI is briefly described.

TANDARD

RODUCT

PMC-Sierra, Inc.

PM5945 SAPI

PMC-940106 ISSUE 3, May 16, 1994

SAPI DAUGHTERBOARD

______________________________________________________________________________________________

The SUNI receives SONET/SDH frames via a bit serial interface, and processes
section, line, and path overhead. It performs framing (A1, A2), descrambling, detects
alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2,
B3), accumulating error counts at each level for performance monitoring purposes.
Line and path far end block error indications (FEBE) are also accumulated. The
SUNI interprets the received payload pointers (H1, H2) and extracts the
synchronous payload envelope which carries the received ATM cell payload.

The SUNI frames to the ATM payload using cell delineation. Header check
sequence (HCS) error correction is provided. Idle/unassigned cells may be
dropped according to a programmable filter. Cells are also dropped upon detection
of an Uncorrectable HCS error. The ATM cell payloads are descrambled. The ATM
cells that are passed are written to a four cell FIFO buffer. The received cells are
read from the FIFO using a generic 8-bit wide datapath interface. Counts of received
ATM cell headers that are erred and uncorrectable, and also those that are erred
and correctable, are accumulated independently for performance monitoring
purposes.

The SUNI transmits SONET/SDH frames via a bit serial interface, and formats
section, line, and path overhead bytes appropriately. It performs framing pattern
insertion (A1, A2), scrambling, alarm signal insertion, and inserts section, line, and
path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring
at the far end. Line and path far end block error indications (FEBE) are also
inserted. The SUNI generates the payload pointer (H1, H2) and inserts the
synchronous payload envelope which carries the ATM cell payload. The SUNI also
supports the insertion of a large variety of errors into the transmit stream, such as
framing pattern errors, bit interleaved parity errors, and illegal pointers, which are
useful for system diagnostics and tester applications.

Transmit ATM cells are written to an internal four cell FIFO using a generic 8-bit wide
datapath interface. Idle/unassigned cells are automatically inserted when the
internal FIFO contains less than one cell. The SUNI provides generation of the
header check sequence and scrambles the payload of the ATM cells. Each of these
transmit ATM cell processing functions can be enabled or bypassed.

The SUNI is configured, controlled and monitored via the UTOPIA interface to the
Vicksburg motherboard.

For a complete description of the SUNI, please refer to PMC-Sierra's PM5345
datasheet.

Электронный компонент: PM5945