PMC-980489 (R2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC. AND FOR IT'S CUSTOMERS' INTERNAL USE
1999 PMC-Sierra, Inc.
PM7324
PMC-Sierra,Inc.
SATURN User Network Interface ATM Layer Solution
S/UNI-ATLAS
FEATURES
Monolithic single chip device which
handles bi-directional ATM Layer
functions including VPI/VCI address
translation, cell appending, policing
(ingress only), cell counting and OAM
requirements for 65536 VCs (virtual
connections).
Instantaneous bi-directional transfer
rate of 800 Mbit/s supports a bi-
directional cell transfer rate of
1.42x106 cells/s.
Ingress input interface supports an 8 or
16 bit PHY interface using direct
addressing for up to 4 PHY devices
(Utopia Level 1) and Multi-PHY
addressing for up to 32 PHY devices
(Utopia Level 2).
Ingress output interface supports an 8
or 16 bit SCI-PHY (52 - 64 byte cell)
interface (Utopia Level 1) to a switch
fabric.
Egress input and output interfaces
support an 8 or 16 bit SCI-PHY (52 -
64 byte cell) interface using direct
addressing for up to 4 PHY devices
(Utopia Level 1) and Multi-PHY
addressing for up to 32 PHY devices
(Utopia Level 2).
Compatible with a wide range of
switching fabrics and traffic
management architectures.
Ingress functionality includes a highly
flexible search engine that covers the
entire PHYID/VPI/VCI address range,
dual leaky bucket policing, per-VC cell
counts, OAM-FM and OAM-PM
processing.
Egress functionality includes direct
address lookup, per-VC cell counts,
OAM-FM and OAM-PM processing.
Per-PHY output buffering scheme
resolves the head-of-line blocking
issue.
Includes a FIFO buffered 16-bit
microprocessor bus interface for cell
insertion and extraction, deterministic
VC Table access, status monitoring
and configuration of the device.
Supports DMA access for cell
extraction.
The UTOPIA and external SRAM
interfaces are 52 MHz max.
POLICING
ITU-I.371, ATM Forum TM4.0
compliant, per-VC programmable dual
leaky bucket policing with a
programmable action (tag, discard, or
count only) for each bucket, each with
3 programmable 16 bit non-compliant
cell counts.
Per-PHY single leaky bucket policing
with a programmable action (tag,
discard, or count only)
Guaranteed Frame Rate (GFR)
Policing with Minimum Cell Rate
Frame Tagging.
OAM
ITU-I.610 compliant OAM on both
Ingress and Egress directions.
Complete Fault Management (AIS,
RDI, CC) processing, for VP/VC,
Segment/End-to-end flows on all VC's.
Complete Performance Monitoring
processing, for VP/VC, Segment/End-
to-end, Forward/Backward flows, on
256 Bi-directional VC's.
CELL COUNTING
Per-VC counts include CLP0 cells,
CLP1 cells, policing violations.
Per-PHY counts include CLP0 cells,
CLP1 cells, OAM cells, errored OAM
cells, unassigned/invalid cells and
policing violations.
Per-device counts include total cells
received/transmitted, and physical
layer cells.
PACKAGING
Provides a standard 5 signal P1149.1
JTAG test port for boundary scan
board test purposes.
Implemented in low power, 0.35
micron, 3.3 Volt CMOS technology
with 5 Volt tolerant and microprocessor
interface, 3.3V UTOPIA and external
synchronous SRAM interfaces.
Packaged in 432 pin ball grid array
(BGA) package.
APPLICATIONS
WAN ATM Core and Edge Switches
ATM Enterprise and Workgroup
Switches
Access Switches/Multiplexers
BLOCK DIAGRAM
Ingress
Input
Cell
Interface
Ingress
Search
Engine
Egress
Output
Cell
Interface
Microprocessor Interface
Egress
Microprocessor
Cell Interface
Ingress
Output
Cell
Interface
JTAG
Interface
Ingress
Backward
Cell
Interface
PHY
Statistics
Collection
Egress
Backward
Cell
Interface
SCI-PHY Level1/
Level2 Interface
(Master)
RDAT[15:0]
RPRTY
RRDENB[1]
RCA[1]
RADDR[4:3]/RCA[3:2]
RAVALID/RCA[4]
RSOC
RFCLK
RPOLL
ADDR[2:0]/RRDENB[4:2]
SCI-PHY Level1/
Level2 Interface
(Master)
TDAT[15:0]
TPRTY
TWRENB[1]
TCA[1]
TADDR[4:3]/TCA[3:2]
TAVALID/TCA[4]
TSOC
TFCLK
TPOLL
TADDR[2:0]/TWRENB[4:2]
SCI-PHY
Level1
Interface
(Slave)
ODAT[15:0]
OPRTY
OSOC
OFCLK
OTSEN
OCA
ORDENB
SCI-PHY Level1/
Level2 Interface
(Slave)
IDAT[15:0]
IPRTY
ISOC
IFCLK
ICA[1]
IADDR[4:3]/ICA[3:2]
IADDR[2:0]/IWRENB[4:2]
IPOLL
IWRENB[1]
IAVALID/ICA[4]
Ingress
Cell
Processor
Egress
Cell
Processor
IS
Y
S
CLK
IS
D
[
63:
0]
IS
P
[
7:0]
I
SA[
1
9
:
0
]
IS
R
W
B
IS
OE
B
I
SADS
B
To External Synchronous SRAM
ESD[
3
1
:
0
]
ES
P[
3
:
0
]
E
SA[
1
9
:
0
]
ESA
DSB
ES
R
W
B
ES
O
E
B
To External Synchronous SRAM
Ingress
Microprocessor
Cell Interface
Egress
Input
Cell
Interface
E
SYS
CL
K
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