PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
PM7346
S/UNI
-
QJET
TM
S/UNI-QJET
SATURN QUAD USER NETWORK
INTERFACE FOR J2/E3/T3
DATASHEET
PROPRIETARY AND CONFIDENTIAL
ISSUE 6: MAY 1999
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
REVISION HISTORY
Issue No.
Issue Date
Details of Change
6
May 14, 1999
The S/UNI-QJET requires a software
initialization sequence in order to
guarantee proper device operation and
long term reliability. Please refer to
Section 12.1 of this document for the
details on how to program this
sequence.
Updated the RFCLK and TFCLK pin
descriptions to reflect that these pins are
not 5V tolerant. Both pins are 3.3V only
input pins.
Documentation clarifications.
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE i
CONTENTS
1
FEATURES ............................................................................................... 1
2
APPLICATIONS ........................................................................................ 6
3
REFERENCES ......................................................................................... 7
4
APPLICATION EXAMPLES .................................................................... 10
5
BLOCK DIAGRAM.................................................................................. 13
6
DESCRIPTION ....................................................................................... 17
7
PIN DIAGRAM ........................................................................................ 21
8
PIN DESCRIPTION ................................................................................ 22
9
FUNCTIONAL DESCRIPTION ............................................................... 59
9.1
DS3 FRAMER.............................................................................. 59
9.2
E3 FRAMER ................................................................................ 61
9.3
J2 FRAMER ................................................................................. 63
9.3.1 J2 FRAME FIND ALGORITHMS ....................................... 65
9.4
PMON PERFORMANCE MONITOR ACCUMULATOR................ 68
9.5
RBOC BIT-ORIENTED CODE DETECTOR ................................. 68
9.6
RDLC FACILITY DATA LINK RECEIVER..................................... 69
9.7
SPLR PLCP LAYER RECEIVER ................................................. 70
9.8
ATMF ATM CELL DELINEATOR .................................................. 70
9.9
RXCP-50 RECEIVE CELL PROCESSOR ................................... 72
9.10
RXFF RECEIVE FIFO.................................................................. 74
9.11
CPPM CELL AND PLCP PERFORMANCE MONITOR ............... 75
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE ii
9.12
PRGD PSEUDO-RANDOM SEQUENCE
GENERATOR/DETECTOR .......................................................... 75
9.13
DS3 TRANSMITTER.................................................................... 76
9.14
E3 TRANSMITTER ...................................................................... 77
9.15
J2 TRANSMITTER....................................................................... 78
9.16
XBOC BIT ORIENTED CODE GENERATOR .............................. 79
9.17
TDPR FACILITY DATA LINK TRANSMITTER .............................. 79
9.18
SPLT SMDS PLCP LAYER TRANSMITTER ................................ 81
9.19
TXCP-50 TRANSMIT CELL PROCESSOR ................................. 82
9.20
TXFF TRANSMIT FIFO................................................................ 83
9.21
TTB TRAIL TRACE BUFFER ....................................................... 83
9.22
JTAG TEST ACCESS PORT ........................................................ 84
9.23
MICROPROCESSOR INTERFACE ............................................. 84
10
NORMAL MODE REGISTER DESCRIPTION........................................ 91
11
TEST FEATURES DESCRIPTION ....................................................... 294
11.1
TEST MODE 0 DETAILS ........................................................... 300
11.2
JTAG TEST PORT...................................................................... 305
12
OPERATION ......................................................................................... 308
12.1
SOFTWARE INITIALIZATION SEQUENCE ............................... 308
12.2
REGISTER SETTINGS FOR BASIC CONFIGURATIONS ........ 310
12.3
PLCP FRAME FORMATS .......................................................... 311
12.3.1 PLCP PATH OVERHEAD OCTET PROCESSING .......... 314
12.4
DS3 FRAME FORMAT .............................................................. 319
12.5
G.751 E3 FRAME FORMAT....................................................... 321
PM7346 S/UNI-QJET
DATASHEET
PMC-960835
ISSUE 6
SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE iii
12.6
G.832 E3 FRAME FORMAT....................................................... 323
12.7
J2 FRAME FORMAT .................................................................. 325
12.8
S/UNI-QJET CELL DATA STRUCTURE..................................... 327
12.9
RESETTING THE RXFF AND TXFF FIFOS .............................. 331
12.10 SERVICING INTERRUPTS........................................................ 331
12.11 USING THE PERFORMANCE MONITORING FEATURES ....... 332
12.12 USING THE INTERNAL FDL TRANSMITTER ........................... 333
12.13 USING THE INTERNAL DATA LINK RECEIVER ....................... 336
12.14 PRGD PATTERN GENERATION................................................ 341
12.14.1 GENERATING AND DETECTING REPETITIVE
PATTERNS ...................................................................... 341
12.14.2 COMMON TEST PATTERNS ...........................................
........................................................................................ 342
12.15 JTAG SUPPORT ........................................................................ 344
13
FUNCTIONAL TIMING ......................................................................... 353
14
ABSOLUTE MAXIMUM RATINGS........................................................ 380
15
D.C. CHARACTERISTICS .................................................................... 381
16
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ...... 384
17
A.C. TIMING CHARACTERISTICS ....................................................... 388
18
ORDERING AND THERMAL INFORMATION ...................................... 405
19
MECHANICAL INFORMATION............................................................. 406
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