Электронный компонент: PM8315-PI

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TITLE PAGE
CONTENTS
LIST OF FIGURES
LIST OF TABLES
FEATURES
APPLICATIONS
REFERENCES
APPLICATION EXAMPLES
BLOCK DIAGRAM
- Top Level Block Diagram
- M13 Multiplexer Mode Block Diagram
- VT/TU Mapper Only Mode Block Diagram
- DS3 Framer Only Block Diagram
DESCRIPTION
PIN DIAGRAM
PIN DESCRIPTION
- T1 Framer (T1-FRMR)
- E1 Framer (E1-FRMR)
- Performance Monitor Counters (T1/E1-PMON)
- Bit Oriented Code Detector (RBOC)
- HDLC Receiver (RDLC)
- T1 Alarm Integrator (ALMI)
- Elastic Store (ELST)
- Signaling Elastic Stores (RX-SIG-ELST and TX_SIG-ELST)
- Signaling Extractor (SIGX)
- Receive Per-Channel Serial Controller (RPSC)
- Basic Transmitter (XBAS)
- E1 Transmitter (E1TRAN)
- Transmit Per-Channel Serial Controller (TPSC)
- Signaling Aligner (SIGA)
- Bit Oriented Code Generator (XBOC)
- HDLC Transmitters (TDPR)
- T1 Automatic Performance Report Generation (APRM)
- Receive and Transmit Digital Jitter Attenuator (RJAT, TJAT)
- Timing Options (TOPS)
- Pseudo Random Binary Sequence Generation and Detection (PRBS)
- Pseudo Random Pattern Generation and Detection (PRGD)
- DS3 Framer (DS3-FRMR)
- Performance Monitor Accumulator (DS3-PMON)
- DS3 Transmitter (DS3-TRAN)
- M23 Multiplexer (MX23)
- DS2 Framer (DS2-FRMR)
- M12 Multiplexer (MX12)
- Tributary Payload Processor (VTPP)
- Receive Tributary Path Overhead Processor (RTOP)
- Receive Tributary Demapper (RTDM)
- Parallel In to Serial Out Converter (PISO)
- DS3 Mapper Drop Side (D3MD)
- Transmit Tributary Path Overhead Processor (TTOP)
- Transmit Remote Alarm Processor (TRAP)
- Transmit Tributary Mapper (TTMP)
- Serial In to Parallel Out Converter (SIPO)
- DS3 Mapper ADD Side (D3MA)
- Egress System Interface (ESIF)
- Ingress System Interface (ISIF)
- Extract Scaleable Bandwidth Interconnect (EXSBI)
- Insert Scaleable Bandwidth Interconnect (INSBI)
- Scaleable Bandwidth Interconnect PISO (SBIPISO)
- Scaleable Bandwidth Interconnect SIPO (SBISIPO)
- JTAG Test Access Port
- Microprocessor Interface
NORMAL MODE REGISTER DESCRIPTION
TEST FEATURES DESCRIPTION
- JTAG Test Port
OPERATION
- DS3 Frame Format
- Servicing Interrupts
- Using the Performance Monitoring Features
- Using the Internal FDL Transmitter
- Using the Internal Data Link Receiver
- T1 Automatic Performance Report Format
- Using the Per-Channel Serial Controllers
- T1/E1 Framer Loopback Modes
- DS3 Loopback Modes
- Telecom Bus Mapper/Demapper Loopback Modes
- SBI Bus Data Formats
- H-MVIP Data Format
- Serial Clock and Data Format
- PRGD Pattern Generation
- JTAG Support
FUNCTIONAL TIMING
- DS3 Line Side Interface Timing
- DS3 System Side Interface Timing
- Telecom DROP Bus Interface Timing
- Telecom ADD Bus Interface Timing
- SONET/SDH Serial Alarm Port Timing
- SBI DROP Bus Interface Timing
- SBI ADD Bus Interface Timing
- Egress H-MVIP Link Timing
- Ingress H-MVIP Link Timing
- Egress Serial Clock and Data Interface Timing
- Ingress Serial Clock and Data Interface Timing
ABSOLUTE MAXIMUM RATINGS
D.C. CHARACTERISTICS
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS
TEMUX TIMING CHARACTERISTICS
ORDERING AND THERMAL INFORMATION
MECHANICAL INFORMATION

STANDARD PRODUCT

PM8315 TEMUX

DATASHEET

PMC-1981125

ISSUE 7

HIGH DENSITY T1/E1 FRAMER WITH

INTEGRATED VT/TU MAPPER AND M13 MUX

PMC-Sierra, Inc.

105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

PM8315

TEMUX

HIGH DENSITY T1/E1 FRAMER WITH

INTEGRATED VT/TU MAPPER AND M13

MULTIPLEXER

DATASHEET

PROPRIETARY AND CONFIDENTIAL

ISSUE 7: MAY 2001

STANDARD PRODUCT

PM8315 TEMUX

DATASHEET

PMC-1981125

ISSUE 7

HIGH DENSITY T1/E1 FRAMER WITH

INTEGRATED VT/TU MAPPER AND M13 MUX

PROPRIETARY AND CONFIDENTIAL

CONTENTS

FEATURES .............................................................................................. 1

APPLICATIONS ..................................................................................... 15

REFERENCES....................................................................................... 16

APPLICATION EXAMPLES ................................................................... 20

BLOCK DIAGRAM ................................................................................. 21

5.1

TOP LEVEL BLOCK DIAGRAM .................................................. 21

5.2

M13 MULTIPLEXER MODE BLOCK DIAGRAM ......................... 23

5.3

VT/TU MAPPER ONLY MODE BLOCK DIAGRAM..................... 23

5.4

DS3 FRAMER ONLY BLOCK DIAGRAM .................................... 24

DESCRIPTION ...................................................................................... 26

PIN DIAGRAM ....................................................................................... 31

PIN DESCRIPTION................................................................................ 32

FUNCTIONAL DESCRIPTION............................................................... 70

9.1

T1 FRAMER (T1-FRMR)............................................................. 70

9.2

E1 FRAMER (E1-FRMR)............................................................. 70

1.3

PERFORMANCE MONITOR COUNTERS (T1/E1-PMON)......... 77

1.4

BIT ORIENTED CODE DETECTOR (RBOC).............................. 78

1.5

HDLC RECEIVER (RDLC) .......................................................... 78

1.6

T1 ALARM INTEGRATOR (ALMI)............................................... 79

1.7

ELASTIC STORE (ELST)............................................................ 80

1.8

SIGNALING ELASTIC STORES (RX-SIG-ELST AND
TX_SIG-ELST) ............................................................................ 80

STANDARD PRODUCT

PM8315 TEMUX

DATASHEET

PMC-1981125

ISSUE 7

HIGH DENSITY T1/E1 FRAMER WITH

INTEGRATED VT/TU MAPPER AND M13 MUX

PROPRIETARY AND CONFIDENTIAL

1.9

SIGNALING EXTRACTOR (SIGX).............................................. 81

1.10 RECEIVE PER-CHANNEL SERIAL CONTROLLER (RPSC)...... 82

1.11 BASIC TRANSMITTER (XBAS) .................................................. 82

1.12 E1 TRANSMITTER (E1-TRAN)................................................... 83

1.13 TRANSMIT PER-CHANNEL SERIAL CONTROLLER (TPSC).... 83

1.14 SIGNALING ALIGNER (SIGA) .................................................... 83

1.15 BIT ORIENTED CODE GENERATOR (XBOC) ........................... 84

1.16 HDLC TRANSMITTERS (TDPR)................................................. 84

1.17 T1 AUTOMATIC PERFORMANCE REPORT GENERATION

(APRM)........................................................................................ 85

1.18 RECEIVE AND TRANSMIT DIGITAL JITTER ATTENUATOR

(RJAT, TJAT) ............................................................................... 86

1.19 TIMING OPTIONS (TOPS) ......................................................... 92

1.20 PSEUDO RANDOM BINARY SEQUENCE GENERATION

AND DETECTION (PRBS).......................................................... 93

1.21 PSEUDO RANDOM PATTERN GENERATION AND

DETECTION (PRGD).................................................................. 93

1.22 DS3 FRAMER (DS3-FRMR) ....................................................... 93

1.23 PERFORMANCE MONITOR ACCUMULATOR (DS3-PMON) .... 96

1.24 DS3 TRANSMITTER (DS3-TRAN).............................................. 96

1.25 M23 MULTIPLEXER (MX23) ....................................................... 97

1.26 DS2 FRAMER (DS2-FRMR) ....................................................... 98

1.27 M12 MULTIPLEXER (MX12) ..................................................... 100

1.28 TRIBUTARY PAYLOAD PROCESSOR (VTPP) ........................ 101

1.29 RECEIVE TRIBUTARY PATH OVERHEAD PROCESSOR

(RTOP) ...................................................................................... 104

STANDARD PRODUCT

PM8315 TEMUX

DATASHEET

PMC-1981125

ISSUE 7

HIGH DENSITY T1/E1 FRAMER WITH

INTEGRATED VT/TU MAPPER AND M13 MUX

PROPRIETARY AND CONFIDENTIAL

iii

1.30 RECEIVE TRIBUTARY DEMAPPER (RTDM) ........................... 106

1.31 PARALLEL IN TO SERIAL OUT CONVERTER (PISO)............. 108

1.32 DS3 MAPPER DROP SIDE (D3MD) ..........................................110

1.33 TRANSMIT TRIBUTARY PATH OVERHEAD PROCESSOR

(TTOP) .......................................................................................113

1.34 TRANSMIT REMOTE ALARM PROCESSOR (TRAP)...............114

1.35 TRANSMIT TRIBUTARY MAPPER (TTMP)...............................115

1.36 SERIAL IN TO PARALLEL OUT CONVERTER (SIPO)..............116

1.37 DS3 MAPPER ADD SIDE (D3MA) .............................................116

1.38 EGRESS SYSTEM INTERFACE (ESIF) ....................................118

1.39 INGRESS SYSTEM INTERFACE (ISIF) ................................... 124

1.40 EXTRACT SCALEABLE BANDWIDTH INTERCONNECT

(EXSBI) ..................................................................................... 129

1.41 INSERT SCALEABLE BANDWIDTH INTERCONNECT

(INSBI)....................................................................................... 130

1.42 SCALEABLE BANDWIDTH INTERCONNECT PISO

(SBIPISO).................................................................................. 130

1.43 SCALEABLE BANDWIDTH INTERCONNECT SIPO

(SBISIPO).................................................................................. 131

1.44 JTAG TEST ACCESS PORT..................................................... 131

1.45 MICROPROCESSOR INTERFACE .......................................... 131

NORMAL MODE REGISTER DESCRIPTION ..................................... 162

TEST FEATURES DESCRIPTION ...................................................... 163

11.1 JTAG TEST PORT .................................................................... 172

OPERATION ........................................................................................ 185

12.1 DS3 FRAME FORMAT.............................................................. 185

STANDARD PRODUCT

PM8315 TEMUX

DATASHEET

PMC-1981125

ISSUE 7

HIGH DENSITY T1/E1 FRAMER WITH

INTEGRATED VT/TU MAPPER AND M13 MUX

PROPRIETARY AND CONFIDENTIAL

12.2 SERVICING INTERRUPTS....................................................... 187

12.3 USING THE PERFORMANCE MONITORING FEATURES ...... 187

12.4 USING THE INTERNAL FDL TRANSMITTER .......................... 192

12.5 USING THE INTERNAL DATA LINK RECEIVER ...................... 196

12.6 T1 AUTOMATIC PERFORMANCE REPORT FORMAT ............ 200

12.7 USING THE PER-CHANNEL SERIAL CONTROLLERS........... 202

12.8 T1/E1 FRAMER LOOPBACK MODES...................................... 204

12.9 DS3 LOOPBACK MODES ........................................................ 207

12.10 TELECOM BUS MAPPER/DEMAPPER LOOPBACK MODES. 210

12.11 SBI BUS DATA FORMATS .........................................................211

12.12 H-MVIP DATA FORMAT ............................................................ 230

12.13 SERIAL CLOCK AND DATA FORMAT ...................................... 236

12.14 PRGD PATTERN GENERATION .............................................. 237

12.15 JTAG SUPPORT ....................................................................... 241

FUNCTIONAL TIMING......................................................................... 249

13.1 DS3 LINE SIDE INTERFACE TIMING ...................................... 249

13.2 DS3 SYSTEM SIDE INTERFACE TIMING................................ 251

13.3 TELECOM DROP BUS INTERFACE TIMING........................... 253

13.4 TELECOM ADD BUS INTERFACE TIMING.............................. 256

13.5 SONET/SDH SERIAL ALARM PORT TIMING .......................... 257

13.6 SBI DROP BUS INTERFACE TIMING ...................................... 259

13.7 SBI ADD BUS INTERFACE TIMING ......................................... 260

13.8 EGRESS H-MVIP LINK TIMING ............................................... 260

13.9 INGRESS H-MVIP LINK TIMING .............................................. 261