Document Outline

• TITLE PAGE
• Legal Information
  • Copyright
  • Disclaimer
  • Trademarks
  • Contacting PMC-Sierra
• Revision History
• Document Conventions
  • � All signal, pin, and bus names described in the text, such as ExtRqst*, are in boldface typeface.
  • � All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold ty...
  • � All instruction names, such as MFHI, are in san serif typeface.
• Table of Contents
  • 1 Features 9
  • 2 Block Diagram 10
  • 3 Hardware Overview 11
    • 3.1 Superscalar Dispatch 11
    • 3.2 CPU Registers 11
    • 3.3 Integer Unit 11
    • 3.4 Pipeline 12
    • 3.5 Register File 12
    • 3.6 ALU 12
    • 3.7 Integer Multiply/Divide 13
    • 3.8 Floating-Point Co-Processor 13
    • 3.9 Floating-Point Unit 13
    • 3.10 Floating-Point General Register File 15
    • 3.11 System Control Co-processor (CP0) 15
    • 3.12 System Control Co-Processor Registers 15
    • 3.13 Virtual to Physical Address Mapping 16
    • 3.14 Joint TLB 17
    • 3.15 Instruction TLB 18
    • 3.16 Data TLB 18
    • 3.17 Cache Memory 18
    • 3.18 Instruction Cache 19
    • 3.19 Data Cache 19
    • 3.20 Write buffer 21
    • 3.21 System Interface 21
    • 3.22 System Address/Data Bus 21
    • 3.23 System Command Bus 21
    • 3.24 Handshake Signals 22
    • 3.25 Non-overlapping System Interface 22
    • 3.26 Enhanced Write Modes 23
    • 3.27 External Requests 24
    • 3.28 Interrupt Handling 24
    • 3.29 Standby Mode 24
    • 3.30 JTAG Interface 24
    • 3.31 Boot-Time Options 24
    • 3.32 Boot-Time Modes 25
  • 4 Pin Descriptions 26
  • 5 Absolute Maximum Ratings 29
  • 6 Recommended Operating conditions 30
  • 7 DC Electrical Characteristics 31
  • 8 Power Consumption 32
  • 9 AC Electrical Characteristics 33
    • 9.1 Capacitive Load Deration 33
    • 9.2 Clock Parameters 33
    • 9.3 System Interface Parameters 34
    • 9.4 Boot-Time Interface Parameters 34
  • 10 Timing Diagrams 35
    • 10.1 System Interface Timing 35
  • 11 Packaging Information 36
  • 12 RM5261 208-pin PQFP Package Pinout 38
  • 13 Ordering Information 40
• List of Figures
  • Figure 1 Block Diagram 10
  • Figure 2 CPU Registers 11
  • Figure 3 Pipeline 12
  • Figure 4 CP0 Registers 16
  • Figure 5 Kernel Mode Virtual Addressing (32-bit) 17
  • Figure 6 Typical Embedded System Block Diagram 21
  • Figure 7 Processor Block Read 23
  • Figure 8 Processor Block Write 23
  • Figure 9 Clock Timing 35
  • Figure 10 Input Timing 35
  • Figure 11 Output Timing 35
• List of Tables
  • Table 1 Integer Multiply/Divide Operations 13
  • Table 2 Floating-Point Instruction Cycles 14
  • Table 3 Cache Attributes 20
  • Table 4 Boot-Time Mode Bit Stream 25
  • Table 5 System Interface 26
  • Table 6 Clock/Control Interface 27
  • Table 7 Interrupt Interface 27
  • Table 8 JTAG Interface 27
  • Table 9 Initialization Interface 28
  • Table 10 Power Supply 28
  • Table 11 DC Electrical Characteristics 31
• 1 Features
• 2 Block Diagram
  • Figure 1 Block Diagram
• 3 Hardware Overview
  • 3.1 Superscalar Dispatch
  • 3.2 CPU Registers
    • Figure 2 CPU Registers
      • 63
      • 0
      • 0
      • 63
      • 0
      • r1
      • HI
      • r2
      • 63
      • 0
      • �
      • LO
      • �
      • �
      • �
      • 63
      • 0
      • r29
      • PC
      • r30
      • r31
  • 3.3 Integer Unit
  • 3.4 Pipeline
    • Figure 3 Pipeline
  • 3.5 Register File
  • 3.6 ALU
  • 3.7 Integer Multiply/Divide
    • Table 1 Integer Multiply/Divide Operations
      • MULT/U, MAD/U
      • 16 bit
      • 3
      • 2
      • 0
      • 32 bit
      • 4
      • 3
      • 0
      • MUL
      • 16 bit
      • 3
      • 2
      • 1
      • 32 bit
      • 4
      • 3
      • 2
      • DMULT, DMULTU
      • any
      • 7
      • 6
      • 0
      • DIV, DIVD
      • any
      • 36
      • 36
      • 0
      • DDIV, DDIVU
      • any
      • 68
      • 68
      • 0
  • 3.8 Floating-Point Co-Processor
  • 3.9 Floating-Point Unit
    • Table 2 Floating-Point Instruction Cycles
      • fadd
      • 4
      • 1
      • fsub
      • 4
      • 1
      • fmult
      • 4/5
      • 1/2
      • fmadd
      • 4/5
      • 1/2
      • fmsub
      • 4/5
      • 1/2
      • fdiv
      • 21/36
      • 19/34
      • fsqrt
      • 21/36
      • 19/34
      • frecip
      • 21/36
      • 19/34
      • frsqrt
      • 38/68
      • 36/66
      • fcvt.s.d
      • 4
      • 1
      • fcvt.s.w
      • 6
      • 3
      • fcvt.s.l
      • 6
      • 3
      • fcvt.d.s
      • 4
      • 1
      • fcvt.d.w
      • 4
      • 1
      • fcvt.d.l
      • 4
      • 1
      • fcvt.w.s
      • 4
      • 1
      • fcvt.w.d
      • 4
      • 1
      • fcvt.l.s
      • 4
      • 1
      • fcvt.l.d
      • 4
      • 1
      • fcmp
      • 1
      • 1
      • fmov
      • 1
      • 1
      • fmovc
      • 1
      • 1
      • fabs
      • 1
      • 1
      • fneg
      • 1
      • 1
    • Note: Numbers are represented as single/double precision format.
  • 3.10 Floating-Point General Register File
  • 3.11 System Control Co-processor (CP0)
  • 3.12 System Control Co-Processor Registers
    • Figure 4 CP0 Registers
  • 3.13 Virtual to Physical Address Mapping
    • � user mode
    • � kernel mode
    • � supervisor mode
    • Figure 5 Kernel Mode Virtual Addressing (32-bit)
      • 0xFFFFFFFF
      • Kernel virtual address space
      • (kseg3)
      • Mapped, 0.5GB
        • 0xE0000000
        • 0xDFFFFFFF
      • Supervisor virtual address space
      • (ksseg)
      • Mapped, 0.5GB
        • 0xC0000000
        • 0xBFFFFFFF
      • Uncached kernel physical address space
      • (kseg1)
      • Unmapped, 0.5GB
        • 0xA0000000
        • 0x9FFFFFFF
      • Cached kernel physical address space
      • (kseg0)
      • Unmapped, 0.5GB
        • 0x80000000
        • 0x7FFFFFFF
      • User virtual address space
      • (kuseg)
      • Mapped, 2.0GB
        • 0x00000000
  • 3.14 Joint TLB
  • 3.15 Instruction TLB
  • 3.16 Data TLB
  • 3.17 Cache Memory
  • 3.18 Instruction Cache
  • 3.19 Data Cache
    • 1. Uncached
    • 2. Write-back
    • 3. Write-through with write allocate
    • 4. Write-through without write allocate
    • Table 3 Cache Attributes
      • Size
      • 32KB
      • 32KB
      • Organization
      • 2-way set associative
      • 2-way set associative
      • Line size
      • 32B
      • 32B
      • Index
      • vAddr11..0
      • vAddr11..0
      • Tag
      • pAddr31..12
      • pAddr31..12
      • Write policy
      • n.a.
      • write-back/write-through
      • Read order
      • sub-block
      • sub-block
      • sequential
      • sequential
      • miss restart after transfer of
      • entire line
      • first double
      • Parity
      • per-word
      • per-byte
      • Cache locking
      • set A
      • set A
  • 3.20 Write buffer
  • 3.21 System Interface
    • Figure 6 Typical Embedded System Block Diagram
  • 3.22 System Address/Data Bus
  • 3.23 System Command Bus
  • 3.24 Handshake Signals
  • 3.25 Non-overlapping System Interface
    • Figure 7 Processor Block Read
    • Figure 8 Processor Block Write
  • 3.26 Enhanced Write Modes
  • 3.27 External Requests
  • 3.28 Interrupt Handling
  • 3.29 Standby Mode
  • 3.30 JTAG Interface
  • 3.31 Boot-Time Options
  • 3.32 Boot-Time Modes
    • Table 4 Boot-Time Mode Bit Stream
      • 0
      • reserved (must be zero)
      • 14:13
      • Output driver strength - 100% = fastest
        • 00: 67% strength
        • 01: 50% strength
        • 10: 100% strength
        • 11: 83% strength
      • 4:1
      • Write-back data rate
        • 0: DDDD
        • 1: DDxDDx
        • 2: DDxxDDxx
        • 3: DxDxDxDx
        • 4: DDxxxDDxxx
        • 5: DDxxxxDDxxxx
        • 6: DxxDxxDxxDxx
        • 7: DDxxxxxxDDxxxxxx
        • 8: DxxxDxxxDxxxDxxx
        • 9-15 reserved
      • 15
      • Reserved: Must be zero
      • 7:5
      • Pclock to SysClock Multiplier
        • Mode Bits 7:5 Mode Bit 20=0 Mode Bit 20=1
        • 000 Multiply by 2 n/a
        • 001 Multiply by 3 n/a
        • 010 Multiply by 4 n/a
        • 011 Multiply by 5 Multiply by 2.5
        • 100 Multiply by 6 n/a
        • 101 Multiply by 7 Multiply by 3.5
        • 110 Multiply by 8 n/a
        • 111 Multiply by 9 Multiply by 4.5
      • 17:16
      • System configuration identifiers - software visible in Config[21..20] register
      • 8
      • Specifies byte ordering. Logically ORed with BigEndian input signal.
        • 0: Little endian
        • 1: Big endian
      • 19:18
      • Reserved: Must be zero
      • 10:9
      • Non-Block Write Protocol
        • 00: R4000 compatible
        • 01: reserved
        • 10: pipelined
        • 11: write re-issue
      • 20
      • Select Pclock to SysClock Multiply Mode
        • 0: Integer Multipliers
        • 1: Half-Integer Multipliers
      • 11
      • Timer Interrupt Enable/Disable
        • 0: Enable the timer interrupt on Int5*
        • 1: Disable the timer interrupt on Int5*
      • 21
      • External Bus Width
        • 0: 64-bit
        • 1: 32-bit
      • 12
      • Reserved: Must be zero
      • 255:22
      • Reserved: Must be zero
• 4 Pin Descriptions
  • Table 5 System Interface
    • ExtRqst*
    • Input
    • External Request
    • Signals that the system interface is submitting an external request.
    • Release*
    • Output
    • Release interface
    • Signals that the processor is releasing the system interface to slave state.
    • RdRdy*
    • Input
    • Read Ready
    • Signals that an external agent can now accept a processor read.
    • WrRdy*
    • Input
    • Write Ready
    • Signals that an external agent can now accept a processor write request.
    • ValidIn*
    • Input
    • Valid Input
    • Signals that an external agent is now driving a valid address or data on the SysAD bus and a vali...
    • ValidOut*
    • Output
    • Valid Output
    • Signals that the processor is now driving a valid address or data on the SysAD bus and a valid co...
    • SysAD[63:0]
    • Input/Output
    • System Address/Data bus
    • A 64-bit address and data bus for communication between the processor and an external agent.
    • SysADC[7:0]
    • Input/Output
    • System Address/Data check bus
    • An 8-bit bus containing parity check bits for the SysAD bus during data cycles.
    • SysCmd[8:0]
    • Input/Output
    • System Command/Data identifier bus
    • A 9-bit bus for command and data identifier transmission between the processor and an external ag...
    • SysCmdP
    • Input/Output
    • Reserved for system command/data identifier bus parity
    • For the RM5261, unused on input and zero on output.
  • Table 6 Clock/Control Interface
    • SysClock
    • Input
    • System Clock
    • Master clock input used as the system interface reference clock. All output timings are relative ...
    • VccP
    • Input
    • Quiet Vcc for PLL
    • Quiet Vcc for the internal phase locked loop. Must be connected to VccInt through a filter circuit.
    • VssP
    • Input
    • Quiet Vss for PLL
    • Quiet Vss for the internal phase locked loop. Must be connected to Vss through a filter circuit.
  • Table 7 Interrupt Interface
    • Int[5:0]*
    • Input
    • Interrupt
    • Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
    • NMI*
    • Input
    • Non-maskable interrupt
    • Non-maskable interrupt, ORed with bit 6 of the interrupt register.
  • Table 8 JTAG Interface
    • JTDI
    • Input
    • JTAG data in
    • JTAG serial data in.
    • JTCK
    • Input
    • JTAG clock input
    • JTAG serial clock input.
    • JTDO
    • Output
    • JTAG data out
    • JTAG serial data out.
    • JTMS
    • Input
    • JTAG command
    • JTAG command signal, signals that the incoming serial data is command data.
  • Table 9 Initialization Interface
    • BigEndian
    • Input
    • Allows the system to change the processor addressing mode without rewriting the mode ROM.
    • VccOK
    • Input
    • Vcc is OK
    • When asserted, this signal indicates to the RM5261 that the 3.3V power supply has been above 3.0V...
    • ColdReset*
    • Input
    • Cold reset
    • This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted ...
    • Reset*
    • Input
    • Reset
    • This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchro...
    • ModeClock
    • Output
    • Boot mode clock
    • Serial boot-mode data clock output at the system clock frequency divided by 256.
    • ModeIn
    • Input
    • Boot mode data in
    • Serial boot-mode data input.
  • Table 10 Power Supply
    • VccInt
    • Input
    • Power supply for core.
    • VccIO
    • Input
    • Power supply for I/O.
    • Vss
    • Input
    • Ground return.
    • 1. An "*" at the end of the signal denotes active low.
• 5 Absolute Maximum Ratings1
  • VTERM
    • Terminal Voltage with respect to Vss
  • �0.52 to +3.9
  • V
  • TCASE
    • Operating Temperature
    • Commercial
  • 0 to +85
  • �C
    • Industrial
  • �45 to +85
  • �C
  • TSTG
    • Storage Temperature
  • �55 to +125
  • �C
  • IIN
    • DC Input Current
  • �203
  • mA
  • IOUT
    • DC Output Current
  • �204
  • mA
    • 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage t...
    • 2. VIN minimum = -2.0 V for pulse width less than 15 ns. VIN should not exceed 3.9 Volts.
    • 3. When VIN < 0V or VIN > VccIO
    • 4. Not more than one output should be shorted at a time. Duration of the short should not exceed ...
• 6 Recommended Operating conditions
  • Commercial
  • 0�C to +85�C (Case)
  • 0 V
  • 2.5 V � 5%
  • 3.15 V to 3.45 V
  • 2.5 V � 5%
  • Industrial
  • -40�C to +85�C (Case)
  • 0 V
  • 2.5 V � 5%
  • 3.15 V to 3.45 V
  • 2.5 V � 5%
  • 1. VccIO should not exceed VccInt by greater than 1.2V during the power-up sequence.
  • 2. Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended.
  • 3. As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid enter...
  • 4. VccP must be connected to VccInt through a passive filter circuit. See the RM5200 User�s Manua...
• 7 DC Electrical Characteristics
  • Table 11 DC Electrical Characteristics
  • VOL
  • 0.2V
    • |IOUT|= 100 mA
  • VOH
  • VccIO - 0.2V
  • VOL
  • 0.4V
    • |IOUT| = 2 mA
  • VOH
  • 2.4V
  • VIL
  • -0.3V
  • 0.8V
  • VIH
  • 2.0V
  • VccIO + 0.3V
  • IIN
  • �15 mA
  • �15 mA
    • VIN = 0
    • VIN = VccIO
• 8 Power Consumption
  • VccInt Power (mWatts)
  • standby
  • No SysAD bus activity
  • 350
  • 435
  • 450
    • active
    • R4000 write protocol with no FPU operation
  • 1600
  • 3200
  • 1850
  • 3700
  • 1900
  • 3800
    • Write re-issue or pipelined writes with superscalar
  • 1750
  • 3500
  • 2025
  • 4050
  • 2075
  • 4150
    • 1. Typical integer instruction mix with nominal supply voltage (untested).
    • 2. Worst case instruction mix with maximum supply voltage.
    • 3. I/O supply power is application dependent, but typically <20% of VccInt.
• 9 AC Electrical Characteristics
  • 9.1 Capacitive Load Deration
    • Load Derate
    • CLD
    • 2
    • ns/25pF
    • IO Power Derate
    • 21
    • mW/25pF/MHz
    • IO Power Derate @ 20pF load
    • 4.0
    • 5.5
    • mW/MHz
  • 9.2 Clock Parameters
    • SysClock High
    • tSCH
      • Transition � 5ns
    • 3
    • 3
    • 3
    • ns
      • SysClock Low
    • tSCL
      • Transition � 5ns
    • 3
    • 3
    • 3
    • ns
      • SysClock Frequency1
    • 25
    • 100
    • 25
    • 125
    • 33.3
    • 106
    • MHz
      • SysClock Period
    • tSCP
    • 40
    • 40
    • 30
    • ns
      • Clock Jitter for SysClock
    • tJI
    • �200
    • �150
    • �150
    • ps
      • SysClock Rise Time
    • tCR
    • 2
    • 2
    • 2
    • ns
      • SysClock Fall Time
    • tCF
    • 2
    • 2
    • 2
    • ns
      • ModeClock Period
    • tModeCKP
    • 256
    • 256
    • 256
    • tSCP
      • JTAG Clock Period
    • tJTAGCKP
    • 4
    • 4
    • 4
    • tSCP
      • 1. Operation of the RM5261 is only guaranteed with the Phase Lock Loop Enabled.
  • 9.3 System Interface Parameters1
    • Data Output2,3
    • tDO
      • mode14:13 = 105 (fastest)
    • 1.0
    • 4.5
    • ns
      • mode14:13 = 115
    • 1.0
    • 5.0
    • ns
      • mode14:13 = 005
    • 1.0
    • 5.5
    • ns
      • mode14:13 = 015 (slowest)
    • 1.0
    • 6.0
    • ns
      • Data Setup4
    • tDS
      • trise = see above table
      • tfall = see above table
    • 2.5
    • ns
      • Data Hold4
    • tDH
    • 1.0
    • ns
      • 1. Timings are measured from 1.5 V of the clock to 1.5 V of the signal.
      • 2. Capacitive load for all maximum output timings is 50 pF. Minimum output timings are for a theo...
      • 3. Data Output timing applies to all signal pins whether tristate I/O or output only.
      • 4. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
      • 5. Only mode 14:13 = 00 is tested and guaranteed.
  • 9.4 Boot-Time Interface Parameters
    • Mode Data Setup
    • tDS(M)
    • 4
    • SysClock cycles
    • Mode Data Hold
    • tDH(M)
    • 0
    • SysClock cycles
• 10 Timing Diagrams
  • Figure 9 Clock Timing
  • 10.1 System Interface Timing
    • Figure 10 Input Timing
    • Figure 11 Output Timing
• 11 Packaging Information
  • A
  • --
  • 3.70
  • 4.07
  • A1
  • 0.25
  • 0.33
  • --
  • A2
  • 3.20
  • 3.37
  • 3.60
  • D
  • 30.60 BSC
  • To be determined at seating Plane C.
  • D1
  • 28.00 BSC
  • Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 MM per si...
  • D2
  • 25.00 REF.
  • E
  • 30.60 BSC
  • To be determined at seating Plane C.
  • E1
  • 28.00 BSC
  • Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 MM per si...
  • E2
  • 25.00 REF.
  • D3
  • 21.0 REF.
  • E3
  • 21.0 REF.
  • L
  • 0.46
  • 0.56
  • 0.66
  • e
  • 0.50 BSC
  • b
  • 0.17
  • 0.22
  • 0.27
  • b1
  • 0.17
  • 0.20
  • 0.23
  • aaa
  • 0.08
  • ThetaJa
  • 13.7� C/W
  • ThetaJc
  • 1.5� C/W
  • 1. All dimensioning and tolerances confirm to ASME Y14.5�1994.
  • 2. Datum Plane H located at the bottom of the mold parting line and coincident with where lead ex...
  • 3. Datums A�B and D to be determined where center line between leads exits plastic body at Datum ...
  • 4. To be determined at seating Plane C.
  • 5. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 MM per...
  • 6. �N� is number of terminals.
  • 7. Package top dimensions are smaller than bottom dimensions by 0.20 millimeters and top of packa...
  • 8. Dimensions b does not include Damabr protrusion. Allowable Damabr protrusion shall be 0.08 MM....
  • 9. All dimensions are in millimeters.
  • 10. The optional exposed heat shrink is coincident with the top or bottom side of the package and...
  • 11. These dimensions apply to the flat section of the lead between 0.10 MM and 0.25 MM from the l...
  • 12. This drawing conforms to JEDEC registered outline MS-029. But the heat slug dimension was not...
  • 13. A1 is defined as the distance from the seating plane to the lowest point of the package body.
• 12 RM5261 208-pin PQFP Package Pinout
  • 1
  • VccIO
  • 2
  • NC
  • 3
  • NC
  • 4
  • VccIO
  • 5
  • Vss
  • 6
  • SysAD4
  • 7
  • SysAD36
  • 8
  • SysAD5
  • 9
  • SysAD37
  • 10
  • VccInt
  • 11
  • Vss
  • 12
  • SysAD6
  • 13
  • SysAD38
  • 14
  • VccIO
  • 15
  • Vss
  • 16
  • SysAD7
  • 17
  • SysAD39
  • 18
  • SysAD8
  • 19
  • SysAD40
  • 20
  • VccInt
  • 21
  • Vss
  • 22
  • SysAD9
  • 23
  • SysAD41
  • 24
  • VccIO
  • 25
  • Vss
  • 26
  • SysAD10
  • 27
  • SysAD42
  • 28
  • SysAD11
  • 29
  • SysAD43
  • 30
  • VccInt
  • 31
  • Vss
  • 32
  • SysAD12
  • 33
  • SysAD44
  • 34
  • VccIO
  • 35
  • Vss
  • 36
  • SysAD13
  • 37
  • SysAD45
  • 38
  • SysAD14
  • 39
  • SysAD46
  • 40
  • VccInt
  • 41
  • Vss
  • 42
  • SysAD15
  • 43
  • SysAD47
  • 44
  • VccIO
  • 45
  • Vss
  • 46
  • ModeClock
  • 47
  • JTDO
  • 48
  • JTDI
  • 49
  • JTCK
  • 50
  • JTMS
  • 51
  • VccIO
  • 52
  • Vss
  • 53
  • NC
  • 54
  • NC
  • 55
  • NC
  • 56
  • VccIO
  • 57
  • Vss
  • 58
  • ModeIn
  • 59
  • RdRdy*
  • 60
  • WrRdy*
  • 61
  • ValidIn*
  • 62
  • ValidOut*
  • 63
  • Release*
  • 64
  • VccP
  • 65
  • VssP
  • 66
  • SysClock
  • 67
  • VccInt
  • 68
  • Vss
  • 69
  • VccIO
  • 70
  • Vss
  • 71
  • VccInt
  • 72
  • Vss
  • 73
  • SysCmd0
  • 74
  • SysCmd1
  • 75
  • SysCmd2
  • 76
  • SysCmd3
  • 77
  • VccIO
  • 78
  • Vss
  • 79
  • SysCmd4
  • 80
  • SysCmd5
  • 81
  • VccIO
  • 82
  • Vss
  • 83
  • SysCmd6
  • 84
  • SysCmd7
  • 85
  • SysCmd8
  • 86
  • SysCmdP
  • 87
  • VccInt
  • 88
  • Vss
  • 89
  • VccInt
  • 90
  • Vss
  • 91
  • VccIO
  • 92
  • Vss
  • 93
  • Int0*
  • 94
  • Int1*
  • 95
  • Int2*
  • 96
  • Int3*
  • 97
  • Int4*
  • 98
  • Int5*
  • 99
  • VccIO
  • 100
  • Vss
  • 101
  • NC
  • 102
  • NC
  • 103
  • NC
  • 104
  • NC
  • 105
  • VccIO
  • 106
  • NMI*
  • 107
  • ExtRqst*
  • 108
  • Reset*
  • 109
  • ColdReset*
  • 110
  • VccOK
  • 111
  • BigEndian
  • 112
  • VccIO
  • 113
  • Vss
  • 114
  • SysAD16
  • 115
  • SysAD48
  • 116
  • VccInt
  • 117
  • Vss
  • 118
  • SysAD17
  • 119
  • SysAD49
  • 120
  • SysAD18
  • 121
  • SysAD50
  • 122
  • VccIO
  • 123
  • Vss
  • 124
  • SysAD19
  • 125
  • SysAD51
  • 126
  • VccInt
  • 127
  • Vss
  • 128
  • SysAD20
  • 129
  • SysAD52
  • 130
  • SysAD21
  • 131
  • SysAD53
  • 132
  • VccIO
  • 133
  • Vss
  • 134
  • SysAD22
  • 135
  • SysAD54
  • 136
  • VccInt
  • 137
  • Vss
  • 138
  • SysAD23
  • 139
  • SysAD55
  • 140
  • SysAD24
  • 141
  • SysAD56
  • 142
  • VccIO
  • 143
  • Vss
  • 144
  • SysAD25
  • 145
  • SysAD57
  • 146
  • VccInt
  • 147
  • Vss
  • 148
  • SysAD26
  • 149
  • SysAD58
  • 150
  • SysAD27
  • 151
  • SysAD59
  • 152
  • VccIO
  • 153
  • Vss
  • 154
  • NC
  • 155
  • NC
  • 156
  • Vss
  • 157
  • NC
  • 158
  • NC
  • 159
  • NC
  • 160
  • NC
  • 161
  • VccIO
  • 162
  • Vss
  • 163
  • SysAD28
  • 164
  • SysAD60
  • 165
  • SysAD29
  • 166
  • SysAD61
  • 167
  • VccInt
  • 168
  • Vss
  • 169
  • SysAD30
  • 170
  • SysAD62
  • 171
  • VccIO
  • 172
  • Vss
  • 173
  • SysAD31
  • 174
  • SysAD63
  • 175
  • SysADC2
  • 176
  • SysADC6
  • 177
  • VccInt
  • 178
  • Vss
  • 179
  • SysADC3
  • 180
  • SysADC7
  • 181
  • VccIO
  • 182
  • Vss
  • 183
  • SysADC0
  • 184
  • SysADC4
  • 185
  • VccInt
  • 186
  • Vss
  • 187
  • SysADC1
  • 188
  • SysADC5
  • 189
  • SysAD0
  • 190
  • SysAD32
  • 191
  • VccIO
  • 192
  • Vss
  • 193
  • SysAD1
  • 194
  • SysAD33
  • 195
  • VccInt
  • 196
  • Vss
  • 197
  • SysAD2
  • 198
  • SysAD34
  • 199
  • SysAD3
  • 200
  • SysAD35
  • 201
  • VccIO
  • 202
  • Vss
  • 203
  • NC
  • 204
  • NC
  • 205
  • NC
  • 206
  • NC
  • 207
  • VccIO
  • 208
  • Vss
• 13 Ordering Information
  • RM5261�200�Q
  • RM5261�250�Q
  • RM5261�266�Q
  • RM5261�200�QI (Contact Sales prior to design)