2FAH-C20R Series - Integrated Passive & Active Device using CSP
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
SOLDER
BUMPS
SILICON
DIE
Electrical Characteristics
Symbol
Minimum
Nominal
Maximum
Unit
(T
A
= 25 C unless otherwise noted)
Zener Diode
Breakdown Voltage @ 1 mA
V
ZT
6
7.2
8 V
Leakage Current @ 3 V
I
R
1 A
ESD Performance (Note 1)
Withstand
Contact Discharge
8
kV
Air Discharge
15
kV
Let Through (Note 2)
Contact Discharge
150 V
Air Discharge
150 V
Channel Specification
Resistance R
90
100
110
Capacitance @ 1 V & 1 MHz
C
8.5
10.5
12.5
pF
Thermal Characteristics
(T
A
= 25 C unless otherwise noted)
Operating Temperature
T
J
-40 25 +85 C
Storage Temperature
T
stg
-60 25 +125 C
Total Power Dissipation @ 70 C
P
D
100 mW
General Information
Electrical & Thermal Characteristics
This application specific integrated passive component is
designed to provide all of the necessary ESD protection
and line resistance required on the data port of a custom
portable electronic device. The ESD protection provided by
the component enables the data port to withstand 8 KV
Contact / 15 KV Air Discharge when tested according to
the method specified in IEC 61000-4-2. The component
incorporates 7 identical channels and is supplied in a 20
pin CSP package which is intended to be mounted
directly onto an FR4 printed circuit board. This package
will meet typical thermal cycle and bend test specifica-
tions without the use of an underfill material.
Note:
1. The IEC 61000-4-2 test method will be adapted for component level testing. The device will provide the specified ESD protection
performance on the "IN 1-7" pins only.
2. "Let Through" is a measure of the component of an incident ESD transient that the protection device allows through to the down
stream circuitry.
Figure 1 CSP Format
Features
New Product Development
Integrated Passive Device
ESD Protection to IEC61000-4-2 Spec.
DIMENSIONS =
MICRONS
(MILS)
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
Mechanical Characteristics
2FAH-C20R Series - Integrated Passive & Active Device using CSP
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
BUMP A1/PIN 1
INDICATOR
BOURNS
LOGO
858 40
(33.78 1.57)
225 20
(8.86 0.79)
45 45
(1.78 1.78)
45 45
(1.78 1.78)
248.5 45
(9.78 1.78)
248.5 45
(9.78 1.78)
348.5 45
(13.72 1.78)
1997 45
(78.62 1.78)
2597 45
(102.24 1.78)
500
(19.69)
300
(11.81)
DIA.
500
(19.69)
This is a Silicon-based device and is packaged using chip scale packaging technology. Solder bumps, formed on the Silicon die,
provide the interconnect medium from die to PCB. The bumps are arranged on the die in a regular grid formation. The grid pitch is
0.5mm. The dimensions for the CSP packaged device are shown in Fig. 2 below.
Reliability data exists and continues to be gathered on an ongoing basis for Bourns Integrated Passive and Active Devices using CSP
packaging.
"Package level" testing of the integrity of the solder joint is carried out on an independent Daisy-Chain test device. A 25-Pin Daisy
Chain component is available from Bourns for this purpose (part number 2TAD-C25R). This is a 5 x 5 array featuring 0.5mm pitch
solder bumps. The Distance to Neutral Point (DNP) on that component is larger than that of the 2FAH-C20R and is thus deemed a
worse case for Thermal Cycle testing.
"Silicon level" reliability performance will be assured by similarity to other Integrated Passive and Active Devices using CSP product
from Bourns.
Fig. 2 Device Mechanical Drawing
Reliability
This section contains the schematic (See Fig. 3 below) for the single channel in the integrated passive device. Note that the electrical
parameters of primary interest are (a) DC Resistance and (b) ESD performance. In terms of DC parameters it should be noted that all
resistor values have a tolerance of 10 %. This schematic consists of a series 100ohm resistance and Back to Back Zener 6.5 Volt
diodes for ESD protection.
Key Design Parameters
DC Channel Resistance: 100 10 %
DC Channel Capacitance: 12.5 pF Maximum
V
BR
: 6 V Min, 8 V Max @ I
BR
= 1 mA.
I
R
: 1 uA Max @ V
R
=3 V.
Individual Channel Schematic
100
6.5V
IN
OUT
Fig. 3 Channel Schematic
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2FAH-C20R Series - Integrated Passive & Active Device using CSP
Block Diagram
100
6.5V
IN1
OUT1
100
6.5V
IN2
OUT2
100
6.5V
IN3
OUT3
100
6.5V
IN4
OUT4
100
6.5V
IN5
OUT5
100
6.5V
IN6
OUT6
100
6.5V
IN7
OUT7
GROUND
GROUND
PIN A1
LOCATION
A
B
C
D
1 2 3 4 5
FAH
Lotcode
Figure 4 contains a block diagram of the CSP device. This diagram includes the pin
names and basic electrical connections associated with each channel.
The device will be laser marked on the
backside according to the following Fig.
5 scheme below. Position A1, on the
Bump Grid is located at the top left of the
die when the die is orientated so that the
mark is read in the normal fashion.
Marking
Please consult Bourns'
Thin Film on
Silicon using CSP
Users Guide
Application Note for notes on PCB
design and SMT processing.
PCB Design and SMT Processing
Fig. 4 Device Block Diagram
Fig. 5 Backside Laser Mark
How to Order
2 FAH - C20R
__
Thinfilm
Model
Chipscale
No. of Solder Bumps
Packaging Option
- R = Tape and Reel
Packaged 3000 pcs. / 7 " reel
COPYRIGHT 2001, BOURNS, INC. LITHO IN U.S.A. IP 5/02 .5M/CS0202
2FAH-C20R REV. F, 8/12/03
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
2FAH-C20R Series - Integrated Passive & Active Device using CSP
The Pin-Out for the device is shown in Fig. 6. Note also that the device is shown with bumps facing up.
Function Pin
Out Function Pin
Out
IN1 B1
OUT4
D3
IN2 A1
OUT5
D4
IN3 A2
OUT6
D5
IN4
A3
OUT7
C5
IN5
A4
Ground
B2
IN6
A5
Ground
B3
IN7
B5
Ground
B4
OUT1
C1
Ground
C2
OUT2
D1
Ground
C3
OUT3
D2
Ground
C4
Device Pin Out
The product will be dispensed in an 8mm x 4mm Tape and Reel format - see Fig. 7 diagram below. The Tape and Reel package will
conform to customer specification.
Packaging
OUT 2
OUT 3
OUT 4
OUT 5
OUT 1
IN 1
IN 2
IN 3
IN 4
IN 5
OUT 6
OUT 7
IN 7
IN 6
GROUND
X 6
1
2
3
4
5
D
C
B
A
2.0 0.05
(.08 .002)
0.3 0.05
(.01 .002)
2.19 0.05
(.09 .002)
2.77 0.05
(.11 .002)
1.75 0.1
(.07 .004)
3.5 0.05
(.14 .002)
8.0 0.3
(.31 .01)
0.9 0.05
(.04 .002)
ORIENTATION
OF COMPONENT
IN POCKET
BACKSIDE FACING UP
0.3
(0.01)
4.0 0.1
(.16 .004)
4.0 0.1
(.16 .004)
0.25
(0.001)
TYP.
R
1.5 0.1/-0
(.06 .004/-0)
DIA.
MAX.
R
Fig. 6 (a) - Device Pin Out "Bumps Up" View
Fig. 6 (b) - Pin Listings
Fig. 7 - Tape and Reel Drawing
DIMENSIONS =
MILLIMETERS
(INCHES)
Reliable Electronic Solutions
Asia-Pacific: TEL +886- (0)2 25624117 FAX +886- (0)2 25624116
Europe: TEL +353 214 515 225 FAX +353 214 515 292
North America: TEL +1-909 781-5492 FAX +1-909 781-5700
www.bourns.com
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