MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12013-A

FLAT-BASE TYPE

INSULATED TYPE

Jan. 2000

8.5

(7.75)

0.3

92.5

2.45

0.3

83.5

0.5

0.3

0.8

71.5

0.5

80.5

0.6

0.5

78.75

1.2

4-R4

LABEL

0.5

2.5

76.5

20.4

50.8

0.8

10.16

0.3

(10.35)

1 CBU+
2 CBU
3 CBV+
4 CBV
5 CBW+
6 CBW
7 GND
8 VDL
9 VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN
21 VN
22 WN
23 Br

31 P
32 B
33 N
34 U
35 V
36 W

Terminals Assignment:

PS12013-A

PACKAGE OUTLINES

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12013-A

FLAT-BASE TYPE

INSULATED TYPE

(Fig. 1)

INTEGRATED FUNCTIONS AND FEATURES

· 3-Phase IGBT inverter bridge configured by the latest 3rd.

generation IGBT and diode technologies.

· Circuit for dynamic braking of motor regenerative energy.

· Inverter output current capability Io (Note 1) :

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:

· For P-Side IGBTs : Drive circuit, High-speed photo-couplers, Short circuit protection (SC),

Bootstrap circuit supply scheme (Single drive power supply ) and Under-voltage protection (UV).

· For N-Side IGBTs : Drive circuit, Short-circuit protection (SC), Control supply Under voltage and Over voltage protection (OV/UV),

System Over temperature protection (OT), Fault output signaling circuit (Fo), and Current-Limit warning signal out-
put (CL).

· For Brake circuit IGBT : Drive circuit.
· Warning and Fault signaling :

: Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.

: N-side control supply abnormality locking (OV/UV)

: System over-temperature protection (OT).

CL : Warning for inverter current overload condition

· For system feedback control : Analogue signal feedback reproducing actual inverter output phase current (3

· Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.

Type Name

PS12013-A

100% load

1.8A (rms)

150% over load

2.7A (rms), 1min

(Note 1) : The inverter output current is assumed to be sinu-

soidal and the peak current value of each of the

above loading cases is defined as : Iop = Io

APPLICATION
Acoustic noise-less 0.4kW/AC400V Class 3 Phase inverter and other motor control applica-
tions.

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12013-A

FLAT-BASE TYPE

INSULATED TYPE

Jan. 2000

CBU

CBU+

CBV

CBV+

CBW

CBW+

GND

VDL VDH

Fo Logic

Application Specific Intelligent

Power Module

CU CV CW

CL,FO

,FO

Protection

Circuit

Photo

Coupler

Input Circuit

Drive Circuit

Input signal conditioning

Current sensing

circuit

Protection

circuit

Control supply

fault sense

Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit may become necessary
depending on the application environment].

AC 400V class
line output

Brake resistor connection,

AC 400V class line input

Inrush prevention circuit,
etc.

T
S

Analogue signal output corresponding to

each phase current (5V line) Note 1)

PWM input

(5V line) Note 2)

Note 1) To prevent chances of signal oscillation, a series resistor (1k

) coupling at each output is recommended.

Note 2) By virtue of integrating a photo-coupler inside the module, direct coupling to CPU, without any extemal opto or transformer isolation is possible.
Note 3) All outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1k

resistance.

Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage.
For extra precaution, a small film snubber capacitor (0.1~0.22

F, high voltage type) is recommended to be mounted close to these P and N DC power input pins.

Fault output

(5V line) Note 3)

INTERNAL FUNCTIONS BLOCK DIAGRAM

(Fig. 2)

Ic(

Icp)

Ic(Icp)

)

900

1000

1200

Applied between P-N

Applied between P-N, Surge-value

Applied between P-U, V, W, Br or U, V, W, Br-N

Supply voltage

Supply voltage (surge)

Each output IGBT collector-emitter static voltage

Condition

Symbol

Item

Ratings

Unit

CC(surge)

or V

MAXIMUM RATINGS

(Tj = 25

INVERTER PART (Including Brake Part)

P(S)

N(S)

Each output IGBT collector-emitter surge voltage

Each output IGBT collector current

Brake IGBT collector current

Brake diode anode current

Applied between P-U, V, W, Br or U, V, W, Br-N

= 25

Note : "( )" means I

peak value

1200

5 (

10)

5 (10)

CIN

Applied between V

-GND

Supply voltage

Symbol

Item

Ratings

Unit

CONTROL PART

Condition

Input signal voltage

Fault output supply voltage

Fault output current

Current-limit warning output voltage

CL output current

Analogue-current-signal output current

0.5 ~ V

+0.5

Applied between U

· V

· W

· U

· V

· B

-GND

Applied between F

· F

-GND

Sink current of F

· F

Applied between CL-GND

Sink current of CL

Sink current of CU · CV · CW

0.5 ~ 7

, V

Supply voltage

Applied between V

-GND, C

BU+

-C

BV+

-C

, C

BW+

-C

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12013-A

FLAT-BASE TYPE

INSULATED TYPE

Jan. 2000

Condition

Symbol

Item

Ratings

Unit

(Note 2)

(Fig. 3)

60 Hz sinusoidal AC for 1 minute, between all terminals
and base plate.

Mounting screw: M3.5

stg

ISO

Junction temperature

Storage temperature

Module case operating temperature

Isolation voltage

Mounting torque

20 ~ +125

40 ~ +125

20 ~ +100

2500

0.78 ~ 1.27

Vrms

N·m

TOTAL SYSTEM

Note 2) : The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation.

However, these power elements can endure instantaneous junction temperature as high as 150

C. To make use of this additional

temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is
to be provided before use.

CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)

C/W

Inverter IGBT (1/6)

Inverter FWDi (1/6)

Brake IGBT

Brake FWDi

Case to fin, thermal grease applied (1 Module)

Junction to case Thermal
Resistance

Contact Thermal Resistance

th(jc

)

th(jc)F

th(jc

)

th(jc)FB

th(c-f)

Condition

Symbol

Item

Ratings

Min.

THERMAL RESISTANCE

Typ.

Max.

3.0

7.3

3.0

7.3

0.040

Unit

(Fig. 3)

150

2.0

4.0

1.4

3.0

150

0.8

2.5

Circuit Current

Input on threshold voltage

Input off threshold voltage

Input pull-up resistor

Min.

3.5

2.0

1.4

4.0

1.6

1.2

0.5

2.2

0.9

0.2

th(on)

th(off)

800V, Input = ON (One-Shot)

Tj = 125

C start

13.5V

= V

16.5V

800V, Tj

125

Ic < I

(CL) operation level, Input = ON,

13.5V

= V

16.5V

FBr

ton

tc(on)

toff

tc(off)

trr

CE(sat)

= 5V, V

= V

= 15V Input = ON,

Tj = 25

C, Ic = 5A

Tj = 25

C, Ic = 5A, Input = OFF

Condition

Symbol

Item

Ratings

Typ.

Max.

Unit

· No destruction

· F

output by protection operation

ELECTRICAL CHARACTERISTICS

(Tj = 25

C, V

= 15V , V

= 15V, V

= 5V unless otherwise noted)

Collector-emitter saturation
voltage

FWDi forward voltage

Brake IGBT
Collector-emitter saturation voltage

Brake diode forward voltage

CE(sat)Br

Tj = 25

C, I

= 5A, Input = OFF

= 5V, V

= 15V Input = ON, Tj = 25

C, Ic = 5A

Switching times

FWD reverse recovery time

1/2 Bridge inductive, Input = ON

= 600V, Ic = 5A, Tj = 125

= 5V, V

= 15V, V

= 15V

Note : ton, toff include delay time of the internal control

circuit.

Short circuit endurance
(Output, Arm, and Load, Short
Circuit Modes)

Switching SOA

= 5V, V

= 15V, V

CIN

= 5V

= 5V, V

= 15V, V

CIN

= 5V

0.3

3.6

3.5

3.6

· No destruction

· No protecting operation

· No F

output

Integrated between input terminal-V

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12013-A

FLAT-BASE TYPE

INSULATED TYPE

Jan. 2000

ELECTRICAL CHARACTERISTICS

(Tj = 25

C, V

= 15V, V

= 5V unless otherwise noted)

(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only.

(b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit.

(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The

circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.

(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen-

tarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is
not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to
excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri-
ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut
down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back
from its F

pin of the ASIPM indicating a short circuit situation.

OTr

DBr

DHr

FO(H)

FO(L)

= 5V, V

= 15V, T

= 20 ~ 100

(Note 4)

d(read)

CL(H)

CL(L)

= 15V

= 5V

= 20 ~ 100

(Fig.4)

int

C+(200%)

C(200%)

C+

Ratings

Min.

Trip level

Reset level

Trip level

Reset level

Trip level

Reset level

Trip level

Reset level

Filter time

Over tenperature
protection

Signal output cur-
rent of CL operation

Ic = 0A

Ic = I

OP(200%)

Ic = I

OP(200%)

Allowable input signal dead time
for blocking arm shoot-through

100

C, Tj

125

= 15V, V

= 5V, T

= 20

C ~ +100

Note 3)

Relates to corresponding inputs (Except brake part)
T

= 20

C ~ +100

Relates to corresponding inputs (Except brake part)

Condition

Symbol

Item

Typ.

Max.

Unit

Input inter-lock sensing

Offset change area vs temperature

Idle

Active

Supply circuit
u n d e r a n d
over voltage
protection

Idle

Active

Fault output current

kHz

dead

Analogue signal linearity with
output current

= 15V, V

= 5V, T

= 20 ~ 100

Analogue signal output voltage limit

Ic > I

OP(200%)

, V

= 15V,

= 5V

(Fig. 4)

(200%)

Analogue signal overall linear
variation

Analogue signal data hold
accuracy

-V

(200%)

Correspond to max. 500

s data hold period only,

Ic = I

OP(200%)

(Fig. 5)

After input signal trigger point

(Fig. 8)

Open collector onput

Tj = 25

(Fig. 7), (Note 5)

= 5V, V

= 15V

= 20

C ~ +100

125

Open collector output

4.0

1.87

0.77

2.97

4.0

4.84

8.2

100

10.0

10.5

11.05

11.55

18.00

16.50

2.27

1.17

3.37

1.1

5.85

14.4

110

11.0

11.5

12.00

12.50

19.20

17.50

500

100

2.57

1.47

3.67

0.7

7.38

20.9

120

12.0

12.5

12.75

13.25

20.15

18.65

Analogue signal reading time

CL warning operation level

Short circuit current trip level

PWM

PWM input frequency

Allowable input on-pulse width

5.0

4.8

, V

800

Control supply voltage

Applied between P-N

Applied between V

-GND, C

BU+

-C

, C

BV+

-C

BW+

-C

Condition

Symbol

Item

Ratings

Supply voltage

Min.

RECOMMENDED CONDITIONS

Typ.

Max.

Unit

Control supply voltage

Applied between V

-GND

13.5

600

15.0

16.5

5.2

CIN(on)

CIN(off)

PWM

dead

Using application circuit

4.8

4.0

0.3

kHz

Supply voltage ripple

Input ON voltage

Input OFF voltage

PWM Input frequency

Arm shoot-through blocking time

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12013-A

FLAT-BASE TYPE

INSULATED TYPE

Jan. 2000

delay time

Short circuit sensing signal V

Error output F

Gate signal Vo of each phase
upper arm(ASIPM internal)

Input signal V

CIN

of each phase

upper arm

Input signal V

CIN(p)

of each phase upper arm

Input signal V

CIN(n)

of each phase lower arm

Gate signal V

o(p)

of each phase upper arm

(ASIPM internal)

Gate signal V

o(n)

of each phase upper arm

(ASIPM internal)

Error output F

200

Analogue output signal

data hold range

400

300

100

300

400

+(200%)

(200%)

(V)

min

max

Real load current peak value.(%)(I

=15V

=5V

100°C

Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-

neously in "LOW" level.

By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and "F

" signal is outputted. After an "input

interlock" operation the circuit is latched. The "F

" is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,

whichever comes in later.

Note : Shor t circuit protection operation. The protection operates with "F

" flag and reset on a pulse-by-pulse scheme. The protection by

gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the "Brake").

Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING

LINEARITY

Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING

"DATA HOLD" DEFINITION

Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION

Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART

(505

500

(505

s)-V

Note ; Ringing happens around the point where the signal output
voltage changes state from "analogue" to "data hold" due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5

s delayed point.

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