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Электронный компонент: P2V28S30ATP-75

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128Mb Synchronous DRAM
JULY.2000
Rev.2.2
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
P2V28S20DTP-7,-75,-8
P2V28S30DTP-7,-75,-8
P2V28S40DTP-7,-75,-8
128Mb SDRAM Specification
MIRA TECHNOLOGY INC.
8F., 68, SEC.3, NANKING E. RD. , TAIPEI, TAIWAN, R.O.C.
TEL: 886-2-25170055.25170066
FAX: 886-2-25174575
JULY.2000
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
DESCRIPTION
P2V28S20ATP is organized as 4-bank x 8,388,608-word x
4-bit Synchronous DRAM with LVTTL interface and
P2V28S30ATP is organized as 4-bank x 4,194,304-word x
8-bit and P2V28S40ATP is organized as 4-bank x 2,097,
152-word x 16-bit. All inputs and outputs are referenced to
the rising edge of CLK.
P2V28S20ATP-7,-75,-8
(4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8
(4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8
(4-BANK x 2,097,152-WORD x 16-BIT)
128Mb Synchronous DRAM
Page-1
- Single 3.3V 0.3V power supply
- Max. Clock frequency -7:143MHz<3-3-3>/-75:133MHz<3-3-3>/-8:100MHz<2-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (P2V28S40ATP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
P2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
PRELIMINARY
Some of contents are described for general products and
are subject to change without notice.
P2V28S20ATP,P2V28S30ATP and P2V28S40ATP
achieve very high speed data rates up to 166MHz, and are
suitable for main memories or graphic memories in com-
puter systems.
FEATURES
ITEM
tCLK
tRAS
tRCD
tAC
tRC
Icc1
Icc6
Clock Cycle Time
Active to Precharge Command Period (Min.)
Row to Column Delay
Access Time from CLK
Ref /Active Command Period
Operation Current (Single Bank)
Self Refresh Current
V28S20D
CL=2
CL=3
CL=2
CL=3
V28S30D
V28S40D
(Min.)
(Min.)
(Max.)
(Max.)
(Min.)
(Max.)
-7
85mA
85mA
85mA
63ns
20ns
5.4ns
45ns
7ns
-
-
1mA
-75
85mA
85mA
85mA
67.5ns
10ns
45ns
20ns
5.4ns
7.5ns
6ns
1mA
-8
70ns
10ns
48ns
20ns
6ns
6ns
8ns
85mA
85mA
85mA
1mA
-7,-75,-8
P2V28S20/30/40ATP
128Mb Synchronous DRAM
JULY.2000
Rev.2.2
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Page-2
PIN CONFIGURATION (TOP VIEW)
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
23
32
24
31
25
30
26
29
27
28
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A2
A3
Vdd
A0
A1
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
NC
A11
A8
A7
A6
A5
A4
Vss
A9
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A2
A3
Vdd
A0
A1
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A2
A3
Vdd
A0
A1
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A8
A7
A6
A5
A4
Vss
A9
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A8
A7
A6
A5
A4
Vss
A9
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
DQM
: Output Disable / Write Mask
A0-11
: Address Input
BA0,1
Vdd
: Power Supply
VddQ
: Power Supply for Output
Vss
: Ground
VssQ
: Ground for Output
400mil 54pin TSOP(II)
: Bank Address
P2V28S20ATP
P2V28S30ATP
P2V28S40ATP
JULY.2000
Rev.2.2
128Mb Synchronous DRAM
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
P2
V 28 S 3 0
TP
-8
Access Item
-7 : 7 ns (143MHz/3-3-3)
-75 : 7.5ns (100MHz/2-2-2 or 133MHz/3-3-3)
-8 : 8 ns (100MHz/2-2-2 or 125MHz/3-3-3)
Package Type
TP : TSOP(II)
Process Generation
Interface
V :LVTTL
Organization
2 : x4, 3 : x8, 4: x16
Synchronous DRAM
Density
128 :128Mbit
Function 0 : Random Column
PSC DRAM
Address Buffer
A0-11
BA0,1
Control Signal Buffer
/CS
/RAS
/CAS
/WE
CLK
CKE
Clock Buffer
Control Circuitry
I/O Buffer
DQ0-7
Mode
Register
DQM
Memory Array
Bank #0
4096 x1024 x8
Cell Array
Memory Array
Bank #1
Cell Array
Memory Array
Bank #2
Cell Array
Memory Array
Bank #3
Cell Array
A
4096 x1024 x8
4096 x1024 x8
4096 x1024 x8
Note:This figure shows the P2V28S30ATP
The A2V28S20ATP configuration is 4096x2048x4 of cell array and DQ0-3
The A2V28S40ATP configuration is 4069x512x16 of cell array and DQ0-15
A : 2nd generation
Page-3
BLOCK DIAGRAM
Type Designation Code
128Mb Synchronous DRAM
JULY.2000
Rev.2.2
P2V28S20ATP-7,-75,-8 (4-BANK x 8,388,608-WORD x 4-BIT)
P2V28S30ATP-7,-75,-8 (4-BANK x 4,194,304-WORD x 8-BIT)
P2V28S40ATP-7,-75,-8 (4-BANK x 2,097,152-WORD x 16-BIT)
Page-4
PIN FUNCTION
CLK
Input
Master Clock:
All other inputs are referenced to the rising edge of CLK
CKE
Input
Clock Enable:
CKE controls internal clock.When CKE is low, internal clock for
the following cycle is ceased. CKE is also used to select
auto / self-refresh.
After self-refresh mode is started, CKE becomes asynchronous input.
Self-refresh is maintained as long as CKE is low.
/CS
Input
Chip Select:
When /CS is high, any command means No Operation.
/RAS, /CAS, /WE
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11
Input
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11.
The Column Address is specified by A0-9,11(x4)/A0-9(x8)/A0-8(x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
BA0,1
Input
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE , READ , WRITE commands.
Input / Output
Input
Din Mask / Output Disable:
When DQM(U/L) is high in burst write, Din for the current cycle is
masked. When DQM(U/L) is high in burst read,
Dout is disabled at the next but one cycle.
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
Data In and Data out are referenced to the rising edge of CLK.
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
DQM(x4,x8),
DQMU/L(x16)