n
Transfer molded -- reliable. Contact factory for
other logic specifications.
n
Military models with temperature range of -55 to
+125oC and ceramic package IC to meet MIL-
STD-883C, add suffix "M" to part number.
n
Military models as "M" above, but with ceramic
package IC screened to MIL-STD -883C, add
suffix "MX" to part number.
n
Military models as "MX" above, but with in-house
burn-in and thermal shock, add suffix "MY" to
part number.
n
Specifications are for Schottky TTL only.
n
5 to 500 ns delays available.
n
3-bit binary (1, 2, 4) programming gives 7 equal
step delays.
n
Low on E enables output.
n
Complimentary output available.
n
Available in 19 step delays from 1 to 64 ns.
n
Designed for leading-edge timing.
n
Low inherent delay from:
Input to output = 6.0 + 1.5 ns.
Input to output = 3.0 + 1.5 ns.
E to output = 10.0 ns maximum
Sn to output = 13.0 ns maximum
TTL Programmable Delay Lines
TWO PEARL BUCK COURT
l
BRISTOL, PA 19007-6812
l
TEL 215-781-6400
l
FAX 215-781-6403
l
www.pulsespecialty.com
MODEL HTTLDL ACTIVE TTL DELAY LINES
TECHNITROL
PAR T NO.
Step Delay
ns + ns
M ax. Delay
n s + ns
Output Rise
Time (ns)
TTLPG301
1.0 + .4
13.0 + 2.0
2.0
TTLPG302
2.0 + .6
20.0 + 2.0
2.0
TTLPG303
3.0 + 1.0
27.0 + 2.0
2.0
TTLPG304
4.0 + 1.0
34.0 + 2.0
2.0
TTLPG305
5.0 + 1.5
41.0 + 2.0
2.0
TTLPG306
6.0 + 1.5
48.0 + 2.0
2.0
TTLPG307
7.0 + 1.5
55.0 + 2.5
2.0
TTLPG308
8.0 + 1.5
62.0 + 2.5
2.0
TTLPG309
9.0 + 1.5
69.0 + 3.0
2.0
TTLPG310
10.0 + 1.5
76.0 + 3.5
2.0
TTLPG315
15.0 + 1.5
111.0 + 5.0
2.0
TTLPG320
20.0 + 1.5
146.0 + 7.0
2.0
TTLPG325
25.0 + 1.5
181.0 + 9.0
2.0
TTLPG330
30.0 + 2.0
216.0 + 11.0
2.0
TTLPG335
35.0 + 2.0
251.0 + 12.0
2.0
TTLPG340
40.0 + 2.5
286.0 + 14.0
2.0
TTLPG345
45.0 + 3.0
321.0 + 16.0
2.0
TTLPG350
50.0 + 3.5
356.0 + 17.0
2.0
TTLPG364
64.0 + 4.0
454.0 + 23.0
2.0
TTLPG
16-pin DIP
For delay adjustments via BCD programming. Simplifies minor adjustments and adds
flexibility. Although indicated below that programmable modules are available up to
3-bit, 6-bit modules are available through a simple combination of modules (see next page).
Delay Characteristics measured at Vcc = 5.0V and Ta = 25
o
C, no load.
Delay time measured at 1.5V level.
Rise Time measured @ 0.8V to 2.0V levels.
For minimum input pulse width -- contact factory.
TWO PEARL BUCK COURT
l
BRISTOL, PA 19007-6812
l
TEL 215-781-6400
l
FAX 215-781-6403
l
www.pulsespecialty.com
SCHEMATIC
MECHANICAL OUTLINE
Notes
n
Only the pins specified in the schematics
are provided with each package.
n
Pin numbers shown are for reference only
and are not necessarily marked on unit.
n
Lead material is electro tin plated
(alloy 42) or solder dipped.
n
All specifications are subject to change
without notice.
TTLPG
16-pin DIP
Delay Characteristics measured at Vcc = 5.0V, 25
o
C, no load.
Delay Tolerance +2 ns or 5%, whichever is greater.
Rise time measured @ 0.8V to 2.0V levels.
For minimum input pulse width -- contact factory.
CASCADE EXAMPLE
Example of 6-bit cascade with 63 steps of 1.0 ns delay with an
inherent (or reference) delay of 12.0 ns (2 x 6.0 ns).
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