ChipFind - документация

Электронный компонент: P3C1256-20JI

Скачать:  PDF   ZIP
133
P3C1256
P3C1256
HIGH SPEED 32K x 8
3.3V STATIC CMOS RAM
3.3V Power Supply
High Speed (Equal Access and Cycle Times)
-- 12/15/20/25 ns (Commercial)
-- 15/20/25 ns (Industrial)
Low Power
-- 360 mW Active
Single 3.3 Volts
0.3Volts Power Supply
Easy Memory Expansion Using
CE
CE
CE
CE
CE
and
OE
OE
OE
OE
OE
Inputs
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
1519B
1Q97
Means Quality, Service and Speed
INPUT
DATA
CONTROL
262,144-BIT
MEMORY
ARRAY
COLUMN I/O
I/O
1
I/O
2
COLUMN
SELECT
WE
OE
CE


ROW SELECT
A
A

A
A
(7)
(8)


Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
--28-Pin 300 mil DIP and SOJ
FEATURES
DESCRIPTION
The P3C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 3.3V
0.3V tolerance power
supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P3C1256 is a member of a family of PACE RAMTM prod-
ucts offering fast access times.
The P3C1256 device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A
0
to A
14
. Reading is ac-
complished by device selection (
CE
and output enabling
(
OE
) while write enable (
WE
) remains HIGH. By present-
ing the address under these conditions, the data in the
addressed memory location is presented on the data in-
put/output pins. The input/output pins stay in the HIGH Z
state when either
CE
or
OE
is HIGH or
WE
is LOW.
Package options for the P3C1256 include 28-pin 300 mil
DIP and SOJ packages.
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CE
WE
A
11
OE
I/0
2
I/0
3
I/0
8
I/0
7
I/0
6
I/0
5
I/0
4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/0
1
A14
A13
A12
VCC
DIP (P5), SOJ (J5)
TOP VIEW
134
P3C1256
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Supply Voltage
3.0V
V
CC
3.6V
Industrial (-40
C to 85
C)
3.0
V
CC
3.6V
Commercial (0
C to 70
C)
V
CC
= 3.6V, I
OUT
= 0 mA
CE
= V
CC
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
SB
I
SB1
Output High Voltage
(I/O
0
- I/O
7
)
Output Low Voltage
(I/O
0
- I/O
8
)
Input High Voltage
Input Low Voltage
V
CC
Current
CMOS Standby Current
V
CC
Current
TTL Standby Current
Output Leakage Current
Input Leakage Current
I
OH
= 4mA, V
CC
= 3.0V
I
OL
= 8 mA
I
OL
= 10 mA
V
CC
= 3.6V, I
OUT
= 0 mA
CE
= V
CC
GND
V
OUT
V
CC
CE
= V
CC
GND
V
IN
V
CC
Test Conditions
Min
Max
Unit
2.4
2.2
-0.5
V
V
V
V
V
A
A
mA
mA
0.4
0.5
V
CC
+ 0.3
0.8
20
3
-5
-5
+5
+5
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress
ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can
adversely affect device reliability.
Symbol
Parameter
Min
Max
Unit
V
CC
Supply Voltage with Respect to GND
-0.5
7.0
V
V
TERM
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
V
CC
+ 0.5
V
T
A
Operating Ambient Temperature
-40
85
C
S
TG
-55
125
C
I
OUT
Output Current into Low Outputs
25
mA
I
LAT
Latch-up Current
>200
mA
Storage Temperature
135
P3C1256
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
CAPACITANCES
(V
CC
= 5.0V, T
A
= 25
C, f = 1.0 MHz)
Symbol
Parameter
Test Conditions
Max
Unit
C
IN
C
OUT
Input Capacitance
Output Capacitance
V
IN
= 0V
V
OUT
= 0V
10
10
pF
pF
Symbol
Parameter
Min
Unit
t
RC
ns
t
AA
Address Access Time
t
AC
Chip Enable Access
Time
t
OH
Output Hold from
Address Change
ns
t
LZ
Chip Enable to
Output in Low Z
ns
t
HZ
Chip Disable to
Output in High Z
ns
t
OE
Output Enable Low
to Data Valid
ns
t
OLZ
Output Enable Low
to Low Z
ns
t
OHZ
Output Enable High
to High Z
t
PU
Chip Enable to
Power Up Time
ns
t
PD
Chip Disable to
Power Down Time
ns
Read Cycle Time
2
2
0
-12
ns
ns
ns
-25
-20
-15
Max
Min
Max
25
25
25
2
2
10
12
0
10
0
20
Min
20
20
20
2
2
9
11
0
9
0
20
Max
Min
Max
15
15
15
2
2
8
9
0
7
0
15
12
12
12
7
7
0
6
12
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e.,
CE
, and
WE
V
IL
(max),
OE
is high. Switching inputs are 0V
and 3V.
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Unit
I
CC
Dynamic Operating Current
Commercial
Industrial
mA
mA
Temperature
Range
-12
110
N/A
-15
100
115
-20
95
110
-25
90
105
Test
Conditions
*
*
136
P3C1256
Notes:
1.
WE
is HIGH for READ cycle.
2.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with
CE
1
transition
LOW .
4. Transition is measured
200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
READ CYCLE NO. 1 (
OE
OE
OE
OE
OE
CONTROLLED)
(1)
OLZ
ADDRESS
OE
t
RC
DATA OUT
(5)
t
OH
CE
t
t
HZ
t
OHZ
t
(4)
(4)
(4)
(4)
t
OE
t
AA
AC
t
AC
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (
CE
CE
CE
CE
CE
CONTROLLED)
t
ADDRESS
DATA OUT
AA
t
t
OH
DATA VALID
PREVIOUS DATA VALID
(5)
RC
tAC
CE
DATA OUT
tRC
tLZ
(8)
DATA VALID
ICC
ISB
tPU
HIGH IMPEDANCE
tPD
tHZ
VCC SUPPLY
CURRENT
137
P3C1256
AC CHARACTERISTICS--WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Notes:
6.
CE
1
and
WE
must be LOW for WRITE cycle.
7.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
8.
If
CE
1
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first
transitioning address.
ADDRESS
CE
tWC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT
DATA UNDEFINED
(9)
(4)
tCW
tAW
tWP
tDW
tAH
tDH
tOW
tAS
tWZ
(4,7)
(7)
Symbol
Parameter
Min
Unit
t
WC
ns
t
CW
Chip Enable Time to
End of Write
t
AW
Address Valid to
End of Write
t
AS
Address Set-up
Time
ns
t
WP
Write Pulse Width
ns
t
AH
Address Hold Time
Data Valid to End of
Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
Write Cycle Time
0
9
-12
ns
ns
-25
-20
-15
Max
Min
Max
25
0
18
Min
20
0
15
Max
Min
Max
15
0
11
12
ns
t
DW
ns
t
DH
0
0
0
0
ns
t
WZ
7
8
10
11
ns
t
OW
3
3
3
3
ns
WRITE CYCLE NO. 1 (
WE
WE
WE
WE
WE
CONTROLLED)
(6)
10
10
0
8
12
15
18
12
15
18
0
10
0
12
0
15