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Электронный компонент: P4C1024-25M

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P4C1024 MILITARY
ADVANCE INFORMATION
HIGH SPEED 128K x 8
CMOS STATIC RAM
The P4C1024 device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (
CE
1
low and
CE
2
high) and output enabling (
OE
) while write enable
(
WE
) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V
10% tolerance power
supply.
Access times of 20 nanoseconds permit greatly en-
hanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1024
is a member of a family of PACE RAMTM products offer-
ing fast access times.
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
--32-Pin 400 mil and 600 mil Ceramic DIP
--32-Pin CERPACK
--32-Pin LCC
High Speed (Equal Access and Cycle Times)
-- 20/25/35/45/55/70 ns
Single 5 Volts
10% Power Supply
Easy Memory Expansion Using
CE
CE
CE
CE
CE
1,
CE
2
and
OE
OE
OE
OE
OE
Inputs
Common Data I/O
Three-State Outputs
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1Q97
Means Quality, Service and Speed
1024.1
INPUT
DATA
CONTROL
262,144-
BIT
MEMORY
ARRAY
COLUMN
I/O
I/O
1
I/O
2
COLUMN
SELECT
WE
CE1
ROW SELECT
A
A
A
A
(8)
(9)
CE2
OE
CONTROL
CIRCUIT
DESCRIPTION
FEATURES
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1024.2
GND
WE
A11
OE
I/O7
I/O6
I/O5
NC
A13
VCC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
15
16
17
18
I/O3
I/O4
CE1
A9
A8
CE2
A15
DIP, SOJ
TOP VIEW
150