117
P4C1256
P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
High Speed (Equal Access and Cycle Times)
-- 12/15/20/25/35 ns (Commercial)
-- 15/20/25/35/45 ns (Industrial)
-- 20/25/35/45/55/70 ns (Military)
Low Power
-- 880 mW Active (Commercial)
Single 5V
10% Power Supply
Easy Memory Expansion Using
CE
CE
CE
CE
CE
and
OE
OE
OE
OE
OE
Inputs
Common Data I/O
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
1519B
1Q97
Means Quality, Service and Speed
INPUT
DATA
CONTROL
262,144-BIT
MEMORY
ARRAY
COLUMN I/O
I/O
1
I/O
2
COLUMN
SELECT
WE
OE
CE
ROW SELECT
A
A
A
A
(7)
(8)
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
--28-Pin 300 mil DIP and SOJ
--28-Pin 600 mil Ceramic DIP
--28-Pin LCC(350 mil x 550 mil)
--32-Pin LCC (450 mil x 550 mil)
FEATURES
DESCRIPTION
The P4C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V
10% tolerance power
supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P4C1256 is a member of a family of PACE RAMTM prod-
ucts offering fast access times.
The P4C1256 device provides asynchronous operation with
matching access and cycle times. Memory locations are
specified on address pins A
0
to A
14
. Reading is accom-
plished by device selection (
CE
and output enabling (
OE
)
while write enable (
WE
) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE
or
OE
is HIGH or
WE
is LOW.
Package options for the P4C1256 include 28-pin 300 mil
DIP and SOJ packages. For military temperature range,
Ceramic DIP and LCC packages are available.
DIP (P5, C5, D5-1), SOJ (J5)
TOP VIEW
32 LCC (L6)
TOP VIEW
See Selection Guide page for 28-pin LCC
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CE
WE
A
11
OE
I/0
2
I/0
3
I/0
8
I/0
7
I/0
6
I/0
5
I/0
4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/0
1
A14
A13
A12
VCC
A
2
A3
NC
CE
A12
A11
NC
GN
D
V
CC
29
28
27
26
25
24
23
5
6
7
8
9
10
11
12
13
22
21
14
18
3
1
16
2
15
32
17
I/O1
A10
OE
I/O8
I/O7
WE
I/O
3
NC
I/O
4
I/O
5
4
31 30
19 20
A4
A5
A6
A7
A8
A9
I/
O
2
I/
O
6
A13
A
1
A
0
A
14
NC
118
P4C1256
P4C1256
MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Pin with
0.5 to +7
V
Respect to GND
Terminal Voltage with
0.5 to
V
TERM
Respect to GND
V
CC
+0.5
V
(up to 7.0V)
T
A
Operating Temperature
55 to +125
C
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under
55 to +125
C
Bias
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE
V
IH
or Mil.
CE
2
V
IL
, V
CC
= Max Ind./Com'l.
f = Max., Outputs Open
___
___
45
30
20
10
___
___
CE
V
HC
or Mil.
CE
2
V
LC
, V
CC
= Max Ind./Com'l.
f = 0, Outputs Open
V
IN
V
LC
or V
IN
V
HC
Standby Power Supply
Current
(CMOS Input Levels)
I
SB1
Industrial
Grade(2)
Ambient
Temperature
GND
V
CC
0V
0V
5.0V
10%
5.0V
10%
0V
5.0V
10%
55
C to +125
C
Military
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
8
10
Unit
pF
pF
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25
C, f = 1.0MHz
n/a = Not Applicable
Symbol
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
V
IH
V
IL
V
HC
V
LC
I
LI
I
LO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Leakage Current
Test Conditions
V
CC
= Max. Mil.
V
IN
= GND to V
CC
Ind./Com'l.
V
CC
= Max.,
CE
= V
IH
, Mil.
V
OUT
= GND to V
CC
Ind./Com'l.
Min
2.2
0.5
(3)
V
CC
0.2
0.5
(3)
10
5
10
5
Max
V
CC
+0.5
0.8
V
CC
+0.5
0.2
+10
+5
+10
+5
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than 3.0V and
100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Typ.
Commercial
40
C to +85
C
0
C to +70
C
Unit
V
V
V
V
A
A
mA
mA
V
OL
Output Low Voltage
(TTL Load)
I
OL
= +8 mA, V
CC
= Min.
0.4
V
Output High Voltage
(TTL Load)
V
OH
I
OH
= 4 mA, V
CC
= Min.
2.4
V
Output Leakage Current
119
P4C1256
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
I
CC
Symbol
Parameter
Temperature
Range
Dynamic Operating Current*
Commercial
Industrial
Military
N/A
N/A
15
N/A
12
20
25
35
45
55
70
Unit
N/A
mA
mA
mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
N/A
N/A
N/A
N/A
170
160
170
155
165
170
150
145
160
155
150
150
150
155
160
165
AC ELECTRICAL CHARACTERISTICS--READ CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable
Low to Low Z
Output Enable
High to High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down
Time
Output Enable
Low to Data
Valid
Min Max Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
-20
-25
-35
-45
-55
-70
-12
-15
Unit
12
2
0
0
12
12
2
5
5
5
12
15
2
2
0
0
15
15
8
7
7
15
20
2
2
0
0
20
20
9
9
9
20
25
3
3
0
0
25
25
11
10
11
20
35
3
3
0
0
35
35
15
15
15
20
45
3
3
0
0
45
45
20
20
20
25
55
3
3
0
0
55
55
25
25
25
30
70
3
3
0
0
70
70
30
30
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
120
P4C1256
Notes:
1.
WE
is HIGH for READ cycle.
2.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with
CE
1
transition
LOW .
4. Transition is measured
200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
READ CYCLE NO. 1 (
OE
OE
OE
OE
OE
CONTROLLED)
(1)
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (
CE
CE
CE
CE
CE
CONTROLLED)
t
ADDRESS
DATA OUT
AA
t
t
OH
DATA VALID
PREVIOUS DATA VALID
(5)
RC
OLZ
ADDRESS
OE
tRC
DATA OUT
(5)
tOH
CE
t
tAC
tOHZ
tHZ
(4)
(4)
(4)
(4)
tOE
tAA
tAC
tAC
CE
DATA OUT
tRC
tLZ
(8)
DATA VALID
ICC
ISB
tPU
HIGH IMPEDANCE
tPD
tHZ
VCC SUPPLY
CURRENT
121
P4C1256
Notes:
6.
CE
1
and
WE
must be LOW for WRITE cycle.
7.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
8.
If
CE
1
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
-35
AC CHARACTERISTICS--WRITE CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
9. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Sym.
t
WC
t
CW
t
AS
t
WP
t
AH
t
DW
t
DH
Parameter
Write Cycle Time
Chip Enable
Time to End of
Write
Address Set-up
Time
Write Pulse
Width
Address Hold
Time
Date Hold Time
Data Valid to
End of Write
Min Max Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
-20
-25
-45
-55
-70
-12
-15
Unit
12
0
0
9
0
8
15
11
0
20
15
0
25
0
18
0
35
0
22
0
45
0
25
0
55
0
30
0
70
0
35
0
9
10
0
9
15
0
11
18
20
0
13
22
25
0
15
30
35
0
20
35
40
0
25
40
45
0
30
ns
ns
ns
ns
ns
ns
ns
ns
t
AW
Address Valid to
End of Write
9
10
15
0
0
Write Enable to
Output in High Z
t
WZ
7
8
10
11
15
18
25
30
ns
Output Active
from End of Write
t
OW
3
3
3
3
5
5
0
0
ns
WRITE CYCLE NO. 1 (
WE
WE
WE
WE
WE
CONTROLLED)
(6)
ADDRESS
CE
tWC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT
DATA UNDEFINED
(9)
(4)
tCW
tAW
tWP
tDW
tAH
tDH
tOW
tAS
tWZ
(4,7)
(7)
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