125
P4C1256L
V
CC
Current (Commercial/Industrial)
-- Operating: 70mA/85mA
-- CMOS Standby: 100
A/100
A
Access Times
--55/70 (Commercial or Industrial)
Single 5 Volts
10% Power Supply
Easy Memory Expansion Using
CE
CE
CE
CE
CE
and
OE
OE
OE
OE
OE
Inputs
locations are specified on address pins A
0
to A
14
. Read-
ing is accomplished by device selection (
CE
and out-
put enabling (
OE
) while write enable (
WE
) remains
HIGH. By presenting the address under these condi-
tions, the data in the addressed memory location is pre-
sented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either
CE
or
OE
is
HIGH or
WE
is LOW.
Package options for the P4C1256L include 28-pin 600
mil DIP and 28-pin 330 mil SOP packages.
P4C1256L
LOW POWER 32K x 8
STATIC CMOS RAM
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
--28-Pin 600 mil DIP
--28-Pin 330 mil SOP
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1Q97
Means Quality, Service and Speed
DESCRIPTION
The P4C1256L device provides asynchronous opera-
tion with matching access and cycle times. Memory
FEATURES
The P4C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V
10% tolerance power
supply.
Access times of 55 ns and 70 ns are available. CMOS
is utilized to reduce power consumption to a low level.
A
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CE
WE
A
11
OE
I/0
2
I/0
3
I/0
8
I/0
7
I/0
6
I/0
5
I/0
4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/0
1
A14
A13
A12
VCC
INPUT
DATA
CONTROL
262,144-BIT
MEMORY
ARRAY
COLUMN I/O
I/O1
I/O2
COLUMN
SELECT
WE
OE
CE
ROW SELECT
A
A
A
A
(7)
(8)
DIP (P6), SOP (S11-2)
TOP VIEW
126
P4C1256L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress
ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can
adversely affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Temperature Range (Ambient)
Supply Voltage
4.5V
V
CC
5.5V
Industrial (-40
C to 85
C)
4.5
V
CC
5.5V
Commercial (0
C to 70
C)
Symbol
Parameter
Min
Max
Unit
V
CC
Supply Voltage with Respect to GND
-0.5
7.0
V
V
TERM
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
V
CC
+ 0.5
V
T
A
Operating Ambient Temperature
-55
125
C
S
TG
-65
150
C
I
OUT
Output Current into Low Outputs
25
mA
I
LAT
Latch-up Current
>200
mA
Storage Temperature
Symbol
Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
SB
I
SB1
Output High Voltage
(I/O
0
- I/O
7
)
Output Low Voltage
(I/O
0
- I/O
7
)
Input High Voltage
Input Low Voltage
V
CC
Current
CMOS Standby Current
(CMOS Input Levels)
V
CC
Current
TTL Standby Current
(TTL Input Levels)
Output Leakage Current
Input Leakage Current
I
OH
= 1mA, V
CC
= 4.5V
I
OL
= 2.1mA
V
CC
= 5.5V, I
OUT
= 0 mA
CE
V
CC
-0.2V
V
CC
= 5.5V, I
OUT
= 0 mA
CE
= V
IH
GND
V
OUT
V
CC
Ind'l.
CE
V
IH
Com'l.
Test Conditions
Min
Max
Unit
2.4
2.2
-0.5
-5
-2
-5
-2
V
V
V
V
A
mA
A
0.4
V
CC
+ 0.3
0.8
+5
+2
3
100
+5
+2
A
GND
V
IN
V
CC
Ind'l.
Com'l.
127
P4C1256L
Symbol
Parameter
Test Conditions
Max
Unit
C
IN
C
OUT
Input Capacitance
Output Capacitance
V
IN
= 0V
V
OUT
= 0V
7
9
pF
pF
Symbol
Parameter
-55
Min
Max
-70
Min
Max
Unit
t
RC
55
ns
t
AA
Address Access Time
55
70
ns
t
AC
Chip Enable Access
Time
55
70
ns
t
OH
Output Hold from
Address Change
5
5
ns
t
LZ
Chip Enable to
Output in Low Z
5
5
ns
t
HZ
Chip Disable to
Output in High Z
20
25
ns
t
OE
Output Enable Low
to Data Valid
30
35
ns
t
OLZ
Output Enable Low
to Low Z
5
5
ns
t
OHZ
Output Enable High
to High Z
20
25
ns
t
PU
Chip Enable to
Power Up Time
0
0
ns
t
PD
Chip Disable to
Power Down Time
55
70
ns
Read Cycle Time
70
CAPACITANCES
(V
CC
= 5.0V, T
A
= 25C, F = 1.0 MHz)
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e.
CE
and
WE
V
IL
(max),
OE
is high. Switching
inputs are 0V and 3V.
**As above but @ f=1 MHz and V
IL
/ V
IH
= 0V/ V
CC
.
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
-55
-70
Unit
I
CC
Dynamic Operating Current
Commercial
Industrial
70
85
70
85
15
25
15
25
mA
mA
-55
-70
Temperature
Range
*
**
128
P4C1256L
READ CYCLE NO. 1 (
OE
OE
OE
OE
OE
CONTROLLED)
(1)
NOTES:
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (
CE
CE
CE
CE
CE
CONTROLLED)
t
ADDRESS
DATA OUT
AA
t
t
OH
DATA VALID
PREVIOUS DATA VALID
(5)
RC
t
CE
1
DATA OUT
AC
t
RC
t
LZ
DATA VALID
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
t
HZ
SUPPLY
CC
CURRENT
V
(8)
OLZ
ADDRESS
OE
t
RC
DATA OUT
(5)
t
OH
CE
t
t
HZ
t
OHZ
t
(4)
(4)
(4)
(4)
t
OE
t
AA
AC
t
AC
1.
WE
is HIGH for READ cycle.
4. Transition is measured
200 mV from steady state voltage
2.
CE
is LOW and
OE
is LOW for READ cycle.
prior to change, with loading as specified in Figure1. This
3. ADDRESS must be valid prior to, or coincident with
parameter is sampled and not 100% tested.
CE
transition LOW.
5. READ Cycle Time is measured from the last valid address to
the first transitioning address.
129
P4C1256L
Notes:
6.
CE
and
WE
must be LOW for WRITE cycle.
7.
OE
is LOW for this WRITE cycle to show twz and tow.
8. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
WRITE CYCLE NO. 1 (
WE
WE
WE
WE
WE
CONTROLLED)
(6)
Symbol
Parameter
-55
Max
-70
Max
Unit
Min
Min
t
WC
t
CW
t
AS
t
WP
t
AH
t
DH
t
WZ
t
OW
Write Cycle Time
55
70
ns
Chip Enable Time
to End of Write
50
60
ns
Address Valid to
End of Write
50
60
ns
Address Set-up
Time
0
0
ns
Write Pulse Width
40
50
ns
Address Hold
Time
0
0
ns
Data Valid to End
of Write
25
30
ns
Data Hold Time
0
0
ns
Write Enable to
Output in High Z
25
30
ns
Output Active from
End of Write
5
5
ns
t
AW
t
DW
ADDRESS
CE
t
WC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT
DATA UNDEFINED
(9)
(4)
t
CW
t
AW
t
WP
t
DW
t
AH
t
DH
t
OW
t
AS
t
WZ
(4,7)
(7)
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