19
P4C148/P4C149
DESCRIPTION
The P4C148 and P4C149 are 4,096-bit ultra high-speed
static RAMs organized as 1K x 4. Both devices have
common input/output ports. The P4C148 enters the standby
mode when the chip enable (
CE
) goes HIGH; with CMOS
input levels, power consumption is extremely low in this
mode. The P4C149 features a fast chip select capability
using
CS
. The CMOS memories require no clocks or
refreshing, and have equal access and cycle times. Inputs
are fully TTL-compatible. The RAMs operate from a single
5V
10% tolerance power supply.
P4C148, P4C149
ULTRA HIGH SPEED 1K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
10/12/15/20/25 ns (Commercial)
15/20/25/35 ns (P4C148 Military)
Low Power Operation
715 mW Active
10 (Commecial)
550 mW Active
25 (Commercial)
110 mW Standby (TTL Input) P4C148
55 mW Standby (CMOS Input) P4C148
Single 5V
10% Power Supply
Two Options
P4C148 Low Power Standby Mode
P4C149 Fast Chip Select Control
Common Input/Output Ports
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
18 Pin 300 mil DIP
1Q97
Means Quality, Service and Speed
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption when active;
for the P4C148, consumption is further reduced in the
standby mode.
The P4C148 and P4C149 are available in 18-pin 300 mil
DIP packages providing excellent board level densities.
A
CE/CS
WE
INPUT
DATA
CONTROL
ROW
SELECT
4,096-BIT
MEMORY
ARRAY
COLUMN I/O
A
A
A
I/O
1
I/O
2
I/O
3
I/O
4
COLUMN
SELECT
A
A
A
A
POWER
DOWN
P4C148 ONLY
A
A
P4C148 DIP (P1, D1)
P4C149 DIP (P1)
TOP VIEW
CE
,
CS
I/O3
A4
A0
A1
A2
A3
A5
A6
A9
A8
A7
I/O4
VCC
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
WE
I/O2
I/O1
GND
20
P4C148/P4C149
MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Pin with
0.5 to +7
V
Respect to GND
Terminal Voltage with
0.5 to
V
TERM
Respect to GND
V
CC
+0.5
V
(up to 7.0V)
T
A
Operating Temperature
55 to +125
C
Temperature
Range
V
CC
= Max.,
CE
,
CS
= V
IH
,
V
OUT
= GND to V
CC
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under
55 to +125
C
Bias
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25
C, f = 1.0MHz)
Grade
(2)
Commercial
Military
Symbol
Parameter
Conditions Typ. Unit
C
IN
Input Capacitance
V
IN
= 0V
5
pF
C
OUT
Output Capacitance V
OUT
= 0V
7
pF
Ambient Temp
0C to 70C
-55C to +125C
Gnd
0V
0V
V
CC
5.0V
10%
5.0V
10%
RECOMMENDED OPERATING
CONDITIONS
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
SB
I
SB1
Parameter
Output High Voltage
(TTL Load)
Output Low Voltage
(TTL Load)
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Standby Power Supply
Current (TTL Input Levels)
Standby Power Supply
Current
(CMOS Input Levels)
Test Conditions
I
OH
= 4 mA, V
CC
= Min.
V
CC
= Max., V
IN
= GND to V
CC
Unit
V
V
V
mA
mA
A
A
V
I
OL
= +8 mA, V
CC
= Min
CE
V
IH
, V
CC
= Max.,
f=Max., Outputs Open
CE
V
HC
, V
CC
= Max., f= 0,
Outputs Open
V
IN
0.2V or V
IN
V
CC
-0.2V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)
Max.
0.4
0.8
Sym.
Min.
2.4
Max.
0.4
V
CC
+0.5
2.2
0.5
(3)
0.8
P4C148
P4C149
Min.
2.4
2.2
V
CC
+0.5
0.5
(3)
Mil.
Comm'l
Mil.
Comm'l
Mil.
Comm'l
Mil.
Comm'l
10
5
10
5
+10
+5
+10
+5
15
10
30
23
N/A
N/A
N/A
N/A
N/A = Not Applicable
Parameter
Commercial
Military
Symbol
Unit
-35
-25
-20
-15
-12
130
N/A
130
N/A
120
145
115
135
100
125
N/A
120
mA
mA
-10
Dynamic Operating Current
I
CC
POWER DISSIPATION CHARACTERISTICS VS. SPEED
10
5
+10
+5
+10
+5
10
5
21
P4C148/P4C149
Chip Disable to Power Down
Time
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than 3.0V and
100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured
200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
ADDRESS
DATA OUT
t
AA
DATA VALID
PREVIOUS DATA VALID
(8)
t
OH
t
RC
TIMING WAVEFORM OF READ CYCLE NO. 1
(5)
Sym.
Read Cycle Time
Chip Enable Access Time
(P4C148)
Unit
AC CHARACTERISTICS--READ CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
Parameter
Address Access Time
Chip Select Access Time
(P4C149)
Output Hold from Address
Change
Chip Enable to Output in Low Z
-35
Max
Max
Min
Max
Min
-25
Max
Min
-20
Max
Min
Min
Max
Min
Read Command Setup Time
Read Command Hold Time
Chip Enable to Power Up Time
Chip Disable to Output in High Z
t
RC
t
AA
t
AC
t
AC
*
t
OH
t
LZ
*
t
HZ
*
t
RCS
t
RCH
t
PU
t
PD
10
3
2
0
0
0
10
10
8
4
10
12
3
2
0
0
0
12
12
10
5
12
15
3
2
0
0
0
15
15
12
6
15
20
3
2
0
0
0
20
20
14
8
20
25
3
2
0
0
0
25
25
15
10
25
35
3
2
0
0
0
35
35
20
14
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-10
-12
-15
t
CE
DATA OUT
AC
t
RC
t
LZ
DATA VALID
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
(7)
(7)
t
HZ
SUPPLY
CURRENT
(P4C148 ONLY)
CC
V
t
RCS
t
RCH
WE
22
P4C148/P4C149
0
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE
WE
WE
WE
CONTROLLED)
(9)
ADDRESS
CE
t
WC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT
DATA UNDEFINED
(11)
(12)
t
CW
t
AW
t
WP
t
DW
t
WR
t
AH
t
DH
t
OW
t
AS
t
WZ
(10, 12)
12. Transition is measured
200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is
sampled and not 100% tested.
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
high, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CE
CE
CE
CE
CE
/
CS
CS
CS
CS
CS
CONTROLLED)
(9)
t
t
WE
ADDRESS
CE
DATA OUT
DATA IN
t
WC
DATA VALID
HIGH IMPEDANCE
(11)
t
AS
t
CW
t
AW
t
WP
DW
AH
WR
t
DH
t
Sym.
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time from
End of Write
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
-10
Min
10
8
8
0
8
0
5
0
0
Max
5
-12
Min
12
10
10
0
10
0
6
0
0
Max
6
-15
Min
15
12
12
0
12
0
7
0
0
Max
7
-20
Min
20
16
16
0
16
0
9
0
0
Max
7
-25
Min
25
20
20
0
20
0
12
0
Max
8
AC CHARACTERISTICS--WRITE CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
-35
Min
35
25
25
0
25
0
16
0
0
Max
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
23
P4C148/P4C149
Mode
CE
WE
Output
Power
Standby
H
X
High Z
Standby
Read
L
H
D
OUT
Active
Write
L
L
High Z
Active
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST CONDITIONS
TRUTH TABLE
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Due to the ultra-high speed of the P4C147, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the V
CC
and ground planes
directly up to the contactor fingers. A 0.01
F high frequency capacitor
is also required between V
CC
and ground. To avoid signal reflections,
proper termination must be used; for example, a 50
test environment
should be terminated into a 50
load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116
resistor must be used in series with
D
OUT
to match 166
(Thevenin Resistance).
RTH = 166.5
VTH = 1.73 V
DOUT
30pF (5pF* for tHZ, tLZ, tOHZ,
tOLZ, tWZ and tOW)
DOUT
255
480
+5
30pF (5pF* for tHZ, tLZ, tOHZ,
tOLZ, tWZ and tOW)
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