25
P4C150
DESCRIPTION
The P4C150 is a 4,096-bit ultra high-speed static RAM
organized as 1K x 4 for high speed cache applications.
The RAM features a reset control to enable clearing all
words to zero within two cycle times. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs and outputs are fully TTL-compat-
ible. The RAM operates from a single 5V
10% tolerance
power supply.
Access times as fast as 10 nanoseconds are available
permitting greatly enhanced system operating speeds.
Single 5V
10% Power Supply
Separate Input and Output Ports
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
24-Pin 300 mil DIP
24-Pin 300 mil SOIC
28-Pin LCC (350 x 550 mils)
24-Pin CERPACK
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
10/12/15/20/25 ns (Commercial)
15/20/25/35 ns (Military)
Chip Clear Function
Low Power Operation
713 mW Active
10 ns (Commercial)
550 mW Active
25 ns (Commercial)
1Q97
Means Quality, Service and Speed
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
A
A
A
A
INPUT
DATA
CONTROL
ROW
SELECT
4,096-BIT
MEMORY
ARRAY
COLUMN I/O
I
1
I
2
I
3
I
4
COLUMN
SELECT
A
A
A
A
A
A
O
1
O
2
O
3
O
4
CS
OE
RS
WE
P4C150
ULTRA HIGH SPEED 1K X 4
RESETTABLE STATIC CMOS RAM
Time required to reset is only 20 ns for the 10 ns SRAM.
CMOS is used to reduce power consumption to a low
level.
The P4C150 is available in 24-pin 300 mil DIP and SOIC
packages providing excellent board level densities. The
device is also available in a 28-pin LCC package as well
as a 24-pin FLATPACK for military applications.
A
4
I
A
0
A
1
A
2
A
3
A
5
A
6
A
9
A
8
A
7
RS
CS
V
CC
1
2
3
4
5
6
7
8
9
10
11
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
OE
WE
4
3
I
I
4
3
O
O
12
GND
2 3
2 4
1
2
I
I
1
2
O
O
LCC (L5)
TOP VIEW
A
1
A4
A5
NC
A6
I1
I2
OE
A7
RS
CS
GN
D
NC
A
0
V
CC
26
25
24
23
22
21
20
4
5
6
7
8
9
10
11
12
19
18
13
17
3
27
1
15
2
14
28
16
O1
WE
NC
I4
I3
A
9
O
2
NC
O
3
O
4
A3
A2
A8
DIP (P4, D4), SOIC (S4)
CERPACK (F4) SIMILAR
TOP VIEW
26
P4C150
MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Pin with
0.5 to +7
V
Respect to GND
Terminal Voltage with
0.5 to
V
TERM
Respect to GND
V
CC
+0.5
V
(up to 7.0V)
T
A
Operating Temperature
55 to +125
C
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under
55 to +125
C
Bias
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25
C, f = 1.0MHz)
Grade
(2)
Commercial
Military
Symbol
Parameter
Conditions Typ. Unit
C
IN
Input Capacitance
V
IN
= 0V
5
pF
C
OUT
Output Capacitance V
OUT
= 0V
7
pF
Ambient Temp
0C to 70C
-55C to +125C
Gnd
0V
0V
V
CC
5.0V
10%
5.0V
10%
RECOMMENDED OPERATING
CONDITIONS
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Symbol
Output High Voltage
(TTL Load)
Output Low Voltage
(TTL Load)
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Test Conditions
I
OH
= 4 mA, V
CC
= Min.
I
OL
= +8 mA, V
CC
= Min
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH
, V
OUT
= GND to V
CC
P4C147
Min.
2.4
2.2
0.5
(3)
5
5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)
Max.
V
CC
=+0.5
0.8
+5
+5
Unit
V
V
V
A
A
V
0.4
Symbol
Parameter
Temperature
Range
130
N/A
Unit
mA
mA
130
N/A
120
145
115
135
100
125
N/A
120
Commercial
Military
Dynamic Operating Current
I
CC
-10
-12
-15
-20
-25
-35
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to MAXIMUM rating condi-
tions for extended periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than 3.0V and
100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
POWER DISSIPATION CHARACTERISTICS VS. SPEED
27
P4C150
Notes:
5.
WE
is HIGH for READ cycle.
6.
CS
and
OE
are LOW for READ cycle.
7.ADDRESS must be valid prior to, or concident with,
CS
transition
LOW, t
AA
must still be met.
Min
Sym.
t
RC
t
AA
t
AC
t
HZ
t
OE
t
OLZ
Read Cycle Time
Chip Select Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable to
Data Valid
Output Enable to
Output in Low Z
-10
-12
-15
-20
-25
-35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
10
8
4
10
2
2
AC CHARACTERISTICS--READ CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
12
2
2
Max
12
10
6
Min
15
2
2
Max
15
12
8
Min
20
2
2
Max
20
14
10
Min
25
2
2
Max
25
15
13
Min
35
2
2
Max
35
35
15
Parameter
Address Access Time
t
OH
t
LZ
t
OHZ
Output Disable to
Output in High Z
7
9
10
14
15
20
2
2
2
2
2
2
5
7
9
11
13
16
ns
TIMING WAVEFORM OF READ CYCLE NO. 1
(5,6)
t
CS
DATA OUT
AC
t
RC
t
LZ
DATA VALID
t
OLZ
HIGH IMPEDANCE
(8)
(8)
t
HZ
t
OE
(8)
t
OHZ
OE
(8)
(7)
ADDRESS
DATA OUT
t
AA
DATA VALID
PREVIOUS DATA VALID
(8)
t
OH
t
RC
8. Transition is measured
200 mV from steady state volt-
age prior to change, with loading as specified in Figure 1.
9. Read Cycle Time is measured from the last valid address
to the first transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 2 (
CS
CS
CS
CS
CS
CONTROLLED)
(5, 7)
28
P4C150
TIMING WAVEFORM OF READ CYCLE NO. 3 (
OE
OE
OE
OE
OE
Controlled)
(5)
AC CHARACTERISTICS--RESET CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
Symbol
Parameter
-10
-12
-15
-20
-25
-35
Min Max
Min Max
Min Max
Min Max
Min Max
Min Max
Write Enable High to
Beginning of Reset
Chip Select Low to
Beginning of Reset
Reset Pulse Width
Chip Select Hold
after End of Reset
Write Enable Hold
after End of Reset
Reset High to
Ourput in Low Z
Reset Low to
Output in High Z
Reset Cycle Time
t
RRC
t
WER
t
CR
t
RP
t
HWR
t
RHZ
t
RLZ
20
0
0
10
0
10
24
0
0
12
12
30
0
0
15
0
15
0
0
40
0
0
20
0
20
0
50
0
25
0
25
0
70
0
30
0
35
0
Unit
ns
ns
ns
ns
ns
0
0
ns
t
HCR
ns
0
0
0
8
0
10
0
12
0
16
0
20
0
ns
TIMING WAVEFORM OF RESET CYCLE
HWR
t
RS
ADDRESS
WE
(DATA OUTPUT)
HIGH IMPEDANCE
RHZ
t
RLZ
CS
t
OUTPUT VALID ZERO
t
HCR
t
WER
t
CR
O
1
O
4
t
RRC
t
RP
ADDRESS
t
RC
(9)
1521 05
OE
t
AA
t
OLZ
CS
OE
t
OH
t
AC
t
OHZ
t
(8)
(8)
DATA OUT
t
HZ
t
LZ
(8)
(8)
29
P4C150
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE
WE
WE
WE
CONTROLLED)
(10)
12. Write Cycle Time is measured from the last valid address to the first
transition address.
Notes:
10.
CS
and
WE
must be LOW for WRITE cycle.
11. If
CS
goes HIGH simultaneously with
WE
high, the output remains
in a high impedance state.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CS
CS
CS
CS
CONTROLLED)
(10)
Sym.
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time from
End of Write
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
-10
Min
10
8
8
0
8
0
5
0
2
Max
5
-12
Min
12
10
10
1
10
1
8
1
2
Max
8
-15
Min
15
11
13
1
11
1
11
1
2
Max
12
-20
Min
20
13
16
1
13
1
13
1
3
Max
15
-25
Min
25
15
20
2
15
2
15
2
3
Max
20
AC CHARACTERISTICS--WRITE CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
-35
Min
35
20
25
2
20
2
20
2
3
Max
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
ADDRESS
CS
t
WC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT
DATA UNDEFINED
(12)
(8)
t
CW
t
AW
t
WP
t
DW
t
WR
t
AH
t
DH
t
OW
t
AS
t
WZ
(8, 11)
t
t
WE
ADDRESS
CS
DATA OUT
DATA IN
t
WC
HIGH IMPEDANCE
(12)
t
AS
t
CW
t
AW
t
WP
DW
AH
WR
t
DH
t
DATA VALID
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