109
P4C163/163L
P4C163/P4C163L
ULTRA HIGH SPEED 8K x 9
STATIC CMOS RAMS
DESCRIPTION
The P4C163 and P4C163L are 73,728-bit ultra high-speed
static RAMs organized as 8K x 9. The CMOS memories re-
quire no clocks or refreshing and have equal access and
cycle times. Inputs are fully TTL-compatible. The RAMs op-
erate from a single 5V
10% tolerance power supply. With
battery backup, data integrity is maintained for supply volt-
ages down to 2.0V. Current drain is 10
A from a 2.0V supply.
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
25/35ns (Commercial)
25/35/45ns (Military)
Low Power Operation (Commercial/Military)
690/800 mW Active 25
193/220 mW Standby (TTL Input)
5.5 mW Standby (CMOS Input) P4C163L
Output Enable and Dual Chip Enable Control
Functions
Single 5V
10% Power Supply
Data Retention with 2.0V Supply, 10
A Typical
Current (P4C163L Military)
Common I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
28-Pin 300 mil DIP, SOJ
28-Pin 350 x 550 mil LCC
28-Pin CERPACK
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
Means Quality, Service and Speed
1Q97
A
INPUT
DATA
CONTROL
ROW
SELECT
73,728-BIT
MEMORY
ARRAY
COLUMN I/O
A
A
A
I/O
1
I/O
9
COLUMN
SELECT
8
12
0
7
OE
WE
CE1
CE2
DIP (P5, C5), SOJ (J5)
CERPACK (F4) SIMILAR
TOP VIEW
Access times as fast as 25 nanoseconds are available, per-
mitting greatly enhanced system operating speeds. CMOS
is used to reduce power consumption in both active and
standby modes.
The P4C163 and P4C163L are available in 28-pin 300 mil
DIP and SOJ and 28-pin 350 x 550 mil LCC packages provid-
ing excellent board level densities.
A
2
A3
A
5
A
6
A
7
A
8
1
I/O
2
CE
CE
2
A
12
A
11
A
10
GN
D
A
0
A
1
V
CC
26
25
24
23
22
21
20
4
5
6
7
8
9
10
11
12
19
18
13
17
3
27
1
15
2
14
28
16
I/O
3
A
9
OE
I/O
9
I/O
8
WE
I/
O
4
I/
O
5
I/
O
6
I/
O
7
A
4
1
I/O
A
1
A0
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
11
A
9
CE
2
I/O
I/O
I/O
GND
WE
10
A
A
12
OE
V
CC
2
3
4
1
I/O
9
I/O
8
I/O
I/O
6
I/O
5
7
A
2
LCC (L5)
TOP VIEW
110
P4C163/163L
MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Pin with
0.5 to +7
V
Respect to GND
Terminal Voltage with
0.5 to
V
TERM
Respect to GND
V
CC
+0.5
V
(up to 7.0V)
T
A
Operating Temperature
55 to +125
C
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under
55 to +125
C
Bias
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
Ambient
Temperature
Commercial
0
C to +70
C
0V
5.0V
10%
Grade
(2)
GND
V
CC
Grade
(2)
GND
V
CC
Ambient
Temperature
Military
55 to +125
C
0V
5.0V
10%
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
P4C163
P4C163L
Min
Max
Min
Max
V
IH
Input High Voltage
2.2
V
CC
+0.5
2.2
V
CC
+0.5
V
V
IL
Input Low Voltage
0.5
(3)
0.8
0.5
(3)
0.8
V
V
HC
CMOS Input High Voltage
V
CC
0.2 V
CC
+0.5
V
CC
0.2 V
CC
+0.5
V
V
LC
CMOS Input Low Voltage
0.5
(3)
0.2
0.5
(3)
0.2
V
V
CD
Input Clamp Diode Voltage
V
CC
= Min., I
IN
= 18 mA
1.2
1.2
V
V
OL
Output Low Voltage
I
OL
= +8 mA, V
CC
= Min.
0.4
0.4
V
(TTL Load)
V
OLC
Output Low Voltage
I
OLC
= +100
A, V
CC
= Min.
0.2
0.2
V
(CMOS Load)
V
OH
Output High Voltage
I
OH
= 4 mA, V
CC
= Min.
2.4
2.4
V
(TTL Load)
V
OHC
Output High Voltage
I
OHC
= 100
A, V
CC
= Min.
V
CC
0.2
V
CC
0.2
V
(CMOS Load)
I
LI
Input Leakage Current
V
CC
= Max.
Mil.
10
+10
5
+5
A
V
IN
= GND to V
CC
Com'l.
5
+5
N/A
N/A
I
LO
Output Leakage Current
V
CC
= Max.,
CE
= V
IH
,
Mil.
10
+10
5
+5
A
V
OUT
= GND to V
CC
Com'l.
5
+5
N/A
N/A
Symbol
Parameter
Test Conditions
Unit
Symbol
Parameter
Conditions Typ. Unit
C
IN
Input Capacitance
V
IN
= 0V
5
pF
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25
C, f = 1.0MHz)
Symbol
Parameter
Conditions Typ. Unit
C
OUT
Output Capacitance
V
OUT
= 0V
7
pF
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than 3.0V and
100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
111
P4C163/163L
POWER DISSIPATION CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
P4C163
P4C163L
Min
Max
Min
Max
I
CC
Dynamic Operating
V
CC
= Max., f = Max.,
Mil.
--
145
--
145
mA
Current 25
Outputs Open
Com'l.
--
125
--
N/A
I
CC
Dynamic Operating
V
CC
= Max., f = Max.,
Mil.
--
120
--
120
mA
Current 35, 45
Outputs Open
Com'l.
--
95
--
N/A
I
SB
Standby Power Supply
CE
1
V
IH
or
Mil.
--
40
--
40
mA
Current (TTL Input Levels) CE
2
V
IL
, V
CC
= Max.,
Com'l.
--
35
--
N/A
f = Max., Outputs Open
I
SB1
Standby Power Supply
CE
1
V
HC
or
Mil.
--
20
--
1
mA
Current
CE
2
V
LC
, V
CC
= Max.,
Com'l.
--
18
--
N/A
(CMOS Input Levels)
f = 0, Outputs Open,
V
IN
V
LC
or V
IN
V
HC
V
CC
t
CDR
4.5V
V
DR
2V
4.5V
t
R
DATA RETENTION MODE
V
HC
V
DR
CE
CE
1
2
V
LC
V
HC
V
LC
DATA RETENTION WAVEFORM
Symbol
Parameter
Test Conditions
Unit
n/a = Not Applicable
DATA RETENTION CHARACTERISTICS (P4C163L, Military Temperature Only)
Typ.*
Max
Symbol
Parameter
Test Condition
Min
V
CC
=
V
CC
=
Unit
2.0V
3.0V
2.0V
3.0V
V
DR
V
CC
for Data Retention
2.0
V
I
CCDR
Data Retention Current
10
15
200
300
A
t
CDR
Chip Deselect to
0
ns
Data Retention Time
t
R
Operation Recovery Time
t
RC
ns
*T
A
= +25
C
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
CE
1
V
CC
0.2V or
CE
2
0.2V, V
IN
V
CC
0.2V
or V
IN
0.2V
112
P4C163/163L
Symbol
Parameter
Unit
-25
-35
-45
Min
Max Min Max Min
Max
t
RC
Read Cycle Time
25
35
45
ns
t
AA
Address Access Time
25
35
45
ns
t
AC
Chip Enable
25
35
45
ns
Access Time
t
OH
Output Hold from
3
3
3
ns
Address Change
t
LZ
Chip Enable to
3
3
3
ns
Output in Low Z
t
HZ
Chip Disable to
10
15
20
ns
Output in High Z
t
OE
Output Enable
13
18
20
ns
Low to Data Valid
t
OLZ
Output Enable
3
3
3
ns
Low to Low Z
t
OHZ
Output Enable
12
15
20
ns
High to High Z
t
PU
Chip Enable to
0
0
0
ns
Power Up Time
t
PD
Chip Disable to
20
20
25
ns
Power Down Time
AC ELECTRICAL CHARACTERISTICS--READ CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
OLZ
ADDRESS
OE
t
RC
DATA OUT
(9)
t
AA
t
OE
t
OH
CE
CE
1
2
t
LZ
t
AC
t
HZ
t
OHZ
t
(8)
(8)
(8)
(8)
READ CYCLE NO. 1 (
OE
OE
OE
OE
OE
CONTROLLED)
(5)
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
1
transition
LOW and CE
2
transition HIGH.
8. Transition is measured
200mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
113
P4C163/163L
t
ADDRESS
DATA OUT
AA
t
t
OH
DATA VALID
PREVIOUS DATA VALID
(9)
RC
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether
CE
1
or CE
2
causes them.
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
READ CYCLE NO. 3 (
CE
CE
CE
CE
CE
1
, CE
2
CONTROLLED)
(5,7,10)
t
CE
DATA OUT
AC
t
RC
t
LZ
DATA VALID
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
(8,10)
(8,10)
t
HZ
SUPPLY
CC
CURRENT
V
CE
(10)
(10)
(10)
2
1
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