63
P4C188/188L
DESCRIPTION
The P4C188 and P4C188L are 65,536-bit ultra high speed
static RAMs organized as 16K x 4. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. Inputs and outputs are fully TTL-compatible.
The RAMs operate from a single 5V
10% tolerance power
supply. With battery backup, data integrity is maintained for
supply voltages down to 2.0V. Current drain is typically 10
A from a 2.0V supply.
Single 5V
10% Power Supply
Data Retention with 2.0V Supply
(P4C188L Military)
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
22-Pin 300 mil DIP
24-Pin 300 mil SOJ
22-Pin 290 x 490 mil LCC
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
10/12/15/20/25 ns (Commercial)
12/15/20/25/35 (Industrial)
15/20/25/35/45 ns (Military)
Low Power (Commercial/Military)
715 mW Active 12/15
550/660 mW Active 20/25/35/45
193/220 mW Standby (TTL Input)
83/110 mW Standby (CMOS Input) P4C188
15 mW Standby (CMOS Input)
(P4C188L Military)
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
P4C188/P4C188L
ULTRA HIGH SPEED 16K x 4
STATIC CMOS RAMS
I/O
A
4
A
7
A
0
A
1
A
2
A
3
A
5
A
6
A
13
A
12
A
11
A
10
A
9
I/O
4
3
2
1
V
CC
A
8
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
WE
I/O
I/O
A
CE
A
GND
I/O
2
3
I/O
4
I/O
A
7
A
6
A
5
A
4
A
3
3
4
5
6
7
8
9
22
A
1
A
0
V
CC
A
13
10
11 12
CE
GND
WE
1
21
2
13
A
2
A
A
A
18
17
16
15
14
19
20
A
11
A
10
A
9
A
12
A
8
I/O
1
DIP (P3, D3)
TOP VIEW
LCC (L3)
TOP VIEW
For SOJ pin configuration, please see Selection Guide Page.
A
CE
WE
INPUT
DATA
CONTROL
ROW
SELECT
65,536-BIT
MEMORY
ARRAY
COLUMN I/O
A
A
A
(8)
(6)
I/O
1
I/O
2
I/O
3
I/O
4
COLUMN
SELECT
Means Quality, Service and Speed
1Q97
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption to a low 715mW
active, 193mW standby and only 5mW in the P4C188L
version.
The P4C188 and P4C188L are available in 22-pin 300 mil
DIP, 24-pin 300 mil SOJ and 22-pin LCC packages provid-
ing excellent board level densities.
64
P4C188/188L
MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Pin with
0.5 to +7
V
Respect to GND
Terminal Voltage with
0.5 to
V
TERM
Respect to GND
V
CC
+0.5
V
(up to 7.0V)
T
A
Operating Temperature
55 to +125
C
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under
55 to +125
C
Bias
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Industrial
Commercial
Grade(2)
Ambient
Temperature
GND
V
CC
40
C to +85
C
0
C to +70
C
0V
0V
5.0V
10%
5.0V
10%
0V
5.0V
10%
55
C to +125
C
Military
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
5
7
Unit
pF
pF
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25
C, f = 1.0MHz
n/a = Not Applicable
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than 3.0V and
100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Typ.
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE
V
IH
Mil.
V
CC
= Max ., Ind./Com'l.
f = Max., Outputs Open
___
___
40
35
___
___
___
___
20
15
40
n/a
2.7
n/a
mA
mA
___
___
CE
V
HC
Mil.
V
CC
= Max., Ind./Com'l.
f = 0, Outputs Open
V
IN
V
LC
or V
IN
V
HC
Standby Power Supply
Current
(CMOS Input Levels)
I
SB1
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
Test Conditions
V
CC
= Min., I
IN
= 18 mA
I
OL
= +8 mA, V
CC
= Min.
I
OH
= 4 mA, V
CC
= Min.
V
CC
= Max. Mil.
V
IN
= GND to V
CC
Com'l.
V
CC
= Max.,
CE
= V
IH
, Mil.
V
OUT
= GND to V
CC
Com'l.
P4C188
Min
2.2
0.5
(3)
V
CC
0.2
0.5
(3)
2.4
10
5
10
5
Max
V
CC
+0.5
0.8
V
CC
+0.5
0.2
1.2
0.4
+10
+5
+10
+5
P4C188L
Min
Max
2.2
0.5
(3)
V
CC
0.2
0.5(3)
2.4
5
n/a
5
n/a
V
CC
+0.5
0.8
V
CC
+0.5
0.2
0.4
1.2
+5
n/a
+5
n/a
Unit
V
V
V
V
V
V
V
A
A
65
P4C188/188L
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
DATA RETENTION CHARACTERISTICS (P4C188L Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
V
CC
0.2V,
V
IN
V
CC
0.2V or
V
IN
0.2V
Min
2.0
0
t
RC
Typ.*
V
CC
=
2.0V 3.0V
10
15
Max
V
CC
=
2.0V 3.0V
600
900
Unit
V
A
ns
ns
DATA RETENTION WAVEFORM
*T
A
= +125
C
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
V
CC
V
IH
t
CDR
4.5V
V
DR
2V
4.5V
t
R
V
DR
V
IH
DATA RETENTION MODE
CE
I
CC
Symbol
Parameter
Temperature
Range
Dynamic Operating Current*
Commercial
Industrial
Military
10
N/A
12
15
20
25
35
45
Unit
N/A
mA
mA
mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
N/A
150
155
160
170
180
N/A
170
160
155
150
145
180
170
160
155
150
N/A
N/A
66
P4C188/188L
AC CHARACTERISTICS--READ CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
Notes:
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured
200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
TIMING WAVEFORM OF READ CYCLE NO. 1
(5)
ADDRESS
DATA OUT
t
AA
DATA VALID
PREVIOUS DATA VALID
(8)
t
OH
t
RC
t
CE
DATA OUT
AC
t
RC
t
LZ
DATA VALID
I
CC
I
SB
t
PU
HIGH IMPEDANCE
t
PD
(7)
(7)
t
HZ
SUPPLY
CC
CURRENT
V
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down
Time
-10
Min
10
2
2
0
Max
10
10
5
10
-12
Min
12
2
2
0
Max
12
12
6
12
-15
Min
15
2
2
0
Max
15
15
6
15
-20
Min
20
2
3
0
Max
20
20
8
20
-25
Min
25
2
3
0
Max
25
25
10
25
-35
Min
35
2
3
0
Max
35
35
20
35
-45
Min
45
2
3
0
Max
45
45
25
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
67
P4C188/188L
ADDRESS
CE
t
WC
DATA VALID
HIGH IMPEDANCE
WE
DATA IN
DATA OUT
DATA UNDEFINED
(11)
(12)
t
CW
t
AW
t
WP
t
DW
t
WR
t
AH
t
DH
t
OW
t
AS
t
WZ
(10, 12)
12. Transition is measured
200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE
WE
WE
WE
CONTROLLED)
(9)
AC CHARACTERISTICS - WRITE CYCLE
(V
CC
= 5V
10%, All Temperature Ranges)
(2)
Sym.
Parameter
-10
-12
-15
-20
-25
-35
-45
Unit
Min
Min
Min
Min
Min
Min
Min
Max
Max
Max
Max
Max
Max
Max
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
DW
Write Cycle Time
Chip Enable
Time to
End of Write
Address Valid
to End of Write
Address
Set-up Time
Write Pulse
Width
Address Hold
Time from
End of Write
Data Valid to
End of Write
Data Hold
Time
Write Enable
to Ourput in
High Z
Output Active
from End
of Write
10
7
7
0
8
0
5
0
2
5
12
8
8
0
9
0
6
0
2
6
13
10
10
0
10
0
7
0
2
6
20
13
15
0
13
0
8
0
2
8
25
15
20
0
15
0
10
0
2
35
25
25
0
25
0
15
0
3
15
45
35
35
0
35
0
20
5
3
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
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